26th International Conference on VLSIJanuary 2013

Pune,India

Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply

VoltagesVijay Sheshadri, Vishwani D. Agrawal, Prathima

Agrawal

Outline

• Introduction– Problem Statement

• Integer Linear Programming (ILP)– ILP: Variable test clock

• Optimum supply voltage– Results for ASIC Z

• Future Work• Conclusions

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Introduction

• Technology scaling has led to more cores and increased complexity in SoC devices.– This has resulted in high test data volumes

and longer test times.– Reducing test time is one of the major

objectives in SoC testing

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Problem Statement

• Given an SoC with N core tests and a peak power budget, find a test schedule to:– Test all cores.– Maximize concurrency to reduce test time.– Conform to power budget by restricting

concurrency.

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An Example – ASIC Z

• Y. Zorian, “A distributed control scheme for complex VLSI devices,” VTS’93, pp. 4–9.

• Often used as benchmark for SoC test scheduling.

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RAM 2(61,241)

RAM 3(38,213)

ROM 1(102,279)

ROM 2(102,279)

RAM 1(69,282)

RAM 4(23,96)

Reg. file(10,95)

Random logic 1 (134, 295)

Random logic 2 (160, 352)

Pmax= 900

Block(time, power)

Blocks of ASIC Z, and their test time (in a.u.) and test power (in mW)

An Example – ASIC Z

• Comparison of existing optimal test schedules for ASIC Z.

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Test Session Chou et al.[1] Larsson and Peng[2]

Test Time Blocks Test Time Blocks

1 69 RAM1,RAM3,RAM4,RF 160 RL2,RL1,RAM2

2 160 RL1,RL2 102 RAM1, ROM1, ROM2

3 102 ROM1,ROM2,RAM2 38 RAM3, RAM4,RF

331 300

[1] R. M. Chou et al, “Scheduling tests for vlsi systems under power constraints,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp. 175–185, 1997.

[2] E. Larsson and Z. Peng, “An integrated framework for the design and optimization of soc test solutions,” JETTA Spl. Ed., vol. 18, pp. 385–400, 2002

Integer Linear Progam (ILP)

• Given:– Power budget for SoC, Pmax

– N core tests for an SoC.• ti = test time and pi = test power of ith test

– K sessions in the test schedule for N core tests.

• Test time of jth session is, Tj = max{ti}

• Test power of jth session is, Pj = ∑ (pi)

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Variable Test Clock Frequency

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• Selectable clock frequency for each test session.

• Increasing test clock frequency by a factor f =>

Test time, and Test power,

• Proper choice f for each session (ref. to as frequency factor) can optimize overall test time.

€

T j →T j

f

€

Pj → f × Pj

• Objective:Minimize , where

• Subject to:– Power constraint: – Test completeness constraint:

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ILP: Variable Test clock

€

T j

Fj

⎛ ⎝ ⎜

⎞ ⎠ ⎟× x j

∀sessions

∑

€

jx =0, if thj session is ignored

1, if thj session is scheduled

{

€

jP ×jF ×

jx ≤maxP , ∀ sessions

€

x j

j∈{sessions including core i}

∑ ≥ 1, ∀core tests

Frequency Factor

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• Fj = Frequency factor of jth session.

• Frequency factor limited by:– Pmax (Power Constraint)

– Max. speed of slowest core in session

• For simulation, max. clock frequency values assigned to ASIC Z blocks.

€

F j =freq. of j th test session

freq. of slowest test session

ASIC Z Results

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Slower clock Faster clock

Nominal clock

Prev. Best Optimal Solution

Constraints on Frequency

• Each core’s max. clock rate decided by:– Max. power limit of core (power constraint)– Critical path delay (structural constraint)

• Both constraints also influenced by VDD.

– Power Constraint:

– Structural constraint:

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€

Pcore ∝VDD2 • f

€

delay∝VDD

VDD − VTH( )α

(also known as Alpha power law)

Influence of VDD on Test time

• Power constrained test:

• Structure constrained test:

• An optimal VDD can balance the two constraints.

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€

As VDD ↓, Pcore ↓⇒ TCLK ↑, Test time ↓

€

As VDD ↓, delay ↑⇒ TCLK ↓, Test time ↑

Optimal VDD Selection

• Experiments on ISCAS circuits show upto 62% improvement in test time at optimal VDD

[3].

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[3] P. Venkataramani and V. D. Agrawal, “Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage.” Proc. VLSID, in press, Jan. 2013.

Simulation and experimental test time plots for s298[3]

Optimal VDD Selection for SoC

• Clock frequency of a test session may be power constrained or structure constrained.– If power constrained, lowering VDD improves

test time.– If structure constrained, lowering VDD

deteriorates test time.

• Objective: To find optimal VDD for power constrained test sessions, thereby reduce overall test time.

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ASIC Z Results Revisited

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Slower clock

Faster clock

Nominal clock

Prev. Best Optimal Solution

Saturates at 268.3 time units.

Point A

• Cannot further reduce time by increasing Frequency factor.– Limited by frequency constraints.

Assumptions

• At Point A:– All test session frequencies are power

constrained.– Structural constraint limit >> power

constraint limit.– Nominal VDD = 1V, VTH = 0.5V, α = 1

• All cores can be tested at same voltage.– Optimal VDD same for all cores.

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Optimal VDD for ASIC Z

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Power constrained test

Structure constrained test

Optimum VDD

• 42% reduction in overall test time at optimal VDD .

Optimal VDD for ASIC Z

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• Margin between the constraints impacts test time reduction.

SC >> PC

SC > PC

SC = PCSC = Structural Constraint limitPC = PowerConstraint limit

Next Steps

• Not all test sessions are power constrained.– Identify and include only power constrained

test sessions in ILP.• Different cores may be tested at different

voltages.– Include voltage range for each core.

• Optimum VDD for each test session.

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Conclusion

• Test time minimized by optimizing supply voltage and customizing test clock rate.

• Proposed method demonstrated on ASIC Z.– 48% improvement over existing solution

(300 time units).• Main assumption:

– Voltage and frequency characteristics of all cores similar.

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