2nd sem syllabi

8/2/2019 2nd Sem Syllabi

1/5

Embedded Computing System

Unit1:

Circuits and DSP Architecture: Circuit Design basics, Deep Submicron issues, low power techniques, Highlevel power models, algorithm transformation techniques, dedicated architectures for embeddedsystems.

Unit2:

Architectures Design: Embedded Processor architectures, architectural techniques for low power designmethods for core based ASICs.

Unit3:

Compiler and OS: Introduction to compiler optimization, power models for compiler optimizations, coresize vs. performance/power trade off.

Unit4:

DSP algorithm Design: A/D conversion and finite precision analysis, algorithms for embedded systems,source and channel processing, portable embedded code.

Unit5:

Networking: Networking Basics (addressing and routing), wireless vs, wire-line networking, distributedOS for networked embedded systems, Case study of JINI

Text books:

1. K.Hwang, advanced computer architecture: Parallelism, scalability and programmability, NewYork McGraw Hill Inc.

2. S.Y. Kung, VLSI array Processor, Prentice Hall.


2/5

VLSI TESTING AND TESTABILITY:

Unit1:

Defects and their modeling as faults at gate level and transistor level, Various types of faults, Functionalvs. Structural approach to testing.

Unit2:

Complexity of testing problem, controllability of observability, Generating test for a single stuck at faultin combinational logic, D-A algorithm.

Unit3:

FAN and PODEM Algorithm, Test optimization and fault coverage, The problem of testing of sequentialDFT hardware.

Unit4:

Adhoc and structured approaches of DFT, Various kinds of scan design, Fault models for PLAs, Bridgingand delay faults and their tests.

Unit5:

Memory testing, Testing with random patterns, The LFSR and their use in random test generation andresponse compression ( including MISRS) , built in self test.

Text books:

1. M.Abramoviel, M.A. Breuer and A.D. Friedman, Digital System Testing and Testable Design 2. V. Agrawal and S.C Seth, Test Generation for VLSI chips


3/5

Architecture of DSP

Unit1

Digital Signal Processors: The Programmable DSP architecture, top-down design of dedicated DSPs, ALibrary based Systems Design Environment.

Unit2:

Classification of Architectures: An Abstract Computing Machine, Optimization of performance,interconnection between Functional Units, A Multilevel classification

Unit3:

Data and Instruction Memories: SISC Architectures, Addressing modes, External Interface Units,

VLSI SISC Processors: The SISC Processor, Pipeline control in SISCs, Superscalar Processors

Unit4:

Data Path Logic Design: Introduction, Synchronous Data path design, Monolithic arithmetic circuits,Implementation of pipeline, High level Synthesis(HLS) of data path, Low Power data design, floatingpoint arithmetic.

Unit5:

Rapid Prototyping: Introduction, Highlevel Languages(HLLs) in DSP, hardware descriptionlanguagesa(HDLs), Optimizing compilers, DSP prototyping environment, Real-Time SISC prototyping.

Text books:

1. Vijay k. Madisetti, VLSI Digital Signal Processors An introduction to Rapid prototyping andDesign Syn thesis .

2. Richard J. Higgins, Digital Signal Processing in VLSI , Prentice hall.

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4/5

Low Power VLSI Design

Unit1Analysis of components of power dissipation in digital circuit techniques for low power attechnology level.

Unit2:Techniques for low power design at logic design level (analysis of various logic styles for theirpower consumption).

Unit3Low power design techniques at system levels.

Unit5:Power consumption of dedicated hardware vs. software implementation of systems

Text books:

1. A.P Chanrakasan and R.W Broderson, Low power CMOS design2. J.B Kuo and J.H. Lou, Low voltages cmos vlsi circuits.


5/5

VLSI CAD

Unit1

Introduction: VLSI design flow, challenges, Verilog/VHDL : Introduction and use in synthesis , modelingcombinational and sequential logic, writing test benches.

Unit2

Logic Synthesis: two-level and multilevel gate-level optimization tools, state assignment of finite statemachines.

Unit3

Basic concepts of high-level synthesis: Hierarchical view of VLSI Design, Arichitectural design, High levelsynthesis

Unit4

Basic Concepts of high-level synthesis: Scheduling data path synthesis, Logic Synthesis, Minimizationtechniques, circuit design and simulation

Unit5

Basic concepts of high-level synthesis: Layout synthesis, placement and routing , DRC, silicon compiler,Array processors.

Text Books:

1. S. Palanitkar, Verilog HDL : A guide to digital design and synthesis, second edition , prentice hall,2003

2. G. De Micheli, Synthesis and Optimization of Digital ciruits3. S.H. Gerez, Algorithm for VLSI DESIGN Automation , Wiley. 4. N.Sherwani Algorithm for VLSI physical AutomationThird edition, Kluwer.

2nd sem syllabi

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