3 dt soln -...

1013/SY/Pre_Pap/Comp/DT_Soln58

Vidyalankar S.Y. Diploma : Sem. III

[CO/CM/IF/CD/CW] Digital Techniques

Prelim Question Paper Solution

(i) (1) 101110 (2) 101010 1s COMPLEMENT 010001 1s COMPLEMENT 010101

2s COMPLEMENT 2s COMPLEMENT

(ii) (1) (2)

(iii) 11011 00011 1’s complement 11100 00100 2’s complement

1’s complement 00011 11011 11011

+ 00011 + 00100 11110 11111

+ 1 11111

(iv) Logic Symbol and Truth table for 2i/p NAND gate

(v) i) Commutative Laws : The laws of commutation allow us to arrange variables in any order without changing the result. With two variables A and B, these are given by

A + B = B + A A • B = B • A

ii) Associative Laws : Associative laws define the order in which theoperations are performed. In both the OR and the AND operations, thegrouping does not affect the result. This gives identities such as

For the OR operation : (A + B) + C = A + (B + C) .

For the AND operation : (A B) C = A (B C)

1. (a)

010001 + 1 010010

010101 + 1 010110

1. (a) 1 1 0 1 0 0 1

6 9 = (69)H

1 0 1 0 1 1

2 B = (2B)H

1. (a)

1. (a)

1. (a)

A

B

y

Symbol

Truth Table

A B y 0 0 1 0 1 1 1 0 1 1 1 0

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1013/SY/Pre_Pap/Comp/DT_Soln 59

iii) Distributive Laws : The distribution of AND and OR operations is governed by the following laws. It is important to remember the rule of precedence that, within a grouping, the AND operation always precedes the OR. The two important distributive laws are given by

A (B + C) = (A B) + (A C) A + (B C) = (A + B) (A + C)

(vi) Theorem 1 : A B = A B The NOR operation is equivalent to ANDing the complements of the inputs.

Theorem 2 : (A B) A B The NAND operation is equivalent to ORing the complements of the inputs.

(vii) Full subtractor symbol and truth table Truth table for a full subtractor

Inputs Outputs A

(minuend) B

(Subtrahend) Bin

Previous borrow

(A B Bin) Difference Borrow

0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

(viii) Flip flop can be considered as a basic memory cell because it stores the

value on the data line with the advantage of the output being synchronized to a clock.

Example :

1. (a)

1. (a)

A

B

Diff

Borrow

Bin

1. (a)

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Vidyalankar : S.Y. Diploma DT


The clocked RS flip-flop shown above. It is basically the S - R flip-flop using

NAND gates with an ad “clock” input. It is also called as level triggered SR-FF. The outputs of simple RS flip-flop used to change instantly in response to

any change made at the input. But this doesn’t happen with the clocked S R flip-flop.

For this circuit, the change in output will take place if and only if the clock

input is made active i.e Clk=1. In short, this circuit will operate as an SR flip-flop if clock = 1 but there is no change in the outputs if clock = 0.

(i) Draw pin configuration of TTL IC’s used for AND gate and NAND gate. 7408(AND) Pin Diagram:

1. (b)

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7400(NAND): Pin Diagram:

(ii)

(iii) Half Adders Half adder is a combinational logic circuit with two inputs and two outputs. It

is the basic building block for addition of two “single” bit numbers. This circuit has two outputs “carry” and “sum”.

1. (b)

1. (b)

2 : 1 MUX

Dout D0

D1

S0

S0 Dout

0 D0

1 D1

8 : 1 MUX

Dout

D0

D7

S0

S1 S2

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(i) Propagation delay (or speed of operation)

The delay times are measured between the 50 % voltage levels of input and output waveforms.

There are two delay times tPHL when output goes from High to Low tPLH when output goes from Low to High Propagation delay is average of above two delay times. (ii) Power Dissipation Power dissipation in ICs is the process in which IC consumes electrical

energy and dissipate this energy both by the action of switching devices and by energy lost in the form of heat due to impedance of electronic circuits.

(iii) Noise immunity (or Noise margin) The input & output voltage levels

defined above are shown in figure. Stray electric and magnetic fields

may induce unwanted voltages, known as noise, on the connecting wires between logic circuits. This may cause the voltage at the input to a logic circuit to drop below V1H or rise above V1L and may produce undesired operation.

The circuit’s ability to tolerate noise signals is referred to as the noise immunity, a

quantitative measure of which is called noise margin. There are two types of noise margins. (a) High level noise margin (NMH) NMH = V0H V1H

(b) Low level noise margin (NML) NML = V1L V0L (iv) Fan in The total number of inputs connected to the gate is called as fan in of the

gate. fan in = 3

2. (a)

Input

Output

50 %

50 %

tPHL tPLH

0V0L

V0H

V1H

V1L

1 state noise margin

0 state noise margin

Voltages

V0H V1H

V1L V0L

Y ABC

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(i) 10110 1010 using 1’s complement method. 10110 1010 01010 10101 1’s complement 10110 + 10101 101011 + 1 01100 (ii) 11010 11110 using 2’s complement method. 11010 11110 11110 00001 1’s complement 00010 2’s complement 11010 + 00010 11100 Prove that : YZ WXZ WXYZ WYZ Z LHS = YZ WXZ(Y Y) WXYZ WYZ

= YZ WXYZ WXYZ WXYZ WYZ

= YZ WYZ(X X) WXYZ WYZ

= YZ WYZ WXYZ WYZ

= YZ(1 WX) WYZ WYZ

= YZ WYZ WYZ

= YZ (W W)YZ

= YZ YZ

= (Y Y)Z

= Z K-map for Y = M (1, 3, 5, 7, 9, 11, 13, 15) From K-map we get Y = D

2. (b)

2. (c)

2. (d)

00 01 11 10

00

01 0 0 0 0

11 0 0 0 0

10

AB CD

D Y = D

Logical Diagram :

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Comparison between Static RAM and Dynamic RAM Static RAM Dynamic RAM

i)

Can be constructed by using either unipolar or bipolar components

Can be constructed by using unipolar (MOSFET) components only.

ii)

Packing density is less hence less data can be accommodated.

Packing density is very large & hence large data can be accommodated.

iii)

Basic element of storing the data if F/F.

The data is stored in the inherent capacitor of MOSFETS.

iv)

Data stored permanent can be allowed & no refreshing operation is necessary.

Refreshing of the stored data after every few milli sec. is essential.

v) Transmission gates are not used. Transmission gates are used in the circuit, which can conduct in both the direction.

vi) More costly Less costly

Diagram of binary weighted DAC and its working

Characteristics of ECL logic families. Some of the most important ECL characteristics are as follows : i) Maximum propagation delay : for the latest ECL gates the propagation delay

is very short, of the order of 500 ps. ii) Average power dissipation : 5 mW (for advanced ECL gates) iii) Speed-power product (SPP) : 0.5pJ. iv) Worst case noise margin is only 150 mV. So ECL device are unreliable to

work in noisy environments. v) ECL devices generally produce an output an its complement (e.g. OR/NOR).

So additional inverter is necessary. vi) Due to emitter follower stages, the output impedance is very low. vii) Due to low output impedance, the fan out is typically equal to 25. viii) Typical power dissipation for the standard ECL gate is 25 mW which is

somewhat higher than that of 74 AS series. ix) The current flowing in ECL circuits remains almost constant so no current

transients are observed and so associated noise also is less.

2. (e)

2. (f)

(Reference voltage)

Binary weighted resistors

3. (a)

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(i) 0110 + 0111 (ii) 1001 + 1001 Symbol, logical equation and truth table of 3 i/p AND gate and 3 i/p OR gate

Arithmetic Logic Unit (ALU) ALU is a very widely used and popular combinational circuit. It is capable of performing the arithmetic as well as the logic operations. ALU is the heart of any microprocessor. 74181 is a 24-pin IC in dual in line (DIP) package.A (A0-A3 and B (B0-B3)

are the two 4 bit variables. It can perform a total of 16 arithmetic operations which includes addition, subtraction, compare and double operations. It provides many logic operations such as AND, OR, NOR, NAND, EX-OR, compare, etc. on the two four bit variables.

74181 is a high speed 4 bit parallel ALU. It is controlled by four function select inputs (S0-S3). These lines can select 16 different operations for one mode (arithmetic) and 16 another operations for the other mode (logic). M is

3. (b)

D 0110 C = (6)10 + 0111 7 = (7)10 1101 110

1 0011

(1 3)10

1001 1 = (9)10 + 1001 1 = (9)10 0010 110

1 1000 (1 8)10

3. (c)

A

B

C

y

y = A + B + C

B

A

C

y

y = A . B . C

3. (d)

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the mode control input. It decides the mode of operation to be either arithmetic or logic.

Mode M = 0. For arithmetic operations. M = 1 For logic operations. G and P outputs are used when a number of 74181 circuits are to be used in

cascade alongwith 74182 the look ahead carry generator circuit to make the arithmetic operations faster.

Function Table for IC 74181with active high data and Cn =1

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Case 1: LED ON CQ = 1 QC = 0 J = 0 QB = 0 R = 1 D = 1

Case 2: LED OFF CQ = 0 QC = 1 J = 1 QB = 1 R = 0 D = 0

001 = 0.2 V = RV8

= VR = 1.6 V

i) 100 = R4.V8

= RV2

= 0.8V

ii) 110 = R5V8

= 5 1.6

8´

= 1V

The dual of AND is OR and the dual of OR is AND. According to the duality theorem the following conversions are possible in a given Boolean expression. i) Change each AND operation to an OR operation. ii) Change each OR operation to an AND operation. iii) Complement any 1 or 0 appearing in the expression.

Duality theorem is sometimes useful in creating new expressions from the given Boolean expressions. Universal Gate NAND and NOR are referred to as Universal Logic Gates since all the basic logic gates can be constructed using either the NAND or NOR logic gates only.

3. (e)

3. (f)

4. (a)

4. (b)

I/P D QA

AQ

QB

BQ

QC

CQ

R

S

J

K

LED

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1 : 4 demux using NAND gate Function Table

Input Output

DIN S0 S1 Y0 Y1 Y2 Y3

E 0 0 E 0 0 0

E 1 0 0 E 0 0

E 0 1 0 0 E 0

E 1 1 0 0 0 E

Table (SN54/74LS48)

4. (c)

4. (d)

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1) BI / RBO is wired-AND logic, serving as blacking input (BI) and/or ripple-blacking output (RBO). The blacking out (BI) must be open or held at a HIGH level when output functions 0 through 15 are desired, and ripple-blacking input (RBI) must be open or at a HIGH level if blacking of a decimal 0 is not desired. X-input may be HIGH or LOW.

2) When a LOW level is applied to the blacking input (forced condition) all segment outputs go to a LOW level, regardless of the state of any other input condition.

3) When ripple-blacking input (RBI ) and inputs A, B, C and D are at LOW level, with the lamp test input at HIGH level, all segment outputs go to a HIGH level and the ripple-blacking output (RBO) given to a LOW level (response condition).

4) When the blacking input/ripple-blacking output (BI / RBO) is open or held at a HIGH level, and a LOW level is applied to lamp-test input, all segment outputs go to a LOW level.

8:1 multiplexer using basic gates

4. (e)

D4

D5

D6

D7

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(i) 5 Require 4 bits (in 2s complement) 4 F/F required (ii) 83 Require 7 bits 7 F/Fs required (iii) 99 Require 7 bits 7 F/Fs required (iv) 10 Require 4 bits 4 F/F required y = (A + B) (A + C) = A.A + A.C + B.A + B.C = A + A.C + B.A + B.C = A (1 + C) + BA + BC = A (1 + B) + BC = A + BC (i) y = AB + ABC + AB + ABC

= AB (1 + C) + AB + ABC

= AB + AB ABC

= B (A + A ) + ABC

= B + ABC (ii) y = (A + B) (A + B ) A B

= A B.B A B

= (A + 0) A + B = A A B = A . A + AB = 0 + AB = AB Table

A B Carry Sum y S0 S1 0 0 0 0 D0 = 1 0 1 0 1 D1 = 1 1 0 0 1 D1 = 1 1 1 1 0 D2 = 0

5. (a)

5. (b)

5. (c)

y B

C

A

4. (f)

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Truth table of the full adder Figure (a) show the block diagram of 74180. There are 8parity inputs A to H and two cascading inputs. There are two outputs even and odd. And there are two cascading inputs named EVEN and ODD. The pin configuration of IC 74180 is shown Figure (b).

Fig. (a) : Block diagram of 74180. Fig. (b) : Pin configuration of 74180.

5. (d)

Sum

Cout

A

B

C

5. (e)

Cin A B Sum Carry out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1

MUX 1

MUX 2

S

Cout

MUX

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Functional table for 74180 :

Row no. Parity of inputs Cascading inputs Outputs

(A to H) EVEN ODD Even Odd 1 Even 1 0 1 0 2 Odd 1 0 0 1 3 Even 0 1 0 1 4 Odd 0 1 1 0 5 X 1 1 0 0 6 X 0 0 1 1

3-bit synchronous counter Excitation equation of D Flip-flop.

Qn Qn* D 0 0 0 0 1 1 1 0 0 1 1 1

Previous State Next State Excitation equation Count Q2 Q1 Q0 Q2* Q1* Q0* D2 D1 D0

0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 2 0 1 0 0 1 1 0 1 1 3 0 1 1 1 0 0 1 0 0 4 1 0 0 1 0 1 1 0 1 5 1 0 1 1 1 0 1 1 0 6 1 1 0 1 1 1 1 1 1 7 1 1 1 0 0 0 0 0 0

for D2 for D1

D2 = 2 1 0 2 1 2 0Q Q Q Q Q Q Q D1 = 1 0 1 0Q Q Q Q = 1 0Q Q

for D0

Q1 Q0 Q2

00 01 11 10

0 1 0 0 1

1 1 0 0 1

5. (f)

Q1 Q0 Q2

00 01 11 10

0 0 1 0 1

1 0 1 0 1

Q1 Q0 Q2

00 01 11 10

0 0 0 1 0

1 1 1 0 1

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D2 = 0Q

(i) Theorem 1 : (A B) A B

LHS RHS A B A + B A B A B A .B 0 0 0 1 1 1 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0 0 0

Theorem 2 : (A B) A B

LHS RHS A B A B A B A B A .B 0 0 0 1 1 1 1 0 1 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0

(ii) (A + C) (A + D) (B + C) (B + D) = [A + (C . D)] [B + (C . D)] Distributive = (C . D) + (A . B) Distributive = AB + CD Commutative (i) Purpose of encoder and decoder Decoders will have N inputs, and 2Noutput. Let's say that we have two inputs

(A and B), and 4 outputs (M N O P). Decoders will satisfy the following truth table:

A B M N O P 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

Q0 Q0

D

Q1 Q1

D

Q2 Q2

DCl

6. (a)

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Binary numbers come in, and essentially select which wire to send a signal on. Encoders work in exactly the opposite way as decoders, taking 2N inputs,

and having N outputs. When a bit comes in on an input wire, the encoder outputs the physical address of that wire. It takes 2^n inputs and gives out n outputs, the enable pin should be kept 1 for enabling the circuit.

(ii) Encoders Encoders are used to convert decimal numbers to equivalent binary

numbers. An encoder has “n” number of input lines and “m” number of output lines. An encoder produces a ‘m’ bit binary code corresponding to the digital input number.

If we have 2 outputs we can accommodate 4 input 3 outputs we can accommodate 8 input …… ……… … n outputs we can accommodate 2n input lines. The encoder accepts an n input digital word and converts it into a m bit

another digital word. 3-bit R2R ladder DAC The basic theory of the R-2R ladder network is that current flowing through any input resistor (2R) encounters two possible paths at the far end. The effective resistances of both paths are the same (also 2R), so the incoming current splits equally along both paths. The half-current that flows back towards lower orders of magnitude does not reach the op amp, and therefore has no effect on the output voltage. The half that takes the path towards the op amp along the ladder can affect the output. The inverting input of the op-amp is at virtual earth. Current flowing in the elements of the ladder network is therefore unaffected by switch positions.

6. (b)

6. (c)

'm' output lines

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If we label the bits (or inputs) bit 1 to bit N the output voltage caused by connecting a particular bit to Vr with all other bits grounded is:

Vout = rV2N

where N is the bit number. For bit 1, Vout = rV2

, for bit 2, Vout = rV4

etc.

Since an R/2R ladder is a linear circuit, we can apply the principle of superposition to calculate Vout. The expected output voltage is calculated by summing the effect of all bits connected to Vr. For example, if bits 1 and 3 are connected to Vr with all other inputs grounded, the output voltage is calculated by:

Vout = r rV V2 8

which reduces to Vout = r5V8

.

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