DATASHEET

CELTIC

The Cadence® CeltIC™ signal integrity analyzer is a core nanometer technology in

the Cadence® Encounter™ digital IC design platform. It identifies nets with low

noise immunity to avert potential noise-related problems and lethal silicon

failures before tapeout. The CeltIC analyzer accurately calculates the impact of

noise on both the delay and functionality of cell-based designs. It performs SoC

noise analysis and generates repairs back into place-and-route.

KEY FEATURES AND BENEFITS• Isolates and repairs crosstalk-induced

functional and delay failures

• Calculates the impact of noise ondelay and slew for feedback to STA

• Reduces SI closure iterations byfiltering false failures by over 10 to100X versus other crosstalk analyzers

• Predicts functional, timing, and yieldproblems resulting from bootstrap andovershoot/undershoot noise

• Performs accurate glitch propagationto verify noise immunity with noadditional overhead characterization

• Performs internal timing windowconvergence to reduce pessimism

• Automates noise library creation forcells, memories, I/Os, and custommacros

• Handles multimillion SoC designs flator hierarchically using ECHO models

NOISE IN DIGITAL DESIGNAs designs migrate to nanometertechnologies, the amount of couplingcapacitance between wires increasesto more than 70% of the total wirecapacitance. Combined with increasesin on-chip slew rates, this leads to adramatic increase in on-chip noise. As a result, chips are now failing,under-performing, or suffering fromlow yields.

DELAY UNCERTAINTYCoupling noise can change criticalpath delays and lead to unforeseensetup or hold violations. This delayuncertainty can result in additionaliterations to achieve timing, or inmissed performance targets.

CeltIC analyzer calculates the impact ofcrosstalk on delay and slew for all netsusing a combination of cell- andtransistor-level models. For very noisynets that exhibit non-linear behavior,CeltIC analyzer uses an on-the-fly fasttransient simulation engine tocalculate noise-on-delay effects andensure SPICE-like accuracy.

CeltIC

Timingwindows,slews

SPEF

SDF

Repairs

Synthesis/place-and-route

RC extraction

CeltIC

Static timing

LVS/DRC

Tapeout

CeltIC

CeltIC

Virtual prototyping

Figure 1: CeltIC design flow

GLITCH PROPAGATIONCoupling noise can be severe enoughto cause functional failures. Theproblem is exacerbated with IR drop,which makes the design moresusceptible to noise. CeltIC analyzeraccurately calculates the worst-caseglitch created by the combined impactof instance-specific IR drop and couplingaggressors. CeltIC analyzer guaranteesfunctional validity by performing glitchnoise propagation to register endpointsand ensuring that the register is notdriven unstable. Using noise propagationto register endpoints reduces thenumber of false noise violations by anorder of magnitude compared to usingglitch peak, area-based, or rejectioncurve-based checks. This translates toless work for place-and-route systemsand reduced SI closure iterations.

NOISE LIBRARYCeltIC analyzer is designed to handlemultimillion-gate designs. To efficientlysupport large designs, it uses acharacterized noise library that isespecially tailored for accurate noiseanalysis. The library contains each cell'sholding strength using a series of I/Vcurves along with input noisethresholds. CeltIC analyzer supplies theutility to create this noise library (.cdB)directly from analysis of the extractednetlist view of each cell. The noiselibrary creation process is very efficient,

taking only minutes to characterize acomplete standard cell library. TheCeltIC characterization utility can alsocreate noise views for memories, I/Os,and custom macros. In addition, pre-characterized CeltIC noise libraries areavailable from popular standard celland memory IP vendors.

DATA FLOWCeltIC analyzer requires a cell-levelnetlist with coupled RC parasitics inSPEF format, a noise library, and a Tclcontrol file. Verilog® DSPF, and DEFnetlist formats are also supported.

CeltIC analyzer can generate timingwindows from design constraints inSDC format and timing libraries inLiberty (.lib) format. It will iteratebetween noise-on-delay calculationand internal timing analysis to create aconverged set of timing windows.Timing windows are used to improvethe realism of the analysis and toreduce false failures. Alternatively,timing windows and slews can beimported from external static timinganalyzers using the provided Tcl utilities.

CeltIC analyzer outputs a sorted noisereport in HTML format which detailsthe peak noise for each victim net andthe noise contributors. The glitch noisewaveform can be displayed graphicallyby clicking the appropriate link in theHTML report. It also outputs a delay

uncertainty report in HTML formatsorted by relative or absolute delaychange. The delay changes can beexported as SDF to static timinganalyzers for final static timingverification. Additionally, CeltIC analyzerreports the effective impact of crosstalkon slew. The output reports can alsobe customized using a Tcl API.

HIERARCHICAL CROSSTALK ANALYSISCeltIC analyzer supports twohierarchical noise models: a user-defined noise (UDN) model and anECHO model. UDNs can be used forportions of a design that are not yetcomplete, or for non-digital blockssuch as analog cores. ECHO models canbe created by CeltIC analyzer or fromtransistor-level noise analysis ofcustom digital cores with PacifIC™analyzer. Through the use of thesemodeling schemes, CeltIC analyzer iscapable of performing full-chip noiseanalysis of very large SoC designs.

CROSSTALK FIXINGCeltIC analyzer generates fixes forboth crosstalk-induced timing andfunctional problems. It generatesrepair commands to drive bothCadence third-party place-and-routesystems. Repairs include bufferinsertion, driver sizing, wire spacing,and shielding.

PLATFORMS• Unix (32-bits, 64-bits)

• Linux (32-bits, 64-bits)

FOR MORE INFORMATIONEmail us at icinfo@cadence.com or logon to www.cadence.com

2V

1V

0V1 0ns 1 2ns 1 4ns 1 6ns

TIME

a1, a2Victim (no coupling)

in

Victim

Impact of noiseon delay

Figure 3: Noise caused by coupling can increase the delay of a single logic stage by over 100%

Figure 2: CeltIC analyzer accuracy and false-failure filtering reducesviolations by 10 to 100x

© 2003 Cadence Design Systems, Inc. All rights reserved.Cadence, Verilog, and the Cadence logo are registeredtrademarks and CeltIC, Encounter, and PacifIC aretrademarks of Cadence Design Systems, Inc. All othersare properties of their respective holders.

3073G 11/03

a1

in

a2

victim out

115K nets.18mm

174K nets.15mm

1.4M nets 457K nets.130nm

532K nets.130nm

176

100,000

10,000

1,000

100

10

1

401

1,0839,760

6,500

1 1

40 21

4