32 tap fir filter using hann window-b7

VISVESVARAYA TECHNOLOGICAL UNIVERSITY Belgaum-590014, Karnataka

PROJECT REPORT

ON

32-TAP HANN WINDOW BASED FIR LOW-PASS FILTER IMPLEMENTATION

Submitted in the partial fulfillment for the award of the degree of

Bachelor of Engineering in

Electronics and Communication Engg.

By TARWALA IDRIS IQBAL (1NH06EC081)

ROHAN KAKADE (1NH06EC060)

JAYAKARTHIKEYAN E.M (1NH06EC022)

PRITHVIRAJ K.V (1NH06EC052)

UNDER THE GUIDANCE OF

Mr. C.P.RAJENDRA Mr. V. ANAND

Asst.Professor, ECE, NHCE Director, IIVDT, Bangalore

Department of Electronics & Communication Engg.

New Horizon College of Engineering, Bengaluru-87, Karnataka

2009-10

NEW HORIZON

COLLEGE OF ENGINEERING (Accredited by NBA, Permanently affiliated to VTU)

Kadubisanahalli, Panathur Post, Outer Ring Road, Nr. Marathalli, Bengaluru-560087, Karnataka

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGG.

CERTIFICATE

This is to certify that the project work entitled 32-tap Hann Window based FIR

Lowpass Filter Implementation is a bonafied work carried out by, Tarwala Idris Iqbal,

Rohan Kakade, Jayakarthikeyan E.M & Prithviraj K.V. bearing USN: 1NH06EC081,

1NH06EC060, 1NH06EC022, 1NH06EC052 in partial fulfillment for the award of

degree of Bachelor of Engineering in Electronics & Communication Engg. of the

Visvesvaraya Technological University (VTU), Belgaum during the academic year 2009 -

10. It is certified that all corrections / suggestions indicated for internal assessment has

been incorporated in the project report deposited in the departmental library & in the main

library. This project report has been approved as it satisfies the academic requirements in

respect of project work prescribed for the Bachelor of Engineering Degree in ECE.

Guide Project coordinator

C.P. RAJENDRA C.P. RAJENDRA

………………….. …………………...

H.O.D. Principal

Dr. T.N. Basavaraj Dr. T.N. Basavaraj

…………………… ……………………...

Name of the Students : (i) TARWALA IDRIS IQBAL (ii) ROHAN KAKADE

(iii) JAYAKARTHIKEYAN E.M (iv) PRITHVIRAJ K.V

University Seat Numbers : (i) 1NH06EC081 (ii) 1NH06EC060

(iii) 1NH06EC022 (iv) 1NH06EC052

External Viva / Orals

Name of the internal / external examiner Signature with date

1. …………………………… ………………………

2. …………………………… ………………………

i

ACKNOWLEDGEMENT

Words are often less to reveal one’s deep regards. An understanding of work like this is

never the outcome of the efforts of a single person. We take this opportunity to express

our profound sense of gratitude and respect to all those who helped us through the

duration of this thesis.

First off all we would like to thank the Supreme Power, One who has always guided us to

work on the right path of the life, without His grace this would never have become a

reality.

We are highly indebted to Prof. T.N. BASAVARAJ, Head of Department for providing

us the requisite environment and being a constant source of inspiration. This work would

not have been possible without the encouragement and able guidance of our supervisors

Prof. C.P. RAJENDRA & Mr. V. ANAND, their enthusiasm and optimism made this

experience both rewarding and enjoyable. Most of the novel ideas and solutions found in

this thesis are the result of our numerous stimulating discussions. Their feedback and

editorial comments were also invaluable for the writing of this thesis.

We express our sincerest regards and gratitude to Mr. SASHIKANTH PATIL for his

able guidance, valuable advice and helpful suggestions at times of difficulties, which we

faced while pursuing this project. He has guided us and given us full time to understand

the minute details and all the basic concepts necessary for the successful completion of

the project.

Our humble gratitude is also reserved for our friends whose judicious help and sustained

encouragement were a constant source of inspiration to carry out this thesis. We would

also like to thank all those who directly or indirectly helped us in this unique journey.

ii

ABSTRACT

Finite Impulse Response (FIR) filters as the name suggests has fixed

number of samples to represent its impulse response. The ideal infinite response of

filter is multiplied with a window function to get FIR filter coefficients. Hann

window is one such popular window function used to design FIR filter. The aim of

the project is to design a 32-tap FIR low pass filter based on Hann window and to

implement the same using fixed point arthimetic in VLSI using tools such as Cadence

NCVerilog, Cadence Simvision & Cadence RTL Compiler. The filter is implemented in

Direct form I and Direct form I transposed structures, optimized with respect to area

and performance.

iii

TABLE OF CONTENTS

Acknowledgement i

Abstract ii

Table of contents iii

List of figures v

List of tables vi

1. INTRODUCTION 1

2. LITERATURE 2

2.1. Digital filters 2

2.2. Types of digital filters 2

2.2.1. Finite Impulse response (FIR) filter 3

2.2.2. Infinite Impulse response (IIR) filter 4

2.3. Selection between FIR and IIR filters 5

2.4. Specification of a filter 6

2.5. Coefficient calculation 7

2.6. Filter design by windowing method 8

2.6.1. Fixed window functions 8

2.7. Effect of finite word length in digital filters 12

2.7.1. Rounding and truncation errors 13

2.7.1.1. Truncation error for sign magnitude representation 14

2.7.1.2. Truncation error for Two’s complement representation 14

2.7.1.3. Round off two’s complement and sign magnitude representation 15

2.7.2. Round off error in FIR filter 16

2.7.3. Overflow errors 17

3. SYSTEM DESIGN AND ARCHITECTURE 18

3.1. Design Approaches 18

3.2. Filter specifications 19

3.3. Hardware specification 20

3.4. Software used for FIR digital filter design 21

3.4.1. Introduction to matrix laboratory (MATLAB) 21

3.4.2. MATLAB implementation 22

3.4.3. Computing output using convolution 22

3.4.4. Verilog implementation 23

3.4.5. Verification Plan 28

3.4.6. Synthesis 29

4 RESULT AND ANALYSIS 34

4.1 MATLAB Results 34

4.1.1 Frequency response of FIR filter in Time and Frequency domain 34

4.1.2 Test signals for FIR filter 35

4.2 VERILOG results 38

4.3 Synthesis Results 43

4.4 Operating Frequency and Area reports 45

4.4.1 Operating Frequency 45

4.4.2 Area reports 45

5 FUTURE SCOPE 46

6 CONCLUSION 47 7 REFERENCES 48

8 APPENDICES 49

iv

APPENDIX A: MATLAB Code 49 APPENDIX B: VERILOG Code & Waveform 54 APPENDIX C: SYNTHESIS Report 82

v

LIST OF FIGURES

Fig 2.1 : A Real-Time Digital Filter 2 Fig 2.2 : Direct Form-I Structure 3 Fig 2.3 : Direct Form-I Transposed Structure 4 Fig 2.4 : Pole (o) and Zero(x) plot of FIR filter 5 Fig 2.5 : Tolerance Scheme for a Low Pass Filter 7 Fig 2.6 : Gain response of fixed window functions 10 Fig 2.7 : The relation among the frequency responses of an ideal low pass

filters, a typical window and the windowed filter 10

Fig 2.8 : Hann window Frequency response 11 Fig 2.9 : Hann window Frequency and Phase response 12 Fig 2.10 : Quantized number representation 14 Fig 2.11 : Quantization error in Rounding and Truncation 15 Fig 2.12 : Probabilistic Characteristics of Quantization Errors 16 Fig 3.1 : Design Flow 18 Fig 3.2 : FIR Filter frequency response with specifications 19 Fig 3.3 : FIR Filter Block diagram 20 Fig 3.4 : Multiplier Block diagram 25 Fig 3.5 : Summation Block diagram 26 Fig 3.6 : Verification Plan Flowchart 28 Fig 3.7 : Logic Synthesis 29 Fig 3.8 : Logic Synthesis flow from RTL to Gates 30 Fig 4.1 : Filter Response with Normalized Frequency 34 Fig 4.2 : Filter Response with Normal frequency 34 Fig 4.3 : Impulse response of FIR filter 35 Fig 4.4 : Step response of FIR filter 35 Fig 4.5 : Composite input signal in Time domain 36 Fig 4.6 : Composite input signal in Frequency domain 37 Fig 4.7 : Filter output for composite input signal in Time domain 37 Fig 4.8 : Filter output for composite input signal in Frequency domain 38 Fig 4.9 : Gate level circuit for Form I FIR filter 43 Fig 4.10 : Gate level circuit for Form I Transposed FIR filter 44

vi

LIST OF TABLES

Table 2.1 : Properties of some fixed window functions 11

Table 2.2 : Fixed-point binary representations 13

Table 3.1 : Filter specifications 19

Table 3.2 : FIR Filter Hardware Specifications 20

Table 4.1 : Impulse response results 38

Table 4.2 : Step response results 39

Table 4.3 : Composite Sine wave results 41

Table 4.4 : Operating Frequency Report 45

Table 4.5 : Area report 45

Design of 32 Tap FIR filter

Department of ECE, NHCE 2009-10

1

CHAPTER 1

INTRODUCTION

A digital filter is a discrete-time, discrete-amplitude convolver. Basic Fourier

transform theory states that the linear convolution of two sequences in the time domain is

the same as multiplication of two corresponding spectral sequences in the frequency

domain. Filtering is in essence the multiplication of the signal spectrum by the frequency

domain impulse response of the filter. For an ideal low pass filter the pass band part of

the signal spectrum is multiplied by one and the stop band part of the signal by zero.

It is important to note that distortion and noise can be introduced into digital

filters simply by the conversion of analog signals into digital data, also by the digital

filtering process itself and lastly by conversion of processed data back into analog. When

fixed-point processing is used, additional noise and distortion may be added during the

filtering process because the filter consists of large numbers of multiplications and

additions, which produce errors, creating truncation noise. Increasing the bit resolution

beyond 16-bits will reduce this filter noise. For most applications, as long as the analog to

digital (ADC) and digital to analog (DAC) converters have high enough bit resolution,

distortions introduced by the conversions are less of a problem.

When digital systems are implemented either in hardware or in software, the filter

coefficients are stored in binary registers. These registers can accommodate only a finite

number of bits and hence, the filter coefficients have to be truncated or rounded off in

order to fit into these registers. Truncation and rounding-off the data results in

degradation of system performance.

This project‟s main aim is to design a FIR filter using HANN window initially

with 16 bit data and 16 bit coefficient register size. Further optimization is done by

reducing the input & output data widths to 8 and 10 bits respectively, coefficient data

width to 13 bits, followed by correctoin of all the errors associated with truncation of bits,

hence optimizing the area and performance of the FIR filter.

Chapter 2 talks about the different types of Digital Filters, their specifications and

different types of errors which occur during quantization. Chapter 3 discusses about

hardware design and architecture of HANN FIR filter. Finally the chapter 4 highlights the

various results obtained and analysis performed.



2

CHAPTER 2

LITERATURE

2.1 DIGITAL FILTERS

A digital filter is a mathematical algorithm implemented in hardware and/or

software that operate on a digital input signal to improve output signal for the purpose of

achieving a filter objective. The term digital filter refers to the specific hardware and

software routine that performs the filtering algorithm. Digital filter often operate on

digitized analog signals or just numbers, representing some variable, stored in a computer

memory. A simplified block diagram of a real-time digital filter, with analog input and

output signals, is given in Figure 2.1. The band limited analog signals is sampled

periodically and converted into series of digital samples x (n), n = 0,1….. The digital

processor implements the filtering operation, mapping the input sequence x (n) into the

output sequence y(n) in accordance with a computational algorithm for the filter. The

DAC converts the digitally filtered output into analog values.[1]

Fig 2.1: A Real-Time Digital Filter

2.2 Types of Digital Filters

Many digital systems use signal filtering to remove unwanted noise, to provide

Spectral shaping, or to perform signal detection or analysis. Two types of filters provide

these functions they are finite impulse response (FIR) filters and infinite impulse response

(IIR) filters. Typical filter applications include signal preconditioning, band selection, and

low pass filtering.

2.2.1 Finite Impulse Response (FIR) Filter

A Finite Impulse Response (FIR) digital filter is one whose impulse response is of



3

finite duration. The impulse response is "finite" because there is no feedback in the filter

if we put in an impulse (that is, a single "1" sample followed by many "0" samples),

zeroes will eventually come out after the "1" sample has made its way in the delay line

past all the coefficients.

The structure for these algorithms can be represented as "DIRECT FORM-I

STRUCTURE”& “DIRECT FORM-I TRANSPOSED STRUCTURE”.[1]

Fig 2.2: Direct Form-I Structure

Fig 2.3: Direct Form-I Transposed Structure

This can be stated mathematically as:

y (n) = ℎ 𝑘 𝑥(𝑛 − 𝑘)𝑁−1𝑖=0 (2.1)

y (n) = Response of Linear Time Invariant (LTI) system

x (k) = Input signal.

h (k) = Unit sample response

N= No. of signal samples

FIR filters are simple to design and they are guaranteed to be bounded input-

bounded output (BIBO) stable. By designing the filter taps to be symmetrical about the

center tap position, a FIR filter can be guaranteed to have linear phase response. This is a

desirable property for many applications such as music and video processing. They are

simple to implement in hardware. They have desirable numeric properties. In practice, all

Digital Signal Processing (DSP) filters must be implemented using "finite-precision"



4

arithmetic, that is, a limited number of bits. The use of finite-precision arithmetic in IIR

filters can cause significant problems due to the use of feedback, but FIR filters have no

feedback, so they can usually be implemented using fewer bits, and the designer has

fewer practical problems to solve related to non-ideal arithmetic. FIR filters also have a

low sensitivity to filter coefficient quantization errors. This is an important property to

have when implementing a filter on a DSP processor or on an integrated circuit. FIR filter

are high order FIR filters have longer delays. More side lobes in stop band than the IIR

filter. FIR filters are a higher order than IIR filters, making FIR filters more

computationally expensive.[2]

2.2.2 Infinite Impulse Response (IIR) Filter

IIR filter is one whose impulse response is infinite. Impulse response is infinite because

there is feedback in the filter. This permits the approximation of many waveforms or

transfer functions that can be expressed as an infinite recursive series. These

implementations are referred to as Infinite Impulse Response (IIR) filters. The functions

are infinite recursive because they use previously calculated values in future calculations

to feedback in hardware systems.

IIR filters can be mathematically represented as:

𝑦 𝑛 = − 𝑎𝑘 𝑦 𝑛 − 𝑘 + ℎ𝑘 𝑥(𝑛 − 𝑘)𝑁−10

𝑀−10 (2.2)

Where ak is the Kth feedback tap. M is the number of feed-back taps in the IIR

filter and N is the number of feed forward taps.

IIR Filters are useful for high-speed designs because they typically require a lower

number of multiply compared to FIR filters. IIR filters have lower side lobes in stop band

as compared to FIR filters. Unfortunately, IIR filters do not have linear phase and they

can be unstable if not designed properly. IIR filters are very sensitive to filter coefficient

quantization errors that occur due to using a finite number of bits to represent the filter

coefficients. One way to reduce this sensitivity is to use a cascaded design. That is, the

IIR filter is implemented as a series of lower-order IIR filters as opposed to one high-

order.[1]



5

2.3 Selection between FIR and IIR filter

The choice between the FIR and IIR filter depends largely on the relative

advantages of the two filter types:

FIR filters can have an exactly linear phase response. The implication of this is that

no phase distortion is introduced into the signal by the filter. This is an important

requirement in many applications, for example data transmission, biomedicine,

digital audio, and image processing. The phase response of IIR filter is nonlinear,

especially at the band edges.

The effects of using a limited number of bits to implement filters such as round off

noise and coefficient quantization errors are much less severe in FIR than IIR.

FIR requires more coefficients for sharp cutoff filters than IIR. Thus for a given

amplitude response specification, more processing time and storage will be

required for FIR implementation. However, one can readily take advantage of the

computational speed of the Fast Fourier Transform (FFT) and multirate technique

to improve significantly the efficiency of FIR implementations.

Analog filters can be readily transformed into equivalent IIR digital filters meeting

similar specification. This is not possible with FIR filters, as they have no analog

converter counterpart. However, with FIR it is easier to synthesize filters of

arbitrary frequency response.

The FIR filter are inherently stable because all the poles always lie at the origin

which is not the case with IIR filters which renders them conditionally

stable.[1][2][3]

Fig 2.4: Pole (o) and Zero(x) plot of FIR filter



6

2.4 Specification of a Filter

Required specifications include specifying the:

1. Signal characteristics (types of signal source and sink, input/output interface,

data rates and width and highest frequency of interest).

2. The characteristics of the filter (the desired amplitude and/or phase response

and their tolerances, the speed of operation and modes of filtering (real time or

batch).

3. The manner of implementation (as a high level language routine in a computer

or as a Digital Signal processor-based systems, choice of signal processor),

and

4. Other design constraints (the cost of filter).[2]

The designer may not have enough information to specify the filter completely at the

outset, but as many of the filter requirements as possible should be specified to simplify

the deign process. The characteristics of digital filter are often specified in the frequency

domain. For frequency selective filters, such as low pass and band pass filters; the

specifications are often in the form of tolerance scheme. Figure 2.4 depicts such a scheme

for low pass filter. The shaded horizontal lines indicate the tolerances limits. In the pass

band, the magnitude response has a peak deviation of δp and in the stop band it has a

maximum deviation of δs. The width of the transition band determines the sharpness of

the filter. The magnitude response decreases monotonically from pass band to the stop

band in this region.[1]

The following are key parameters of interest:

δp Pass band Deviation

δs Stop band Deviation

fp Pass edge Frequency

fs Stop band Edge Frequency

The edge frequencies are often given in the normalized form that is as a fraction of the

sampling frequency (f ⁄ Fs), whereas f is input frequency and Fs is the sampling frequency

but specifications using standard frequency units of hertz or kilohertz are valid and

sometimes are more meaningful. Pass band and stop band deviations may be expressed as

ordinary numbers or in decibels (db) when they specify the pass band ripple and

minimum stop band attenuation respectively. Thus the minimum stop band attenuation,

As and the peak band ripple, Ap decibels are given as (FIR filers).[1]

As (Stop band attenuation) = -20 log 10 D (2.3)



7

Ap (Pass band ripple) = 20 log 10 (1+ δp) (2.4)

Fig 2.5: Tolerance Scheme for a Low Pass Filter

2.5 Coefficient Calculation

One of a number of approximation methods is selected and the values of the coefficients,

h (k) for FIR or aK and bK system parameters for IIR are calculated. The two basic

methods used are the impulse invariant and bilinear transformation methods. With the

impulse invariant method, after digitizing the analog filter, impulse response of the

original analog filter is preserved, but not its magnitude frequency response. Because of

the inherent aliasing, the method is inappropriate for high pass or band stop filters. The

bilinear method on the other hand yields very efficient filters and is well suited to the

calculation of the coefficients of the frequency selective filters. It allows the design of

digital filters with known classical characteristics such as Butterworth, Chebyshev and

Elliptic. [2]

Digital filters resulting from bilinear transformation will preserve the magnitude response

characteristics of the analog filter but not the time domain properties. Efficient computer

programs now exist for calculating filter coefficients, using the bilinear method, by

merely specifying filter parameters of interest. The impulse invariant method is good for

simulating analog systems, but the bilinear method is best for frequency selective IIR

filters. The pole zero placement method offers an alternative approach to calculating the

coefficients the of IIR filters. It is an easy way of calculating the coefficients of very

simple filters. However, for filters with good amplitude response it is not recommended



8

as it relies on „trial‟ and „error‟ shuffling of the pole zero positions. [1]

As with IIR filters there are several methods for calculating the coefficients of FIR

filters. The three methods are the window, frequency sampling, and the optimal. The

window method offers a very simple and flexible way of computing FIR filters

coefficients, but it does not allow the designer adequate control over the filter parameters.

The main attraction of the frequency sampling method is that it allows a recursive

realization of FIR filters, which can be computationally very efficient. However, it lacks

flexibly in specifying or controlling filter parameters. With the availability of an efficient

and easy-to-use program, the optimal method is now widely used in industry and for most

applications will yield the desired FIR filters. In following summary, there are several

methods of calculating the coefficients of which these are the most widely used:[2] [8]

1) Impulse invariant (IIR)

2) Bilinear transformation (IIR)

3) Pole –zero placement (IIR)

4) Windows (FIR)

5) Frequency sampling (FIR)

6) Optimal (FIR)

2.6 Filter Design by Windowing Method

The windowing method of FIR filter design bases the filter impulse response

sequence (and consequently, the filter transfer function) on the coefficients of Fourier

series expansion of the desired frequency response function. Since the series will be

infinite and non casual so it is unrealizable. So the series must be truncated to get finite

impulse response. This means of truncation is a technique known as windowing. But this

results in undesirable oscillations in the pass band and stop band of digital filter. These

undesirable oscillations can be reduced by using set of time limited weighting functions,

w (n) referred as window function. A variety of windows are available for use. [3]

2.6.1 Fixed window functions

Authors have proposed many tapered windows, but we restrict our discussions to

the three most commonly used tapered windows of length 2M+1, which are listed below.

𝑅𝑒𝑐𝑡𝑎𝑛𝑔𝑢𝑙𝑎𝑟 ∶ 𝜔 𝑛 = 1 (2.5)

𝐻𝑎𝑛𝑛 ∶ 𝜔 𝑛 = 1

2 [ 1 + cos

2𝜋𝑛

2𝑀+1 −𝑀 ≤ 𝑛 ≤ 𝑀 (2.6)



9

𝐻𝑎𝑚𝑚𝑖𝑛𝑔 ∶ 𝜔 𝑛 = .54 + .46 cos 2𝜋𝑛

2𝑀+1 −𝑀 ≤ 𝑛 ≤ 𝑀 (2.7)

𝐵𝑙𝑎𝑐𝑘𝑚𝑎𝑛 ∶ 𝜔 𝑛 = .42 + .5 cos 2𝜋𝑛

2𝑀+1 + .08 cos

4𝜋𝑛

2𝑀+1 (2.8)

−𝑀 ≤ 𝑛 ≤ 𝑀



10

Fig 2.6: Gain response of fixed window functions

As it can be seen from these plots the magnitude spectrum of each window is

characterized by a large main lobe centered at = 0 followed by a series of side lobes

with decreasing amplitudes. Two parameters that somewhat predict the performance of a

window in FIR filter design are its main lobe width and the relative side lobe level.The

main lobe width ML is the distance between the nearest zero crossing on both sides of

the main lobe and the relative side lobe level Asl is the difference in db between the

amplitudes of the largest side lobe and the main lobe.[8]

Fig 2.7: The relation among the frequency responses of an ideal low pass filters a typical

window and the windowed filter.



11

Table 2.1: Properties of some fixed window functions

Type of

Window

Main lobe

width ML

Relative side

lobe level Asl

Minimum stop

band

attenuation

Transition

Bandwidth

Rectangular 4/(2M + 1) 13.3 db 20.9 db .92/M

Hann 8/(2M + 1) 31.5 db 43.9 db 3.11/M

Hamming 8/(2M + 1) 42.7 db 54.5 db 3.32/M

Blackman 12/(2M + 1) 58.1 db 75.3 db 5.56/M

Comparison among these commonly used windows shows that at a given length,

the rectangular window has the narrowest main lobe; it gives the sharpest transition at the

discontinuity of Hd (ej

). By the tapering the window smoothly to zero as in Hann,

Hamming and Blackman windows, the side lobes can be reduced in amplitudes, but the

trade off is larger main lobes. All of these windows are symmetric about M/2, Hence their

frequency responses have generalized linear phase.[1]

The Hann window named after its inventor Von Hann does a good job of forcing

the ends of the response to zero but it also adds distortion to the wave being analyzed.

Fig 2.8: Hann window Frequency responses



12

Fig 2.9: Hann window Frequency and Phase response

The Hann window should always be used with continuous signals, but must never

be used with transients. The reason is that the window shape will distort the shape of the

transient and the frequency and phase content is intimately connected with its shape. The

measured level will also be greatly distorted.

In conclusion the Hann window function is useful for noise measurements where

better frequency resolution than some of the other windows is desired but moderate side

lobes do not present a problem.[5]

2.7 Effect of Finite Word Length in Digital Filters

When digital systems are implemented either in hardware or in software, the filter

coefficients are stored in binary registers. These registers can accommodate only a finite

number of bits and hence, the filter coefficients have to be truncated or rounded off in

order to fit into these registers. Truncation and rounding-off the data results in

degradation of system performance. Also in digital processing systems, a continuous time

input signal is sampled and quantized in order to get the digital systems.[6]

There are four ways in which finite word length affects the performance of FIR digital

filter:

1) Quantization effects in analog-to-digital conversion.

2) Product quantization and coefficient quantization errors in digital filters.

3) Limit cycles in IIR filters and

4) Finite word length effects in Fast Fourier transform.[4]



13

2.7.1 Rounding and Truncation Errors

Rounding and truncation introduces an error whose magnitude depends on the

number of bits truncated or rounded-off. Also, the characteristics of the error depend on

the form of binary number representation. The sign magnitude and two‟s complement

representation of fixed-point binary numbers are considered here. Table 2.2 gives the sign

magnitude and two‟s complement representation of fixed-point numbers

Table 2.2 Fixed-point binary representations

NUMBER SIGN MAGNITUDE 2‟SCOMPLEMENT

7 0111 0111

6 0110 0110

5 0101 0101

4 0100 0100

3 0011 0011

2 0010 0010

1 0001 0001

0 0000 0000

-0 1000 0000

-1 1001 1111

-2 1010 1110

-3 1011 1101

-4 1100 1100

-5 1101 1011

-6 1110 1010

-7 1111 1001

Consider a number x whose original length is „L‟ bits. Let this number be

quantized to „b‟ bits as shown below. This quantized number is represented by Q (x).

Both x and Q (x) are shown below. Note B<L.



14

Fig 2.10(a) & 2.10(b) Quantized number representation

A Truncation error, εT, is introduced in the input signal and thus the quantized signal is:

Qt (x) = x + εT (2.8)

The range of values of the error due to truncation of the signal is analyzed here for both

sign magnitude and two‟s complement representation.[1]

2.7.1.1 Truncation Error for Sign Magnitude Representation

When the input number x is positive, truncation results in reducing the magnitude

of the number. Thus the truncation error is negative and range is given by:

-(2-B – 2-L) ≤ εT ≤0 (2.9)

The largest error occurs when all the discarded bits are one. When the number x is

negative, truncation results in reduction of the magnitude only. However, because of the

negative sign, the resulting number will be greater than the original number. Let the

number be x = -0.374. That is, in sign magnitude form it is represented as x = 1011 and

after truncation of one bit, Q (x) = 101. This is equivalent to -0.25 in decimal. But -0.25 is

greater than 0.375. Therefore, the truncation error is positive and its range is:

0 ≤ εT ≤ (2-B – 2-L) (2.10)

The overall range of the truncation error for the sign magnitude representation is:

-(2-B – 2-L) ≤ εT ≤ (2-B – 2-L) (2.11)

2.7.1.2 Truncation Error for Two‟s Complement Representation

When the input number is positive, truncation results in a smaller number, as in

case of sign magnitude numbers. Hence, the truncation error is negative and its range is

same as given in Equation (2.9). If the number is negative, truncation of the number in

two‟s complement form results in a smaller number and error is negative. Thus the

complete range of truncation error for two‟s complement representation is:

-(2-B – 2-L) ≤ εT≤0 (2.12)



15

2.7.1.3 Round-off for Sign Magnitude and Two‟s Complement

Representation

The rounding of a binary number involves only the magnitude of the number and is

independent of the type of fixed-point binary representation. The error due to rounding

may either positive or negative and the peak value is (2-B – 2-L)/2.The round off error is

symmetric about zero and its range is

- (2-B – 2-L)/2 ≤ εR ≤ (2-B – 2-L)/2 (2.13)

(a)

Rounding

(b)

Truncation error in 2‟s

complement

(c)

Truncation error in

Sign magnitude Fig 2.11: Quantization error in Rounding and Truncation.

In most cases infinite precision is assumed, i.e. the length of the un-quantized number is

assumed to be infinity and as result Equations (2.11), (2.12), (2.13) can be modified and

the range of error for different cases are as follows:

1) Truncation error for sign magnitude representation

-2-B≤ εT ≤2-B (2.14)

2) Truncation error for sign two‟s complement representation

-2-B≤ εT ≤0 (2.15)

3) Round-off error for sign magnitude and two‟s complement representation

-2-B /2 ≤ εT ≤2-B /2 (2.16)

Figure (2.10) shows quantization error in truncation and rounding-off numbers. In

computations involving quantization, a statistical approach is used in characterization of

these errors.[1]



16

(a)

Rounding

(b)

Truncation error in 2‟s

complement

(c)

Truncation error in

Sign magnitude Fig 2.12: Probabilistic Characteristics of Quantization Errors

2.7.2 Round-Off Error in FIR Filter

The difference equation for FIR filter is given by:

𝑦 𝑛 = ℎ 𝑚 𝑥(𝑛 − 𝑚)𝑁−1𝑚−0 (2.17)

Where each variable is represented by a fixed number of bits. Typically the input

and the output samples, x (n-m) and y (n) are each represented by 12-bits and the

coefficients by 16- bits in 2‟s complement format. It is seen from Equation (2.17) that the

output of the filter is obtained as the sum of products of h (m) and x (n-m). After each

multiplication, the product contains more bits than either h (m) or x (n-m). If a 12-bit

input is multiplied by the 16-bit coefficient the result is 28-bit long and will need to be

quantized back to 16-bits before it can be stored in a memory or to 12-bits before it can

be output to DAC. This quantization leads to errors whose effects are similar to those of

ADC noise, but could be more severe. The common way to quantize the result of an

arithmetic operation is to truncate the result, that is

a) To retain the most significant higher-order bits and to discard the lower-order

bits

b) To round the result, that is to choose the higher-order bits closest to the

unrounded results. This is achieved by adding half an LSB to the result.[1]



17

2.7.3 Overflow Errors

Overflow occurs when the sum of two numbers, usually two large numbers of the

same sign, exceeds the permissible word length. Thus in the Equation (2.17) overflow

could occur when products of h (0) x(n) and h(1) x(n-1) are added provided that the final

output, y(n) is within the permissible word length overflow in partial sum is unimportant.

This is a desirable property of the 2‟s complement arithmetic. However, if the output, y

(n) exceeds the permissible limit then clearly the value of the output sample to the DAC

will be wrong and steps should be taken to prevent this.



18

CHAPTER 3

SYSTEM DESIGN AND ARCHITECTURE

3.1 Design Approaches

Fig 3.1: Design Flow.

Specification

High level Design

Low level Design

RTL Coding

Functional Verification

Logic Synthesis

Place and Route

Fabrication

Gate Level Simulation



19

3.2 Filter Specifications

Table 3.1 Filter specifications

Parameter Design Specification

Filter Order 31

Filter Type Low Pass Filter

Design Method Hann Window

Phase Linear Phase

Cutoff Frequency 2000Hz

Sampling Frequency 8000Hz

Transition Width 0.31517rad

Stop-band attenuation 43.9 dB

Fig 3.2: FIR Filter frequency response with specifications



20

3.3 Hardware Specifications

Table 3.2: FIR Filter Hardware Specifications

Parameter Design Specification

Input data width 8bits

Input Range +127d to -128d

Coefficient data width 13bits

Output Width 10bits

Output range +511 to - 512

Multiplier Width 10 bits

Adder width 10bits

Fig 3.3: FIR Filter Block diagram

[12:0]



21

3.4 Software used for FIR digital filter design

The present work has been undertaken as, Effect of Finite Word Length on FIR

Filter Implemented on Cadence. The software implementation of the FIR filter is divided

into two parts:

Development of Low pass FIR filter with the help of MATLAB using

windowing technique.

Development of Low pass FIR filter by convolving the Quantized &rounded-

off input sequences and filter coefficients using Cadence for Form I and Form

I transposed structures

First a brief introduction to the MATLAB software is given followed by the aforesaid

implementation.

3.4.1 Introduction to Matrix Laboratory (MATLAB)

MATLAB is a high-performance language for technical computing. It integrates

computation, visualization, and programming in an easy-to-use environment where

problems and solutions are expressed in familiar mathematical notation. Typical uses

include:

1. Math computation

2. Algorithm development

3. Data acquisition

4. Modeling, simulation and prototyping.

5. Data analysis, exploration and visualization

6. Scientific and engineering graphics.

MATLAB is an interactive system whose basic data element is an array that does

not require dimensioning. This allows us to solve many technical computing

problems, especially those with matrix and vector formulations, in a fraction of

the time it would take to write a program in a scalar non-interactive language such

as C or Fortran.

MATLAB has evolved over a period of years with input from many users. In

university environments, it is the standard instructional tool for introductory and

advanced courses in mathematics, engineering, and science.

In industry, MATLAB is the tool of choice for high-productivity research,

development, and analysis. MATLAB features a family of add-on application-

specific solutions called toolboxes.



22

Very important to most users of MATLAB, toolboxes allow you to learn and apply

specialized technology.[9]

3.4.2 MATLAB implementation

Steps involved in designing the FIR filter in Matlab R2009a

According to our Specifications we have generated the filter coefficients using the

following command:

o h = fir1 (“filter order”,” Normalized cutoff frequency”,” window type”)

Then multiplying it with the max_data value following which the output is

rounded to the nearest integer value thereby scaling the coefficients.

In a similar fashion the input was first sampled then multiplied with max_input

data. It was then rounded-off to the nearest integer (scaling).[5]

These 2 sequences were then convoluted, the operation of which is explained

next (3.3.3)

The output is also quantized and rounded off as before to match the output data

width, following which the result is store in a *.txt file.

Refer to Appendix A for the MATLAB source code

3.4.3 Computing Output using Convolution

The difference equation that defines the output of an FIR filter in terms of its input

is:

𝑦 𝑛 = 𝑏0 𝑥 𝑛 + 𝑏1 𝑥 𝑛 − 1 + ………… + 𝑏𝑁 𝑥[𝑛 − 𝑁] (3.1)

Where,

x[n] is the input signal,

y [n] is the output signal,

bi are the filter coefficients, &

N is the filter order – an Nth-order filter has (N + 1) terms on the right-hand side; these

are commonly referred to as taps.

This equation can also be expressed as a convolution of the coefficient sequence bi with

the input signal:



23

𝑦 𝑛 = 𝑏𝑖 𝑥[𝑛 − 𝑖]𝑁𝑖=0 (3.2)

That is, the filter output is a weighted sum of the current and a finite number of previous

values of the input.

3.4.4 Verilog Implementation

Verilog facts: -

Phil Moorby and Prabhu Goel invented Verilog during the winter of 1983/1984 at

Automated Integrated Design Systems (renamed to Gateway Design Automation in 1985)

as a hardware modeling language. Cadence Design Systems purchased gateway Design

Automation in 1990. Cadence now has full proprietary rights to Gateway's Verilog and

the Verilog-XL simulator logic simulators.

Verilog-95: -

With the increasing success of VHDL at the time, Cadence decided to make the

language available for open standardization. Cadence transferred Verilog into the

public domain under the Open Verilog International (OVI) (now known as

Accellera) organization. Verilog was later submitted to IEEE and became IEEE

Standard 1364-1995, commonly referred to as Verilog-95.

In the same time frame Cadence initiated the creation of Verilog-A to put standards

support behind its analog simulator Spectre. Verilog-A was never intended to be a

standalone language and is a subset of Verilog-AMS, which encompassed

Verilog-95.

Verilog 2001: -

Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies

that users had found in the original Verilog standard. These extensions became

IEEE Standard 1364-2001 known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support

for (2's complement) signed nets and variables. Previously, code authors had to

perform signed-operations using awkward bit-level manipulations (for example,

the carry-out bit of a simple 8-bit addition required an explicit description of the

Boolean-algebra to determine its correct value). The same function under Verilog-

2001 can be more succinctly described by one of the built-in operators: +, -, /, *,

>>>. A generate/end generate construct (similar to VHDL's generate/end

generate) allows Verilog-2001 to control instance and statement instantiation

through normal decision-operators (case/if/else). Using generate/end generate,



24

Verilog-2001 can instantiate an array of instances, with control over the

connectivity of the individual instances. File I/O has been improved by several

new system-tasks. And finally, a few syntax additions were introduced to improve

code-readability.

Verilog-2001 is the dominant flavor of Verilog supported by the majority of

commercial EDA software packages.

Verilog Abstraction levels: -

Behavioral level: - This level describes a system by concurrent algorithms

(Behavioral). Each algorithm itself is sequential, that means it consists of a set of

instructions that are executed one after the other. Functions, Tasks and Always

blocks are the main elements. There is no regard to the structural realization of the

design.

Register-Transfer Level: - Designs using the Register-Transfer Level specify the

characteristics of a circuit by operations and the transfer of data between the

registers. An explicit clock is used. RTL design contains exact timing bounds:

operations are scheduled to occur at certain times. Modern RTL code definition is

"Any code that is synthesizable is called RTL code".

Gate Level: - Within the logic level the characteristics of a system are described by

logical links and their timing properties. All signals are discrete signals. They can

only have definite logical values (`0', `1', `X', `Z`). The usable operations are

predefined logic primitives (AND, OR, NOT etc gates). Using gate level

modeling might not be a good idea for any level of logic design. Tools like

synthesis tools generate gate level code and this net list is used for gate level

simulation and for backend.

Steps involved in designing the FIR filter in Cadence are as follows:

a) Implementation of FIR filter form I structure: -

1. From the extension of the direct form I structure shown in fig 2.2 a behavioral

module for the filter was designed having the following sub modules:

a) Multiplier Block (mul.v).

b) Summation Block (sum.v).

2. Initially the input data samples are stored in delay pipelines, which are registers.

They act as delay elements for the filter.

3. The values stored in these pipelines are multiplied with filter coefficients according

to the equation 3.1; the results are stored in registers.



25

4. The results of these successive multiplications are added together to generate the

filter output as shown in fig 2.2.

5. To perform the multiplication task a multiplier sub-block is implemented

6. Multiplier Block:

The task of this block is to multiply an 8 bit input word with a 13 bit coefficient

value to generate a 21 bit output, since this does not adhere to the hardware

requirements, the output is scaled down to 10 bits by assigning the first 10 bit of

the output to the register and then adding a carry bit to avoid overflow and

underflow error. This approach helps in maintaining the sign of the output and

also provides satisfactory results with very less loss of accuracy.

Fig 3.4: Multiplier Block diagram

7. Summation Block:

The task of this block is to add successive multiplier outputs of word length 10bits

each. Since the output of this block is 11 bits this also needs to be scaled down to

meet the hardware requirements and thereby avoid overflow and underflow errors.

The output is scaled down by comparing the first two output bits, if the bits are:

a) 11: The output assigned is [9:0], this preserves the sign bit

b) 00: The output assigned is [9:0], this preserves the sign bit

c) 10: The output assigned is max negative value for a 10-bit number (-512).



26

d) 01: The output assigned is max positive value for a 10-bit number (511).

Fig 3.5: Summation Block Diagram

b) Implementation of FIR filter form I transposed structure: -

1. From the extension of the direct form I transposed structure shown in fig 2.3

behavioral module for the filter was designed having the following sub modules:

a) Multiplier Block (mul.v).

b) Summation Block (sum.v).

2. Initially the input data samples are stored in inputreg, which is a register.

3. The value stored in the inputreg is multiplied with filter coefficients according to

the equation 3.1; the results are stored in registers.

4. The results of these successive multiplications are added together to generate the

filter output as shown in fig 2.3.

5. To perform the multiplication task a multiplier sub-block is implemented

6. Multiplier Block:

The task of this block is to multiply an 8 bit input word with a 13 bit coefficient value

to generate a 21 bit output, since this does not adhere to the hardware requirements,



27

the output is scaled down to 10 bits by assigning the first 10 bit of the output to the

register and then adding a carry bit to avoid overflow and underflow error. This

approach helps in maintaining the sign of the output and also provides satisfactory

results with very less loss of accuracy. Refer fig 3.4

7. Summation Block:

The task of this block is to add successive multiplier outputs of word length 10bits

each. Since the output of this block is 11 bits this also needs to be scaled down to

meet the hardware requirements and thereby avoid overflow and underflow errors.

Refer fig 3.5.

The output is scaled down by comparing the first two output bits, if the bits are:

a) 11: The output assigned is [9:0], this preserves the sign bit.

b) 00: The output assigned is [9:0], this preserves the sign bit.

c) 10: The output assigned is max negative value for a 10-bit number (-512).

d) 01: The output assigned is max positive value for a 10-bit number (511).

8. The summation output is stored in the delay pipelines, whose values are in turn

used to perform the further summation operation.

Refer Appendix B for code.



28

3.5 Verification Plan

In order to check the performance and reliability of the above-mentioned filters, a

verification plan was developed. The details of which are mentioned below: -

Step involved in verification: -

First the output results generated in MATLAB are store in a text file which act as

reference and benchmark for the filter operation.

A test bench is written in Verilog to test the structural code and generate filter

output.

This output is stored in a file.

The output from MATLAB is compared with the output from the Verilog code

If the compared outputs are off by + or – 1 bit error then the design is successful

and verification is complete, else the design is faulty.

Fig 3.6: Verification Plan Flowchart



29

3.6 Synthesis

Logic synthesis

Logic synthesis is the process of converting a high-level description (RTL) of

design into an optimized gate-level representation. Logic synthesis uses a standard cell

library which have simple cells, such as basic logic gates like and, or, and nor, or macro

cells, such as adder, muxes, memory, and flip-flops. Standard cells put together are called

technology library. Normally the technology library is known by the transistor size

(0.18u, 90nm).

A circuit description is written in Hardware Description Language (HDL) such as

Verilog. The designer should first understand the architectural description. Then he

should consider design constraints such as timing, area, testability, and power.

Fig 3.7: Logic Synthesis

Impact of HDL and Logic synthesis

High-level design is less prone to human error because designs are described at a

higher level of abstraction. High-level design is done without significant concern about

design constraints. Conversion from high-level design to gates is done by synthesis tools,

using various algorithms to optimize the design as a whole. This removes the problem

with varied designer styles for the different blocks in the design and suboptimal designs.

Logic synthesis tools allow technology independent design. Design reuse is possible for

technology-independent descriptions.

Steps for Synthesis of FIR filter: -



30

Fig 3.8: Logic Synthesis flow from RTL to Gates

RTL description

The designer describes the design at a high level by using RTL constructs. The

designer spends time in functional verification to ensure that the RTL description

functions correctly. After the functionality is verified, the RTL description is input to the

logic synthesis tool.

Translation

The RTL description is converted by the logic synthesis tool to an Unoptimized,

intermediate, internal representation. This process is called translation. The translator

understands the basic primitives and operators in the Verilog RTL description. Design

constraints such as area, timing, and power are not considered in the translation process.

At this point, the logic synthesis tool does a simple allocation of internal resources.

Unoptimized intermediate representation

The translation process yields an unoptimized intermediate representation of the

design. The logic synthesis tool in terms of internal data structures represents the design

internally. The Unoptimized intermediate representation is incomprehensible to the user.

Logic optimization

The logic is now optimized to remove redundant logic. Various technology

independent Boolean logic optimization techniques are used. This process is called logic



31

optimization. It is a very important step in logic synthesis, and it yields an optimized

internal representation of the design.

Technology mapping and optimization

Until this step, the design description is independent of a specific target

technology. In this step, the synthesis tool takes the internal representation and

implements the representation in gates, using the cells provided in the technology library.

In other words, the design is mapped to the desired target technology.

Suppose one wants to get one‟s IC chip fabricated at ABC Inc. ABC Inc. has

0.65-micron CMOS technology, which it calls abc_100 technology. Then, abc_100

becomes the target technology. One must therefore implement one‟s internal design

representation in gates, using the cells provided in abc_100 technology library. This is

called technology mapping. Also, the implementation should satisfy such design

constraints as timing, area, and power. Some local optimizations are done to achieve the

best results for the target technology. This is called technology optimization or

technology-dependent optimization.

Technology library

The technology library contains library cells. The term standard cell library and

the term technology library are identical and are used interchangeably. Library cells can

be basic logic gates or macro cells such as adders, ALUs, multiplexers, and special flip-

flops.

The library cells are the basic building blocks that are used for IC fabrication.

Physical layout of library cells is done first. Then, the area of each cell is computed from

the cell layout. Next, modeling techniques are used to estimate the timing and power

characteristics of each library cell. This process is called cell characterization.

Finally, each cell is described in a format that is understood by the synthesis tool. The cell

description contains information about the following:

Functionality of the cell

Area of the cell layout

Timing information about the cell

Power information about the cell

A collection of these cells is called the technology library. The synthesis tool uses

these cells to implement the design. The cells available in the technology library will

typically dominate the quality of results from synthesis tools. If the choice of cells in the

technology library is limited, the synthesis tool cannot do much in terms of optimization

for timing, area, and power.



32

Design constraints

Design constraints typically include the following:

1. Timing - The circuit must meet certain timing requirements. An internal static

timing analyzer checks timing.

2. Area - The area of the final layout must not exceed a limit.

3. Power - The power dissipation in the circuit must not exceed a threshold.

In general, there is an inverse relationship between area and timing constraints. For a

given technology library, to optimize timing (faster circuits), the design has to be

parallelized, which typically means that larger circuits have to be built. To build smaller

circuits, designers must generally compromise on circuit speed. On top of design

constraints, operating environment factors, such as input and output delays, drive

strengths, and loads, will affect the optimization for the target technology. Operating

environment factors must be input to the logic synthesis tool to ensure that circuits are

optimized for the required operating environment.

Optimized gate-level description

After the technology mapping is complete, an optimized gate-level net list

described in terms of target technology components is produced. If this net list meets the

required constraints, it is handed for final layout. Otherwise, the designer modifies the

RTL or re-constrains the design to achieve the desired results. This process is iterated

until the net list meets the required constraints. Then the layout, timing checks are done to

ensure that the circuit meets the required timing after layout, and then the IC chip is

fabricated.

There are three points to note about the synthesis flow: -

For very high-speed circuits like microprocessors, vendor technology libraries

may yield non-optimal results. Instead, design groups obtain information about

the fabrication process used by the vendor, for example, 0.65 micron CMOS

process, and build their own technology library components. The designers do cell

characterization.

Translation, logic optimization, and technology mapping are done internally in the

logic synthesis tool and are not visible to the designer. The technology library is

given to the designer. Once the technology is chosen, the designer can control

only the input RTL description and design constraint specification. Thus, writing

efficient RTL descriptions, specifying design constraints accurately, evaluating

design trade-offs, and having a good technology library are very important to



33

produce optimal digital circuits when using logic synthesis.

For submicron designs, interconnect delays are becoming a dominating factor in

the overall delay. Therefore, as geometries shrink, in order to accurately model

interconnect delays, synthesis tools will need to have a tighter link to layout, right

at the RTL level. Timing analyzers built into synthesis tools will have to account

for interconnect delays in the total delay calculation.



34

CHAPTER 4

RESULT AND ANALYSIS

4.1 MATLAB Results

4.1.1 Frequency response of FIR filter in Time and Frequency domain

Fig 4.1: Filter Response with Normalized Frequency

Fig 4.2 Filter Response with Normal frequency



35

The fig 4.1 and 4.2 shows the frequency response of the of the FIR filter. As it can

be seen from fig 4.1 the ideal and the quantized response of the filter are almost identical

thereby meeting the stop band requirement of -43.9dB with lesser hardware, thereby

reducing cost and area.

4.1.2 Test signals for FIR filter

a) Impulse response

Fig 4.3 Impulse response of FIR filter

b) Step Response

Fig 4.4 Step response of FIR filter



36

An impulse and Step signals are fed to a filter in order to determine the stability of the

filter. An impulse signal is applied to a filter to test the response in case of sudden change

in the input level. Whereas in case of a step input the input level is suddenly made high

and held for some time, then made to zero.

The Figures 4.3 and 4.4 show the impulse and step response of the filter and prove that

the designed filter is stable.

c) Composite Sine wave

A composite sine wave consists of a mixture of 2 sine waves one of which is in-band and

other is out-band. The frequencies of the signal used to test are in-band – 1500 Hz, out-

band 3500 Hz. Since the in-band sine wave is below the cut off frequency it is passed by

the filter, whereas the out-band sine wave is rejected as it is above the cut-off frequency.

The above facts are verified in the below figures.

Fig 4.5: Composite input signal in Time domain



37

Fig 4.6: Composite input signal in Frequency domain

Fig 4.7: Filter output for composite input signal in Time domain



38

Fig 4.8: Filter output for composite input signal in Frequency domain

4.2 VERILOG results

a) Impulse input

Table 4.1: Impulse response results

Input values MATLAB output Verilog output

127

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

-1

-1

2

3

-4

-6

8

10

-14

-21

37

114

0

0

0

0

0

-1

-1

2

3

-4

-6

8

10

-14

-21

37

114



39

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

114

37

−21

−14

10

8

−6

−4

3

2

−1

−1

0

0

0

0

0

114

37

-21

-14

10

8

-6

-4

3

2

-1

-1

0

0

0

0

0

b) Step response

Table 4.2: Step response results

Input values MATLAB output Verilog output

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

127

127

127

127

127

127

0

0

0

0

0

1

0

-1

0

3

-1

-6

1

12

-3

-24

13

127

241

278

257

242

253

260

0

0

0

0

0

-1

0

-2

0

3

-1

-7

1

11

-3

-24

13

127

241

278

257

243

253

261



40

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

127

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

255

251

253

255

254

253

254

254

254

254

254

254

254

254

254

254

254

254

254

254

254

253

254

255

253

251

255

260

253

242

257

278

241

127

13

-24

-3

12

1

-6

-1

3

0

-1

0

1

0

0

0

0

0

255

251

254

256

255

254

254

254

254

254

254

254

254

254

254

254

254

254

254

254

254

254

255

256

254

251

255

261

253

243

257

278

241

127

13

-24

-3

11

1

-7

-1

3

0

-2

-1

0

0

0

0

0

0



41

c) Composite sine wave input

Table 4.3: Composite Sine wave results

Input values MATLAB output Verilog Output

102

57

-18

-126

-14

48

115

-15

-86

-72

31

117

18

-48

-119

24

73

87

-47

-102

-31

57

115

-24

-69

-96

60

87

47

-72

-102

15

73

96

-64

-78

-60

87

86

0

-86

-87

60

78

64

-96

0

0

0

0

0

-2

1

4

-1

-8

0

15

1

-30

5

119

171

42

-155

-171

31

201

118

-113

-202

-40

171

170

-40

-201

-114

113

200

40

-170

-170

40

201

114

-114

-201

-40

171

171

-40

-201

0

0

0

0

0

-1

-1

4

-1

-8

1

16

1

-28

5

119

173

42

-154

-172

32

199

118

-111

-202

-42

170

169

-42

-202

-114

115

202

38

-172

-172

40

201

112

-113

-201

-39

170

172

-43

-203



42

-73

-15

102

72

-47

-87

-60

96

69

24

-115

-57

31

102

-114

113

200

40

-170

-171

39

201

114

-114

-201

-39

171

170

-40

-200

-113

114

202

40

-173

-172

44

204

105

-121

-184

-26

135

123

15

-33

-4

17

3

-9

-2

4

1

-2

-1

0

0

0

0

-115

113

201

39

-171

-171

39

200

115

-115

-200

-39

172

172

-39

-201

-113

115

203

42

-174

-171

44

203

104

-120

-184

-26

136

123

15

-34

-3

17

2

-8

-2

4

2

-1

-1

0

0

0

0



43

4.3 Synthesis Results

After the Verilog design was successfully verified at the RTL level, the synthesis

of the design was done under constraints to obtain a gate level circuit and implementation

of the FIR filter for Form I and Form I transposed. The gate level circuits of Form I and

Form I transposed are shown below.

Fig 4.9: Gate level circuit for Form I FIR filter



44

Fig 4.10: Gate level circuit for Form I Transposed FIR filter



45

4.4 Operating Frequency and Area reports

4.4.1 Operating Frequency

Table 4.4: Operating Frequency Report

Filter Type Operating Frequency Slack (ps)

Form I 83.33 MHZ 0

Form I Transposed 83.33 MHZ 6991

4.4.2 Area reports

Table 4.5: Area report

Filter Type Total Area

Form I 21323.52 sq.microns

Form I Transposed 14616.50 sq.microns



46

CHAPTER 5

FUTURE SCOPE

Any work, whatsoever precise it may be, always has some scope of improvement.

On the same lines, there is room to believe that there is a lot of scope of improvement in

the present. FIR filter can be implemented FPGA, microcontrollers and by using other

windows. The length of filter coefficient can be decreased further. Real time filter can be

implemented on various other frequency ranges i.e. Audio frequency range etc. The input,

coefficients, multiplier and summation word lengths can be further decreased to reduce

hardware. The operating frequency can be further increased. Work is done only for fixed-

point sequences, floating-point sequences can be included.



47

CHAPTER 6

CONCLUSION

The FIR filters in FORM I and FORM I transposed were successfully designed &

verified. The Filter was implemented in MATLAB and VERILOG; results were verified

using the verification plans. After the verification gate level synthesis was performed,

thereby generating a gate level circuit for both filters using TSMC 180nm technology.

The Area and timing report were successfully generated for both filters, thereby

concluding that FIR FORM I transposed filter consumes approximately half the area of

FORM I filter and is comparatively faster than the equivalent FIR FORM I filter.



48

CHAPTER 7

REFERENCES

[1] Sanjit K. Mitra, “Digital Signal Processing- A Computer based Approach”, TMH,

2nd Edition.

[2] S. Salivahanan, A. Vallavaraj, C. Gnanaapriya, “Digital Signal Processing”, TMH, 6th

Reprint, 2002

[3] Tseng B, Peterson H.E., Signals, Systems and Computers, Twenty-Second Asilomar

Conference on Windowing Techniques, Volume 1, 1988, pp 152-156.

[4] Siohon P, Benslimane A, Acoustics, Speech, and Signal Processing, IEEE

International Conference on ICASSP, Volume 9, Part1, 1984, pp 563-566.

[5] Smith, M.J.T, Circuits and Systems, IEEE International Symposium on Digital Object

Identifier, Volume 1, 1989, pp 347-350

[6] Dusan M. Kodek , “Performance Limit of Finite Word length FIR Digital Filters”,

IEEE Transaction on Signal Processing, Vol. 53, No. 7, July 2005

[7] http:// www.dspguru.com/dsp/faqs/fir

[8] http:// en.wikipedia.org/wiki/Finite_impulse_response

[9] http:// www.mathworks.com/matlabcentral

http://www.dspguru.com/dsp/faqs/fir

http://www.mathworks.com/matlabcentral



49

CHAPTER 8

APPENDICES

APPENDIX – A

MATLAB CODE

%%%% Define parameters

data_width = 08; %input data width

coef_width = 13; %coefficient data width

filter_order = 31; %31-order FIR filter

sampling_freq = 8e3; %Sampling Frequency is 8 KHz

cutoff_freq = 2e3; %Cut-off Frequency is 2 KHz

%% Calculate Parameters

max_data = 2^(data_width-1)-1; %defining input data range

min_data = -max_data; %Range is -128 to 127

max_coef = 2^(coef_width-1)-1; %defining coefficient data range

min_coef = -max_coef; %Range is -4096 to 4095

N = filter_order; %31

Fs = 2*(cutoff_freq/sampling_freq); %Normalized Sampling frequency=0.5

Fsam = sampling_freq/1e3; %Fsam = 8

%%Determining Filter Coefficients

h_ideal = fir1(N, Fs,hann(N+1)); %Caculating Filter Coefficients

h = round(max_coef*h_ideal); %Scaling the Coefficients

%%Time Domain Filter Response Plotting

figure(1);

[h2,o]=freqz(h,1,2^10);

m=20*log10(abs(h2)/max_coef);

[h3,o2]=freqz(h_ideal,1,2^10);

m2=20*log10(abs(h3));

plot(o2/pi,m2,'r-',o/pi,m,'b--');

xlabel('NORMLISED FREQUENCY (Radians)');

ylabel('GAIN (in dB)');

legend('ideal','quantised');

title('FIR RESPONSE');

grid on;

zoom on;



50

%%Generating Square Response

input = zeros(127,1); %Generates 300 0s in 1 column

input(41) = max_data; %Makes the 1st element of input as 127

input(42) = max_data;







































%%Generating Impulse Response

input2 = zeros(300,1);

input2(40)= max_data;

input2(80)= max_data;

%Computing Step Response



51

output = conv(h,input); %Generates the step output

os1 = round( output / (2^11) );

%Computing Impulse Response

output2 = conv(h,input2); %Generates the impulse output

os2 = round( output2 / (2^11) );

%% Step response plotting

figure(2);

square_output = output; %impulse output

sz = size(output); %there are 331 elements in 1 column i.e. [331 1]

max_x = max(sz);%max_x = 331

xline = linspace (0,max_x - 1,max_x); %Generates 331 linearly spaced vectors

plot (xline,output,'r');

title ('TIME DOMAIN DISPLAY OF STEP RESPONSE');

axis([0 120 -5e5 2e6]); %plotting range

xlabel ('TIME');

ylabel ('AMPLITUDE ');

grid on;

zoom on;

outfile1 = fopen ('sqr_in.txt','w'); %creates a file by the name 'sqr_in.txt' and gives

permission to write

fprintf (outfile1, '%d\n', input); %stores the step input in the file

fclose(outfile1);

outfile1 = fopen ('sqr_out.txt','w'); %creates a file by the name 'sqr_out.txt'

fprintf (outfile1, '%d\n', os1); %stores the step output in the file

fclose(outfile1);

%% impulse response plotting

figure(3);

impulse_output = output2; %impulse output

sz2 = size(output2); %there are 331 elements in 1 column i.e. [331 1]

max_x2 = max(sz2);%max_x = 331

xline = linspace (0,max_x2 - 1,max_x2); %Generates 331 linearly spaced vectors

plot (xline,output2,'b');

title ('TIME DOMAIN DISPLAY OF IMPULSE RESPONSE');

axis([0 120 -5e5 2e6]); %plotting range

xlabel ('TIME');


grid on;

zoom on;

outfile3 = fopen ('impulse_in.txt','w'); %creates a file by the name 'imp_in.txt' and

gives permission to write

fprintf (outfile3, '%d\n', input2); %stores the impulse input in the file

fclose(outfile3);

outfile3 = fopen ('impulse_out.txt','w'); %creates a file by the name 'imp_out.txt'

fprintf (outfile3, '%d\n', os2); %stores the impulse output in the file

fclose(outfile3);

%% Frequency Domain Plotting



52

to_plot_ideal = conv(h_ideal,input); %Unquantized output

to_plot = output; %Quantized output

freqdat = fft(to_plot); %fft of Quantized output

absdat = abs(freqdat); %Taking absolute of the fft

maxdat = max (absdat); %maxdat=5.232340026559121*10^5

logdat = 20*log10 (absdat/maxdat); %dB plot of Quantized output

freqdati = fft(to_plot_ideal); %fft of UnQuantized output

absdati = abs(freqdati); %Taking absolute of the fft

maxdati = max(absdati); %Taking absolute of the fft

logdat_ideal = 20*log10(absdati/maxdati); %dB plot of UnQuantized output

figure(4);

sz = size(to_plot); %there are 331 elements in 1 column i.e. [331 1]

numpts = max(sz);%numpts = 331

freq_res =1/numpts; %freq_res = 0.003021148036254

xline = linspace (0, ( (1/2)- freq_res), round(numpts/2) ) * Fsam;

%Generates 166 linearly spaced vectors

plot (xline, logdat(1: round(numpts/2) ), 'b', xline, logdat_ideal(1 : round(numpts/2) ), 'r');

%Plotting Unquantized(ideal) and Quantized response

title('FREQUENCY DOMAIN DISPLAY OF FILTER RESPONSE ');

legend('ideal','quantised');

grid on;

zoom on;

xlabel ('FREQUENCY - Khz');

ylabel ('MAGNITUDE - dB');

%% Sine input Response

step = 1:60;

%%%% inband freq is 1.5 KHZ at 0 dB (FS)

%%%% outband Freq is 3.6 Khz at -6dB (half scale)

sine_inband = round(0.8*max_data * sin(2*pi*0.1875*step));

sine_oband = round(0.2*max_data * sin(2*pi*(3.6/8)*step));

sine_inp = sine_inband + sine_oband;

figure(5);

plot(sine_inp);

title ('COMPOSITE INPUT SIGNAL');

xlabel ('TIME');


grid on;

zoom on;

output = conv(h,sine_inp/2);

sz3 = size(output); %there are 331 elements in 1 column i.e. [331 1]

max_x3 = max(sz3);%max_x = 331

outfile2 = fopen ('sin_inbnd.txt','w'); % creates a file by the name 'sin_inbnd.txt'

fprintf (outfile2, '%d\n', sine_inp); %stores the composite sine input in the file

fclose(outfile2);

outfile2 = fopen ('sin_outputinbnd.txt','w'); %creates a file by the name

'imp_out.txt' and gives permission to write



53

fprintf (outfile2, '%d\n', round(output/2^11)); %stores the sine output in the file

fclose(outfile2);

figure(6);

plot(output/2^11);

title ('FILTER OUTPUT');

xlabel ('TIME');

ylabel ('AMPLITUDE');

grid on;

zoom on;

% sine response plotting

% Frequency Domain Plotting of Input of filter

figure(7);

to_plot = sine_inp;

freqdat = fft(to_plot); %fft of the composite sine wave input

absdat = abs(freqdat);

maxdat = max(absdat); %maxdat = 1.212950912526383*10^5

logdat = 20*log10(absdat/maxdat);

sz = size(to_plot); %sz = [1 3000]

numpts = max(sz); %numpts = 3000

freq_res = 1/numpts; %freq_res = 0.00033333

xline = linspace ( 0, ( (1/2) - freq_res) , round(numpts/2) ) *Fsam;

plot (xline, logdat(1 : round(numpts/2) ) , 'r-');

title ('FREQUENCY RESPONSE AT INPUT OF FIR FILTER ' );

grid on ;

zoom on ;



axis ([0 5 -60 0]); %plot ranges

% Frequency domain plotting of output of filter

figure(8);

to_plot = output;

freqdat = fft(to_plot); %fft of the output

absdat = abs(freqdat);

maxdat = max(absdat); %maxdat = 6.669739002463810*10^8

logdat = 20*log10(absdat/maxdat);

sz = size(to_plot); %sz = [1 3031]

numpts = max(sz) %numpts = 3031

freq_res = 1/numpts; %freq_res = 0.000329924

xline = linspace ( 0, ( (1/2) - freq_res) , round(numpts/2) ) *Fsam;

plot (xline, logdat(1 : round(numpts/2) ) , 'r-');

title ('FREQUENCY RESPONSE TO INPUT OF FIR FILTER ' );

grid on ;

zoom on ;



axis ([0 5 -60 0]);



54

APPENDIX – B

VERILOG CODES

FIR FORM I FILTER CODES:

a) filter_behav.v

`timescale 1 ns / 1 ns

module filter_new

(

clk,

clk_enable,

reset,

filter_in,

filter_out

);

input clk;

input clk_enable;

input reset;

input signed [7:0] filter_in;

output signed [9:0] filter_out;

reg signed[9:0] filter_out;

/// coefficients constants

parameter signed [12:0] coeff1 = 13'd0;

parameter signed [12:0] coeff2 = -13'd1;




















55














//signals

reg signed [7:0] delay_pipeline [0:31] ;

reg signed [9:0] output_register;

// product wires

wire signed [9:0] product[0:31];

//sum wires

wire signed [9:0] sum [0:31] ;

// Block Statements

always @( posedge clk or posedge reset)

begin: Delay_Pipeline_process

if (reset == 1'b1) begin

delay_pipeline[0] <= 0;



















56
















end

else begin

if (clk_enable == 1'b1) begin

delay_pipeline[0] <= filter_in;

delay_pipeline[1] <= delay_pipeline[0];































end

end



57

end // Delay_Pipeline_process

/// product calculation and assignment

mul m1(.a(delay_pipeline[0]),.b(coeff1),.c(product[0]));
































parameter const = 10'd0;

//summation of the products..

sum s0(.a(product[0]),.b(const),.c(sum[0]));

sum s1(.a(product[1]),.b(sum[0]),.c(sum[1]));












58






















always @ (posedge clk or posedge reset)

begin: Output_Register_process


output_register = 0;

end

else begin


output_register = sum[31];

filter_out = output_register;

end

end

end // Output_Register_process

// Assignment Statements

endmodule // FIR_filter

b) mul.v

`timescale 1ns/1ns

module mul(a,b,c);

input signed [7:0]a;



59

input signed [12:0]b;

output signed [9:0]c;

reg signed [9:0] c;

reg signed [20:0] c_init ;

always@(a,b)

begin

c_init = a * b ;

c = c_init[20:11] + c_init[10] ;

end

endmodule

c) sum.v

`timescale 1ns/1ns

module sum(a,b,c);




wire signed [10:0] c_init ;

reg signed [9:0] c;

assign c_init =a+b;

always @(c_init)

begin

if (c_init[10:9] == 2'b00)

c = c_init[9:0];

else if (c_init[10:9] == 2'b11)

c = c_init[9:0];

else if (c_init[10:9] == 2'b01) ///overflow

c = 10'h1FF;

else

c = 10'h200 ;

end

endmodule



60

d) filter_tb.v

`timescale 1ns/1ns

module filter_tb();

// Signals

reg clk;

reg clk_enable;

reg reset;

reg signed [7:0] filter_in;

wire signed [9:0] filter_out;

filter_new uut

(

.clk(clk),

.clk_enable(clk_enable),

.reset(reset),

.filter_in(filter_in),

.filter_out(filter_out)

);

initial begin

clk=0;

forever #25 clk=~clk;

end

initial begin

reset=1;

#10 reset =0;

end

initial begin

clk_enable=0;

count = 0;

#50 clk_enable=1;

end

integer i=0;

integer j=0;

integer outfile1;

always@( posedge clk)

begin



61

// composite signal

#50 filter_in = 8'd102;

#50 filter_in = 8'd57;

#50 filter_in = -8'd18;

#50 filter_in = -8'd126;

#50 filter_in = -8'd14;


#50 filter_in = 8'd115;

#50 filter_in = -8'd15;

#50 filter_in = -8'd86;

#50 filter_in = -8'd72;


#50 filter_in = 8'd117;


#50 filter_in = -8'd48;

#50 filter_in = -8'd119;




#50 filter_in = -8'd47;

#50 filter_in = -8'd102;

#50 filter_in = -8'd31;


#50 filter_in = 8'd115;

#50 filter_in = -8'd24;

#50 filter_in = -8'd69;

#50 filter_in = -8'd96;




#50 filter_in = -8'd72;

#50 filter_in = -8'd102;




#50 filter_in = -8'd64;

#50 filter_in = -8'd78;

#50 filter_in = -8'd60;




#50 filter_in = -8'd86;

#50 filter_in = -8'd87;




#50 filter_in = -8'd96;

#50 filter_in = -8'd73;

#50 filter_in = -8'd15;

#50 filter_in = 8'd102;




62

#50 filter_in = -8'd47;

#50 filter_in = -8'd87;

#50 filter_in = -8'd60;




#50 filter_in = -8'd115;

#50 filter_in = -8'd57;


#50 filter_in = 8'd102;

// delay





























// sin inband 1500 hz



#50 filter_in = -8'd39;

#50 filter_in = -8'd102;

#50 filter_in = -8'd39;



63




#50 filter_in = -8'd94;

#50 filter_in = -8'd72;


#50 filter_in = 8'd102;


#50 filter_in = -8'd72;

#50 filter_in = -8'd94;




#50 filter_in = -8'd39;

#50 filter_in = -8'd102;

#50 filter_in = -8'd39;




#50 filter_in = -8'd94;

#50 filter_in = -8'd72;


#50 filter_in = 8'd102;


#50 filter_in = -8'd72;

#50 filter_in = -8'd94;




#50 filter_in = -8'd39;

#50 filter_in = -8'd102;

#50 filter_in = -8'd39;




#50 filter_in = -8'd94;

#50 filter_in = -8'd72;


#50 filter_in = 8'd102;


#50 filter_in = -8'd72;

#50 filter_in = -8'd94;




#50 filter_in = -8'd39;

#50 filter_in = -8'd102;

#50 filter_in = -8'd39;




#50 filter_in = -8'd94;



64

#50 filter_in = -8'd72;


#50 filter_in = 8'd102;

// delay





























// impulser input

#50 filter_in = 8'd127 ;













65































//square wave input

for(i=0;i<40;i=i+1)

begin

#50 filter_in = 8'd127;

end

for(j=0;j<40;j=j+1)

begin


end

end

initial begin



66

outfile1 = $fopen ("output.txt","w");

end

always@( posedge(clk))

begin

$fwrite (outfile1, "out = %d \n", filter_out);

end

initial

begin

#14850 $finish;

end

endmodule

FORM I TRANSPOSED FIR FILTER

a) filter_transposed.v

`timescale 1 ns / 1 ns

module filter_trans

(

clk,

clk_enable,

reset,

filter_in,

filter_out

);

input clk;

input clk_enable;

input reset;

input signed [7:0] filter_in;

output signed [9:0] filter_out;

reg signed[9:0] filter_out;

/// coefficients constants






67






























//signals

reg signed [9:0] delay_pipeline [0:31] ;

reg signed [9:0] output_register;

reg signed [7:0] inputreg;

wire signed [9:0] sum [0:31] ;

wire signed [9:0] finalsum;

// product wires

wire signed [9:0] product [0:31];



68


begin: input_reg_process


inputreg <= 0;

end

else begin


inputreg <= filter_in;

end

end

end // input_reg_process

// Block Statements

always @( posedge clk or posedge reset)

begin: Delay_Pipeline_process


































end

else begin



69


delay_pipeline[1] <= sum[1];































end

end

end // Delay_Pipeline_process

/// product calculation and assignment

mul m1(.a(inputreg),.b(coeff1),.c(product[0]));












70























//summuation of the products..

sum s0(.a(product[31]),.b(const),.c(sum[0]));

sum s1(.a(product[30]),.b(delay_pipeline[0]),.c(sum[1]));




























71






assign finalsum = delay_pipeline[31];


begin: Output_Register_process


output_register <= 0;

end

else begin


output_register <= finalsum;

filter_out = output_register;

end

end

end // Output_Register_process

// Assignment Statements

endmodule // FIR_filter

b) mul.v

`timescale 1ns/1ns

module mul(a,b,c);




reg signed [9:0] c;

reg signed [20:0] c_init ;

always@(a,b)

begin

c_init = a * b ;

c = c_init[20:11] + c_init[10] ;

end



72

endmodule

c) sum.v

`timescale 1ns/1ns

module sum(a,b,c);




wire signed [10:0] c_init ;

reg signed [9:0] c;

assign c_init =a+b;

always @(c_init)

begin

if (c_init[10:9] == 2'b00)

c = c_init[9:0];

else if (c_init[10:9] == 2'b11)

c = c_init[9:0];

else if (c_init[10:9] == 2'b01) ///overflow

c = 10'h1FF;

else

c = 10'h200 ;

end

endmodule

d) filter_ttb.v

`timescale 1ns/1ns

module filter_ttb();

// Signals

reg clk;

reg clk_enable;

reg reset; // boolean

reg signed [7:0] filter_in;

wire signed [9:0] filter_out;

filter_trans uut

(

.clk(clk),

.clk_enable(clk_enable),

.reset(reset),

.filter_in(filter_in),



73

.filter_out(filter_out)

);

initial begin

clk=0;

forever #25 clk=~clk;

end

initial begin

reset=1;

#10 reset =0;

end

initial begin

clk_enable=0;

#50 clk_enable=1;

end

integer i=0;

integer j=0;

integer outfile1;

always@( posedge clk)

begin

// composite signal

#50 filter_in = 8'd102;


#50 filter_in = -8'd18;

#50 filter_in = -8'd126;

#50 filter_in = -8'd14;


#50 filter_in = 8'd115;

#50 filter_in = -8'd15;

#50 filter_in = -8'd86;

#50 filter_in = -8'd72;


#50 filter_in = 8'd117;


#50 filter_in = -8'd48;

#50 filter_in = -8'd119;




#50 filter_in = -8'd47;



74

#50 filter_in = -8'd102;

#50 filter_in = -8'd31;


#50 filter_in = 8'd115;

#50 filter_in = -8'd24;

#50 filter_in = -8'd69;

#50 filter_in = -8'd96;




#50 filter_in = -8'd72;

#50 filter_in = -8'd102;




#50 filter_in = -8'd64;

#50 filter_in = -8'd78;

#50 filter_in = -8'd60;




#50 filter_in = -8'd86;

#50 filter_in = -8'd87;




#50 filter_in = -8'd96;

#50 filter_in = -8'd73;

#50 filter_in = -8'd15;

#50 filter_in = 8'd102;


#50 filter_in = -8'd47;

#50 filter_in = -8'd87;

#50 filter_in = -8'd60;




#50 filter_in = -8'd115;

#50 filter_in = -8'd57;


#50 filter_in = 8'd102;

// delay









75























// sin inband 1500 hz



#50 filter_in = -8'd39;

#50 filter_in = -8'd102;

#50 filter_in = -8'd39;




#50 filter_in = -8'd94;

#50 filter_in = -8'd72;


#50 filter_in = 8'd102;


#50 filter_in = -8'd72;

#50 filter_in = -8'd94;




#50 filter_in = -8'd39;

#50 filter_in = -8'd102;

#50 filter_in = -8'd39;




76



#50 filter_in = -8'd94;

#50 filter_in = -8'd72;


#50 filter_in = 8'd102;


#50 filter_in = -8'd72;

#50 filter_in = -8'd94;




#50 filter_in = -8'd39;

#50 filter_in = -8'd102;

#50 filter_in = -8'd39;




#50 filter_in = -8'd94;

#50 filter_in = -8'd72;


#50 filter_in = 8'd102;


#50 filter_in = -8'd72;

#50 filter_in = -8'd94;




#50 filter_in = -8'd39;

#50 filter_in = -8'd102;

#50 filter_in = -8'd39;




#50 filter_in = -8'd94;

#50 filter_in = -8'd72;


#50 filter_in = 8'd102;

// delay














77


















// impulser input

#50 filter_in = 8'd127 ;






























78














//square wave input

for(i=0;i<40;i=i+1)

begin

#50 filter_in = 8'd127;

end

for(j=0;j<40;j=j+1)

begin


end

end

initial begin

outfile1 = $fopen ("output.txt","w");

end

always@( posedge(clk))

begin

$fwrite (outfile1, "out = %d \n", filter_out);

end

initial

begin



79

#14850 $finish;

end

endmodule



80

WAVEFORMS:

a) Waveform for form I FIR filter



81

b) Waveform form I transposed FIR filter

APPENDIX – C



82

SYNTHESIS REPORT

FORM I FIR FILTER

Constraint file

create_clock -name clk -period 12 -waveform {0 6} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]

set_clock_transition -fall 0.1 [get_clocks "clk"]

set_clock_uncertainty 0.5 [get_ports "clk"]

set_input_delay -max 1.0 [get_ports "clk_enable"] -clock [get_clocks "clk"]

set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"]

set_input_delay -max 1.0 [get_ports "filter_in"] -clock [get_clocks "clk"]

set_output_delay -max 1.5 [get_ports "filter_out"] -clock [get_clocks "clk"]

Synthesis RC script

# *************************************************

# * Local Variable settings for this design

# *************************************************

include load_etc.tcl

set LOCAL_DIR "[exec pwd]"

set SYNTH_DIR $LOCAL_DIR/work

set RTL_DIR $LOCAL_DIR/rtl

set LIB_DIR $LOCAL_DIR/library

set TCL_DIR $LOCAL_DIR/tcl

set OUT_DIR $LOCAL_DIR/outputs

set LOG_DIR $LOCAL_DIR/logs

set RPT_DIR $LOCAL_DIR/reports

set LIBRARY {slow_normal.lib slow_highvt.lib}

set FILE_LIST {filter_behav.v mul.v sum.v}

set WL_MODEL "tsmc18_wl10"

set WL_MODE enclosed

set SYN_EFFORT medium

set MAP_EFFORT medium

set DESIGN filter_new

# *********************************************************

# * Set all the search paths & Create output directories

# *********************************************************

set_attr hdl_search_path ${RTL_DIR} /

set_attr lib_search_path ${LIB_DIR} /

set_attr script_search_path ${TCL_DIR} /

if {![file exists ${LOG_DIR}]} {

file mkdir ${LOG_DIR}

puts "Creating directory ${LOG_DIR}" }



83

if {![file exists ${OUT_DIR}]} {

file mkdir ${OUT_DIR}

puts "Creating directory ${OUT_DIR}" }

if {![file exists ${RPT_DIR}]} {

file mkdir ${RPT_DIR}

puts "Creating directory ${RPT_DIR}" }

# *********************************************************

# *** SETUP LIBRARY and WIRELOADS *************************

# *********************************************************

set_attribute wireload_mode $WL_MODE /

set_attribute information_level 7 /

set_attribute library $LIBRARY

set THE_DATE [exec date +%m%d.%H%M]

# THESE SETTINGS ARE FOR DIAGNOSTIC PURPOSES AND STRONGLY

RECOMMENDED

# *********************************************************

# * Define Tool Setup and Compatibility

# *********************************************************

#set_attr hdl_max_loop_limit 1024 /

#set_attr hdl_array_naming_style %s_reg\[%d\] /

#set_attr gen_module_prefix G2C_DP_ /

# *********************************************************

# * Define Tool Diagnostic Level

# *********************************************************

set_attr information_level 9 /

#set global_map_report 1

#set map_fancy_names 1

#set iopt_stats 1

set_attr map_timing 1 /

#set_attr hdl_track_filename_row_col true /

####################################################################

## Load Design

####################################################################

read_hdl $FILE_LIST

elaborate $DESIGN

check_design $DESIGN -unresolved

####################################################################

## Constraints Setup

####################################################################

read_sdc ./constraints_serial_adder.g

#####################################################################

## Synthesizing to generic



84

#####################################################################syn

thesize -to_generic -eff $SYN_EFFORT

report datapath > $RPT_DIR/${DESIGN}_datapath_generic.rpt

#####################################################################

## Synthesizing to gates

#####################################################################

synthesize -to_mapped -eff $MAP_EFFORT -no_incr

report datapath > $RPT_DIR/${DESIGN}_datapath_map.rpt

#foreach cg [find / -cost_group *] {

# report timing -cost_group [list $cg] > $_REPORTS_PATH/${DESIGN}_[basename

$cg]_post_map.rpt

#}

##Intermediate netlist for LEC verification..

#write_hdl -lec > ${OUT_DIR}/${DESIGN}_intermediate.v

#write_do_lec -revised_design ${OUT_DIR}/${DESIGN}_intermediate.v -logfile

${_LOG_PATH}/#rtl2intermediate.lec.log > ${OUT_DIR}/rtl2intermediate.lec.do

#####################################################################

## Incremental Synthesis

#####################################################################

## Uncomment to remove assigns & insert tiehilo cells during Incremental synthesis

##set_attribute remove_assigns true /

##set_remove_assign_options -buffer_or_inverter <libcell> -design <design|subdesign>

##set_attribute use_tiehilo_for_const <none|duplicate|unique> /

synthesize -to_mapped -eff $MAP_EFFORT -incr

#foreach cg [find / -cost_group -null_ok *] {


$cg]_post_incr.rpt

#}

#####################################################################

## Write Output file set (verilog, SDC, config, etc.)

#####################################################################

#write_encounter design -basename <path & base filename> -lef <lef_file(s)>

report area > $RPT_DIR/${DESIGN}_area.rpt

report datapath > $RPT_DIR/${DESIGN}_datapath_incr.rpt

report gates > $RPT_DIR/${DESIGN}_gates.rpt

write_design -basename ${OUT_DIR}/${DESIGN}_m

write_hdl > ${OUT_DIR}/${DESIGN}.vg

write_script > ${OUT_DIR}/${DESIGN}_m.script

write_sdc > ${OUT_DIR}/${DESIGN}_m.sdc

#################################

### write_do_lec



85

#################################

#write_do_lec -golden_design ${OUT_DIR}/${DESIGN}_intermediate.v -

revised_design #${OUT_DIR}/${DESIGN}_m.v -logfile

${_LOG_PATH}/intermediate2final.lec.log > #${OUT_DIR}/intermediate2final.lec.do

##Uncomment if the RTL is to be compared with the final netlist..

##write_do_lec -revised_design ${OUT_DIR}/${DESIGN}_m.v -logfile

${_LOG_PATH}/#rtl2final.lec.log > ${OUT_DIR}/rtl2final.lec.do

puts "============================"

puts "Synthesis Finished ........."

puts "============================"

#file copy [get_attr stdout_log /] ${_LOG_PATH}/.

##quit

# *********************************************************

# * ATTRIBUTE Settings to Support Synopsys Pragmas

# *********************************************************

#set_attribute input_pragma_keyword synopsys /

#set_attribute synthesis_off_command translate_off /

#set_attribute synthesis_on_command translate_on /

#set_attribute input_case_cover_pragma {full_case} /

#set_attribute input_case_decode_pragma {parallel_case} /

#set_attr input_synchro_reset_pragma sync_set_reset /

#set_attr input_synchro_reset_blk_pragma sync_set_reset_local /

#set_attr input_asynchro_reset_pragma async_set_reset /

#set_attr input_asynchro_reset_blk_pragma async_set_reset_local /

# *********************************************************

# * Set maximum print of messages

# *********************************************************

#set_attr max_print 1 /messages/LBR/LBR-30




#set_attr max_print 1 [find / -message LBR-72]


# *********************************************************

# * Other common optimization directives

# *********************************************************

# You can have this attribute true almost always.

# set_attr endpoint_slack_opto true /

# Turn this medium or high if you have Multi-VT libraries.

# set_attr lp_multi_vt_optimization_effort medium /

# Turn this on always to optimize logic to reset arcs.

# set_attr time_recovery_arcs true /



86

Gates area report

============================================================

Generated by: Encounter(R) RTL Compiler v08.10-s121_1

Generated on: May 04 2010 05:26:46 PM

Module: filter_new

Technology libraries: slow_normal 1.0

slow_highvt 1.0

Operating conditions: slow (balanced_tree)

Wireload mode: enclosed

Area mode: timing library

============================================================

Gate Instances Area Library

---------------------------------------------------

ACCSIHCONX4TH 1 8.467 slow_highvt

ADDFX1 121 2134.440 slow_normal

ADDFXL 1 17.640 slow_normal

ADDHX1 10 105.840 slow_normal



ADDHXL 1 10.584 slow_normal

AND2X2 81 285.768 slow_normal







AO21X2 9 44.453 slow_normal


AOI211X1 2 8.467 slow_normal

AOI21BX2 6 33.869 slow_normal








AOI21XLTH 3 10.584 slow_highvt

AOI221XL 1 5.645 slow_normal



AOI2B1X1 7 34.574 slow_normal

AOI2BB1X1 1 4.234 slow_normal









BMXIX2 1 16.934 slow_normal

BMXIX4 1 25.402 slow_normal

BUFX2 39 110.074 slow_normal





87

CLKAND2X2 2 7.056 slow_normal


CLKBUFX2 2 5.645 slow_normal



CLKINVX1 2 4.234 slow_normal







CLKNAND2X12 1 11.995 slow_normal


CLKNAND2X2TH 2 5.645 slow_highvt



DFFRHQX2 8 152.410 slow_normal



DFFRQX2 23 357.034 slow_normal

DFFRQX4 1 16.229 slow_normal

INVX1 50 105.840 slow_normal

INVX1TH 1 2.117 slow_highvt


INVX2TH 2 4.234 slow_highvt




INVXL 5 10.584 slow_normal

INVXLTH 1 2.117 slow_highvt

MX2X4 1 8.467 slow_normal

MX2XL 1 6.350 slow_normal

MXI2X1 9 50.803 slow_normal

MXI2XL 4 22.579 slow_normal

NAND2BX1 1 3.528 slow_normal



NAND2BX4TH 1 5.645 slow_highvt


NAND2BXL 2 7.056 slow_normal

NAND2X1 16 45.158 slow_normal




NAND2X4TH 1 4.939 slow_highvt











NAND3XL 4 14.112 slow_normal


NOR2BX1 52 183.456 slow_normal




88


NOR2BXLTH 2 7.056 slow_highvt

NOR2X1 38 107.251 slow_normal






NOR2XL 4 11.290 slow_normal



NOR3XLTH 1 3.528 slow_highvt



OA21X1 3 14.818 slow_normal



OA21XL 2 9.878 slow_normal


OAI211X2 1 4.939 slow_normal


OAI211XL 1 4.234 slow_normal

OAI21BX1 22 108.662 slow_normal







OAI21XLTH 3 10.584 slow_highvt




OAI2B1X1 8 39.514 slow_normal




OAI2BB1X1 27 114.307 slow_normal


OAI2BB1X2TH 1 4.939 slow_highvt


OAI2BB1X4TH 1 6.350 slow_highvt





OR2X2 20 70.560 slow_normal




SDFFHQX8 1 27.518 slow_normal

SDFFQX1 3 52.920 slow_normal

SDFFQXL 6 105.840 slow_normal

SDFFRQX2 179 3536.467 slow_normal

SDFFRXL 2 40.925 slow_normal

XNOR2X1 99 558.835 slow_normal



XNOR2XL 13 73.382 slow_normal

XNOR2XLTH 3 16.934 slow_highvt



89


XOR2X1 154 869.299 slow_normal





XOR2XL 7 39.514 slow_normal

XOR2XLTH 4 22.579 slow_highvt

---------------------------------------------------

total 3866 21419.899

Library Instances Instances %

----------------------------------

slow_highvt 27 0.7

slow_normal 3839 99.3

Type Instances Area Area %

--------------------------------------

sequential 234 4554.648 21.3

inverter 456 1028.059 4.8

buffer 52 163.699 0.8

logic 3124 15673.493 73.2

--------------------------------------

total 3866 21419.899 100.0

Timing report

============================================================



Module: filter_new


slow_highvt 1.0




============================================================

Pin Type Fanout Load Slew Delay

Arrival

(fF) (ps) (ps)

(ps)

--------------------------------------------------------------------

--------

(clock clk) launch

0 R

delay_pipeline_reg[5][6]/CK 100

0 R

delay_pipeline_reg[5][6]/Q DFFRHQX4 4 8.6 45 +151

151 F

m6/a[6]

mul_23_19/A[6]

g1447/A +0

151

g1447/Y INVX4 5 12.7 55 +45

196 R



90

g1373/B +0

196

g1373/Y NAND2X4 5 10.2 55 +52

248 F

g1468/A +0

248

g1468/Y XOR2X3 2 5.7 86 +82

329 F

g1304/A1N +0

329

g1304/Y OAI2BB1X4 2 6.1 50 +97

426 F

g1296/A +0

426

g1296/Y INVX4 2 10.1 47 +42

468 R

g1289/A +0

468

g1289/Y NAND2X5 2 9.8 47 +42

510 F

g1281/C +0

510

g1281/Y NAND3X4 1 4.6 49 +44

554 R

g1277/B +0

554

g1277/Y NAND3X4 3 5.0 60 +56

610 F

g1275/A1N +0

610

g1275/Y OAI2BB1X4 1 5.8 49 +89

699 F

g1269/A +0

699

g1269/Y XOR2X8 4 8.5 104 +64

764 F

mul_23_19/Z[11]

g202/A1N +0

764

g202/Y OAI2BB1X4 1 6.8 53 +103

867 F

g213/A +0

867

g213/Y CLKINVX8 5 16.0 41 +38

905 R

m6/c[9]

s5/a[2]

g12119/A +0

905

g12119/Y CLKINVX6 2 8.0 33 +34

939 F

g12016/A +0

939

g12016/Y NAND2X4 4 12.4 66 +46

985 R

g11988/C +0

985

g11988/Y AND3X4 1 8.6 54 +104

1088 R



91

g11978/A +0

1088

g11978/Y NAND3X8 3 11.7 67 +51

1140 F

g11969/B +0

1140

g11969/Y AND3X6 2 6.3 34 +91

1231 F

g11968/A +0

1231

g11968/Y INVX2 1 4.4 43 +35

1266 R

g11952/A0 +0

1266

g11952/Y OAI211X4 3 6.0 83 +68

1334 F

s5/c[5]

s6/b[5]

g10651/A0 +0

1334

g10651/Y AOI21X2 2 3.8 102 +89

1423 R

g10720/A +0

1423

g10720/Y CLKINVX1 1 1.0 41 +45

1468 F

g10623/A0N +0

1468

g10623/Y OAI2BB1X2 2 4.1 62 +109

1577 F

g10618/A +0

1577

g10618/Y NAND2X2 1 2.3 39 +38

1614 R

g10611/A0 +0

1614

g10611/Y AOI21X2 1 2.3 50 +41

1656 F

g10607/A0 +0

1656

g10607/Y OAI21X2 1 2.0 84 +67

1722 R

g10599/B +0

1722

g10599/Y CLKNAND2X2 2 4.7 74 +69

1791 F

s6/c[7]

s7/b[7]

g18801/A +0

1791

g18801/Y NAND2X2 2 2.4 61 +41

1832 R

g18774/A +0

1832

g18774/Y AND2X2 2 5.7 61 +92

1925 R

g18751/A +0

1925

g18751/Y NAND3X4 2 6.0 66 +55

1979 F



92

g18890/A +0

1979

g18890/Y INVX4 2 8.5 44 +42

2022 R

g18930/A +0

2022

g18930/Y NAND3X6 8 11.1 74 +56

2078 F

g18703/A1N +0

2078

g18703/Y OAI2BB1X2 2 4.7 66 +112

2190 F

s7/c[2]

s8/b[2]

g17989/A +0

2190

g17989/Y NAND2X2 3 6.4 68 +55

2245 R

g17977/B +0

2245

g17977/Y NAND2X2 2 4.2 53 +52

2296 F

g17976/A +0

2296

g17976/Y CLKINVX2 1 2.3 31 +31

2327 R

g17964/A +0

2327

g17964/Y NAND2X2 1 1.7 37 +30

2357 F

g17942/B0 +0

2357

g17942/Y AOI21X1 1 2.4 90 +63

2420 R

g17940/A +0

2420

g17940/Y NOR2X2 1 4.2 39 +40

2459 F

g17930/B +0

2459

g17930/Y CLKNAND2X4 1 7.1 44 +38

2497 R

g17922/A +0

2497

g17922/Y NAND3X6 9 12.4 78 +59

2556 F

g17911/A0N +0

2556

g17911/Y OAI2BB1X4 4 7.5 55 +106

2662 F

s8/c[8]

s9/b[8]

g20040/A +0

2662

g20040/Y CLKAND2X4 2 4.6 40 +79

2741 F

g20146/A0N +0

2741

g20146/Y AOI2BB1X4 1 4.3 49 +94

2835 F



93

g19963/A +0

2835

g19963/Y NAND3X4 1 4.9 49 +38

2874 R

g19945/C +0

2874

g19945/Y NAND3X4 3 5.9 65 +63

2936 F

g20137/A +0

2936

g20137/Y XOR2X4 1 11.7 161 +82

3019 R

g19935/B +0

3019

g19935/Y CLKNAND2X12 9 29.5 85 +85

3104 F

g19931/B0 +0

3104

g19931/Y OAI2BB1X2 2 6.2 69 +64

3168 R

s9/c[0]

s10/b[0]

g19427/A +0

3168

g19427/Y NAND2X4 3 5.1 61 +40

3208 F

g19361/A0 +0

3208

g19361/Y OAI21X1 2 2.5 97 +74

3282 R

g19358/A1N +0

3282

g19358/Y OAI2BB1X4 3 8.8 58 +97

3379 R

g19440/A +0

3379

g19440/Y INVX4 2 8.5 29 +30

3410 F

g19347/A0 +0

3410

g19347/Y OAI21X6 1 3.3 71 +54

3464 R

g19338/A +0

3464

g19338/Y XOR2X4 1 1.3 63 +71

3535 F

g19328/A1N +0

3535

g19328/Y OAI2BB1X4 2 8.4 58 +96

3631 F

s10/c[5]

s11/b[5]

g16275/A +0

3631

g16275/Y INVX4 1 8.8 44 +41

3672 R

g16272/A +0

3672

g16272/Y NAND2X8 6 13.3 45 +37

3709 F



94

g16269/A +0

3709

g16269/Y CLKINVX2 1 2.4 29 +29

3738 R

g16215/A +0

3738

g16215/Y NOR2X2 1 4.0 43 +25

3763 F

g16190/A2 +0

3763

g16190/Y AOI31X4 1 3.7 89 +86

3850 R

g16188/B0 +0

3850

g16188/Y OAI2BB1X4 2 6.9 53 +51

3901 F

g16176/A +0

3901

g16176/Y OR2X6 9 12.7 42 +86

3987 F

g16165/A1N +0

3987

g16165/Y OAI2BB1X4 1 3.3 41 +78

4066 F

s11/c[3]

s12/b[3]

g18727/A +0

4066

g18727/Y INVX3 2 6.5 42 +37

4102 R

g18752/B +0

4102

g18752/Y NAND2BX4 4 9.2 61 +48

4151 F

g18702/A +0

4151

g18702/Y INVX2 2 4.7 47 +44

4194 R

g18667/A +0

4194

g18667/Y NOR2X2 1 1.3 30 +23

4217 F

g18640/A1N +0

4217

g18640/Y OAI2BB1X4 3 3.9 43 +77

4294 F

g18628/A1N +0

4294

g18628/Y OAI2BB1X2 1 3.0 55 +95

4389 F

g18618/A +0

4389

g18618/Y XNOR2X4 1 3.4 110 +61

4450 R

g18606/A +0

4450

g18606/Y NAND2X3 1 4.4 53 +50

4500 F

g18601/A +0

4500



95

g18601/Y NAND2X4 3 8.9 58 +44

4544 R

s12/c[8]

s13/b[8]

g16117/A +0

4544

g16117/Y NOR2X4 2 3.7 59 +25

4569 F

g16098/A +0

4569

g16098/Y NOR2X2 1 2.3 66 +54

4624 R

g16082/A +0

4624

g16082/Y NAND2X2 1 4.6 56 +51

4674 F

g16071/B +0

4674

g16071/Y NOR2X4 1 4.1 62 +59

4733 R

g16062/A1 +0

4733

g16062/Y AOI21X4 2 5.7 51 +50

4783 F

g16176/A +0

4783

g16176/Y INVX2 2 8.0 67 +53

4836 R

g16051/A +0

4836

g16051/Y NAND2X6 8 18.4 75 +56

4893 F

g16044/B0 +0

4893

g16044/Y OAI21X2 2 3.6 108 +48

4941 R

s13/c[0]

s14/b[0]

g20460/A +0

4941

g20460/Y AND2X4 2 3.3 34 +78

5018 R

g20367/A0N +0

5018

g20367/Y OAI2BB1X4 3 4.8 44 +77

5095 R

g20358/A1N +0

5095

g20358/Y OAI2BB1X4 3 7.6 54 +83

5178 R

g20349/AN +0

5178

g20349/Y NOR2BX4 1 2.3 51 +70

5248 R

g20348/A +0

5248

g20348/Y INVX2 2 6.7 37 +37

5285 F

g20496/A +0

5285



96

g20496/Y NAND2X4 1 9.0 54 +40

5325 R

g20463/B +0

5325

g20463/Y NAND2BX8 9 24.1 69 +56

5382 F

g20320/A +0

5382

g20320/Y CLKNAND2X2 2 4.1 61 +46

5427 R

s14/c[0]

s15/b[0]

g22045/A +0

5427

g22045/Y NAND2X2 3 7.0 85 +60

5487 F

g21995/A0 +0

5487

g21995/Y OAI21X4 3 8.1 124 +97

5584 R

g21988/A0N +0

5584

g21988/Y OAI2BB1X4 3 4.2 43 +93

5677 R

g21978/B +0

5677

g21978/Y XOR2X1 1 1.0 64 +85

5762 F

g21959/A0N +0

5762

g21959/Y OAI2BB1X2 2 4.7 66 +118

5880 F

s15/c[4]

s16/b[4]

g27408/A +0

5880

g27408/Y NOR2X2 3 5.1 104 +78

5957 R

g27407/A +0

5957

g27407/Y CLKINVX2 2 6.3 70 +70

6027 F

g27357/B +0

6027

g27357/Y NAND2X4 2 6.0 46 +47

6074 R

g27338/A +0

6074

g27338/Y NOR2X4 1 4.6 25 +24

6098 F

g27310/B +0

6098

g27310/Y NAND2X4 1 4.4 37 +31

6130 R

g27306/A +0

6130

g27306/Y NAND2X4 3 9.0 51 +41

6171 F

g27305/A +0

6171



97

g27305/Y INVX4 2 4.8 30 +31

6202 R

g27293/A1N +0

6202

g27293/Y OAI2BB1X4 1 2.3 35 +67

6269 R

g27284/A +0

6269

g27284/Y NAND2X2 1 4.4 53 +43

6312 F

g27283/A +0

6312

g27283/Y NAND2X4 2 8.4 54 +43

6355 R

s16/c[6]

s17/b[6]

g25666/A +0

6355

g25666/Y NOR2X4 3 7.9 70 +30

6385 F

g25661/A +0

6385

g25661/Y INVX4 3 8.9 46 +44

6430 R

g25605/A +0

6430

g25605/Y NAND3X4 2 2.8 49 +42

6471 F

g25592/A0N +0

6471

g25592/Y OAI2BB1X4 1 9.0 60 +102

6573 F

g25582/B +0

6573

g25582/Y NAND2X8 4 19.1 58 +52

6624 R

g25581/A +0

6624

g25581/Y CLKINVX12 1 8.8 27 +31

6655 F

g25573/A +0

6655

g25573/Y NAND2X8 8 17.7 55 +38

6693 R

g25565/A1N +0

6693

g25565/Y OAI2BB1X4 2 6.7 58 +83

6776 R

s17/c[2]

s18/b[2]

g28276/A +0

6776

g28276/Y NOR2X4 2 3.9 48 +25

6802 F

g28223/C +0

6802

g28223/Y NOR3X1 1 1.3 103 +94

6895 R

g28205/A1N +0

6895



98

g28205/Y OAI2BB1X4 4 7.5 54 +96

6991 R

g28191/A1N +0

6991

g28191/Y OAI2BB1X4 1 2.3 40 +72

7063 R

g28182/A +0

7063

g28182/Y XNOR2X2 1 2.3 76 +72

7135 F

g28173/A +0

7135

g28173/Y NAND2X2 1 4.4 53 +50

7185 R

g28170/A +0

7185

g28170/Y NAND2X4 3 9.1 52 +45

7230 F

s18/c[5]

s19/b[5]

g16522/A +0

7230

g16522/Y NOR2X2 1 2.4 67 +53

7283 R

g16496/A +0

7283

g16496/Y NAND3X2 2 3.6 79 +65

7348 F

g16484/A0 +0

7348

g16484/Y AOI31X2 1 4.6 123 +98

7446 R

g16470/B +0

7446

g16470/Y NAND2X4 2 7.1 53 +58

7503 F

g16468/B0 +0

7503

g16468/Y OAI2BB1X4 2 8.8 58 +48

7551 R

g16459/A +0

7551

g16459/Y NAND2X4 9 14.0 69 +56

7607 F

g16453/A1N +0

7607

g16453/Y OAI2BB1X2 2 5.1 69 +113

7720 F

s19/c[3]

s20/b[3]

g18660/A +0

7720

g18660/Y OR2X4 5 12.5 48 +91

7811 F

g18557/B +0

7811

g18557/Y NAND2X2 2 3.7 48 +43

7854 R

g18672/A1N +0

7854



99

g18672/Y AOI2BB1X4 1 4.9 71 +87

7941 R

g18506/C +0

7941

g18506/Y NAND3X4 3 8.2 78 +74

8015 F

g18497/A +0

8015

g18497/Y CLKNAND2X2 1 2.3 40 +40

8055 R

g18494/A +0

8055

g18494/Y NAND2X2 1 3.3 45 +39

8094 F

g18486/A +0

8094

g18486/Y XOR2X4 1 4.4 124 +59

8153 R

g18477/A +0

8153

g18477/Y NAND2X4 1 4.4 51 +46

8199 F

g18476/A +0

8199

g18476/Y NAND2X4 1 4.4 39 +35

8234 R

s20/c[7]

s21/b[7]

g18185/A +0

8234

g18185/Y INVX4 3 6.9 23 +24

8258 F

g18140/A +0

8258

g18140/Y NAND2X3 3 5.7 52 +34

8293 R

g18101/A +0

8293

g18101/Y NAND2X2 2 3.7 49 +44

8336 F

g18094/A +0

8336

g18094/Y NOR2X2 1 2.4 67 +52

8389 R

g18086/A +0

8389

g18086/Y NAND3X2 1 2.3 66 +57

8446 F

g18083/A +0

8446

g18083/Y NAND2X2 2 4.8 56 +49

8494 R

g18082/A +0

8494

g18082/Y BUFX4 2 10.4 52 +72

8567 R

g18073/A +0

8567

g18073/Y NAND2X8 9 28.1 83 +54

8621 F



100

g18065/B0 +0

8621

g18065/Y OAI2BB1X4 2 6.7 51 +52

8673 R

s21/c[1]

s22/b[1]

g29097/A +0

8673

g29097/Y INVX4 2 4.6 22 +24

8697 F

g29091/A +0

8697

g29091/Y NAND2X2 2 3.2 46 +31

8728 R

g29119/AN +0

8728

g29119/Y NOR2BX4 1 3.7 62 +74

8802 R

g29017/B0 +0

8802

g29017/Y OAI2BB1X4 2 6.7 52 +46

8848 F

g29008/A +0

8848

g29008/Y NAND2X4 2 9.2 54 +45

8892 R

g29003/B +0

8892

g29003/Y NAND2X4 2 5.9 39 +43

8935 F

g28989/A +0

8935

g28989/Y NAND3X4 1 7.7 63 +42

8976 R

g28986/A +0

8976

g28986/Y CLKNAND2X8 9 31.4 108 +76

9052 F

g28976/B0 +0

9052

g28976/Y OAI2BB1X4 2 4.7 52 +53

9105 R

s22/c[3]

s23/b[3]

g22541/A +0

9105

g22541/Y NAND2X2 3 5.7 72 +52

9157 F

g22496/B +0

9157

g22496/Y NAND2X2 1 2.4 43 +45

9202 R

g22484/A +0

9202

g22484/Y NAND3X2 1 2.3 64 +52

9253 F

g22473/B +0

9253

g22473/Y NOR2X2 1 2.3 67 +62

9315 R



101

g22463/B +0

9315

g22463/Y NAND2X2 1 4.3 53 +52

9367 F

g22461/A +0

9367

g22461/Y NAND3X4 2 5.7 52 +41

9408 R

g22460/A +0

9408

g22460/Y BUFX6 2 10.4 40 +62

9470 R

g22454/A +0

9470

g22454/Y NAND2X8 9 31.9 89 +56

9526 F

g22446/B0 +0

9526

g22446/Y OAI2BB1X4 2 6.7 52 +53

9580 R

s23/c[2]

s24/b[2]

g11877/A +0

9580

g11877/Y NAND2X2 2 3.7 67 +44

9623 F

g11854/B +0

9623

g11854/Y AND2X4 2 7.4 37 +88

9711 F

g11853/A +0

9711

g11853/Y CLKINVX3 2 5.6 36 +32

9743 R

g11838/A +0

9743

g11838/Y CLKNAND2X2 1 3.7 62 +50

9793 F

g11825/B0 +0

9793

g11825/Y OAI2BB1X4 3 5.4 46 +44

9836 R

g11810/A1N +0

9836

g11810/Y OAI2BB1X4 1 3.0 40 +72

9908 R

g11804/A +0

9908

g11804/Y XNOR2X4 1 4.4 138 +59

9967 R

g11796/A +0

9967

g11796/Y NAND2X4 1 4.4 54 +48

10016 F

g11792/A +0

10016

g11792/Y NAND2X4 2 4.1 42 +35

10050 R

s24/c[5]

s25/b[5]



102

g8238/A1N +0

10050

g8238/Y OAI2BB1X4 3 8.3 62 +84

10134 R

g8223/A +0

10134

g8223/Y NAND3X4 1 2.4 47 +44

10178 F

g8218/A +0

10178

g8218/Y NOR2X2 1 1.7 58 +47

10225 R

g8203/A0N +0

10225

g8203/Y OAI2BB1X4 2 5.7 47 +84

10309 R

g8194/A1N +0

10309

g8194/Y OAI2BB1X4 2 10.4 63 +90

10398 R

g8187/A +0

10398

g8187/Y NAND2X8 9 20.3 55 +49

10448 F

g8183/B0 +0

10448

g8183/Y OAI2BB1X2 2 6.7 72 +57

10505 R

s25/c[1]

s26/b[1]

g14723/A +0

10505

g14723/Y NAND2X2 3 5.4 76 +56

10560 F

g14674/A1N +0

10560

g14674/Y OAI2BB1X2 2 6.1 76 +119

10680 F

g14667/A +0

10680

g14667/Y NAND2X4 2 9.2 55 +51

10731 R

g14663/B +0

10731

g14663/Y NAND3X4 2 5.9 68 +60

10791 F

g14660/A +0

10791

g14660/Y NAND3X4 1 8.8 71 +52

10843 R

g14655/A +0

10843

g14655/Y NAND2X8 9 21.5 75 +52

10895 F

g14651/B0N +0

10895

g14651/Y AOI21BX4 1 5.7 34 +85

10980 F

g14631/B +0

10980



103

g14631/Y NAND2X5 4 10.6 55 +43

11024 R

s26/c[7]

s27/b[7]

g25628/A +0

11024

g25628/Y NAND2X2 2 6.7 82 +57

11081 F

g25604/A +0

11081

g25604/Y NAND2X4 2 5.6 44 +45

11126 R

g25603/A +0

11126

g25603/Y INVX3 1 3.7 21 +24

11150 F

g25579/B +0

11150

g25579/Y AND3X6 3 13.2 43 +87

11237 F

g25567/B +0

11237

g25567/Y NAND2X3 1 4.4 44 +41

11277 R

g25562/A +0

11277

g25562/Y NAND2X4 9 16.6 83 +59

11336 F

g25542/B +0

11336

g25542/Y NAND2X1 1 1.4 42 +43

11380 R

s27/c[6]

filter_out_reg[6]/D SDFFQXL +0

11380

filter_out_reg[6]/CK setup 100 +120

11500 R

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - -

(clock clk) capture

12000 R

uncertainty -500

11500 R

--------------------------------------------------------------------

--------

Cost Group : 'clk' (path_group 'clk')

Timing slack : 0ps

Start-point : delay_pipeline_reg[5][6]/CK

End-point : filter_out_reg[6]/D

FORM I TRANSPOSED FIR FILTER

Constraint file

create_clock -name clk -period 12 -waveform {0 6} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]

set_clock_transition -fall 0.1 [get_clocks "clk"]



104

set_clock_uncertainty 0.5 [get_ports "clk"]

set_input_delay -max 1.0 [get_ports "clk_enable"] -clock [get_clocks "clk"]

set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"]

set_input_delay -max 1.0 [get_ports "filter_in"] -clock [get_clocks "clk"]

set_output_delay -max 1.5 [get_ports "filter_out"] -clock [get_clocks "clk"]

Synthesis RC script

# *************************************************

# * Local Variable settings for this design

# *************************************************

include load_etc.tcl

set LOCAL_DIR "[exec pwd]"

set SYNTH_DIR $LOCAL_DIR/work

set RTL_DIR $LOCAL_DIR/rtl

set LIB_DIR $LOCAL_DIR/library

set TCL_DIR $LOCAL_DIR/tcl

set OUT_DIR $LOCAL_DIR/outputs

set LOG_DIR $LOCAL_DIR/logs

set RPT_DIR $LOCAL_DIR/reports

set LIBRARY {slow_normal.lib slow_highvt.lib}

set FILE_LIST {filter_trans.v mul.v sum.v}

set WL_MODEL "tsmc18_wl10"

set WL_MODE enclosed

set SYN_EFFORT medium

set MAP_EFFORT medium

set DESIGN filter_trans

# *********************************************************

# * Set all the search paths & Create output directories

# *********************************************************

set_attr hdl_search_path ${RTL_DIR} /

set_attr lib_search_path ${LIB_DIR} /

set_attr script_search_path ${TCL_DIR} /

if {![file exists ${LOG_DIR}]} {

file mkdir ${LOG_DIR}

puts "Creating directory ${LOG_DIR}" }

if {![file exists ${OUT_DIR}]} {

file mkdir ${OUT_DIR}

puts "Creating directory ${OUT_DIR}" }

if {![file exists ${RPT_DIR}]} {

file mkdir ${RPT_DIR}

puts "Creating directory ${RPT_DIR}" }

# *********************************************************

# *** SETUP LIBRARY and WIRELOADS *************************

# *********************************************************

set_attribute wireload_mode $WL_MODE /



105

set_attribute information_level 7 /

set_attribute library $LIBRARY

set THE_DATE [exec date +%m%d.%H%M]

# THESE SETTINGS ARE FOR DIAGNOSTIC PURPOSES AND STRONGLY

RECOMMENDED

# *********************************************************

# * Define Tool Setup and Compatibility

# *********************************************************

#set_attr hdl_max_loop_limit 1024 /

#set_attr hdl_array_naming_style %s_reg\[%d\] /

#set_attr gen_module_prefix G2C_DP_ /

# *********************************************************

# * Define Tool Diagnostic Level

# *********************************************************

set_attr information_level 9 /

#set global_map_report 1

#set map_fancy_names 1

#set iopt_stats 1

set_attr map_timing 1 /

#set_attr hdl_track_filename_row_col true /

####################################################################

## Load Design

####################################################################

read_hdl -v2001 $FILE_LIST

elaborate $DESIGN

check_design $DESIGN -unresolved

####################################################################

## Constraints Setup

####################################################################

read_sdc ./syn/constraints.g

#######################################################################

Synthesizing to generic

#####################################################################

synthesize -to_generic -eff $SYN_EFFORT

report datapath > $RPT_DIR/${DESIGN}_datapath_generic.rpt

#####################################################################

## Synthesizing to gates

#####################################################################

synthesize -to_mapped -eff $MAP_EFFORT -no_incr

report datapath > $RPT_DIR/${DESIGN}_datapath_map.rpt

#foreach cg [find / -cost_group *] {


$cg]_post_map.rpt

#}



106

##Intermediate netlist for LEC verification..

#write_hdl -lec > ${OUT_DIR}/${DESIGN}_intermediate.v

#write_do_lec -revised_design ${OUT_DIR}/${DESIGN}_intermediate.v -logfile

${_LOG_PATH}/#rtl2intermediate.lec.log > ${OUT_DIR}/rtl2intermediate.lec.do

#####################################################################

## Incremental Synthesis

#####################################################################

## Uncomment to remove assigns & insert tiehilo cells during Incremental synthesis

##set_attribute remove_assigns true /

##set_remove_assign_options -buffer_or_inverter <libcell> -design <design|subdesign>

##set_attribute use_tiehilo_for_const <none|duplicate|unique> /

synthesize -to_mapped -eff $MAP_EFFORT -incr

#foreach cg [find / -cost_group -null_ok *] {


$cg]_post_incr.rpt

#}

#####################################################################

## Write Output file set (verilog, SDC, config, etc.)

#####################################################################

#write_encounter design -basename <path & base filename> -lef <lef_file(s)>

report area > $RPT_DIR/${DESIGN}_area.rpt

report timing > $RPT_DIR/${DESIGN}_timing.rpt

report gates > $RPT_DIR/${DESIGN}_gates.rpt

write_design -basename ${OUT_DIR}/${DESIGN}_m

write_hdl > ${OUT_DIR}/${DESIGN}.vg

write_script > ${OUT_DIR}/${DESIGN}_m.script

write_sdc > ${OUT_DIR}/${DESIGN}_m.sdc

#################################

### write_do_lec

#################################

#write_do_lec -golden_design ${OUT_DIR}/${DESIGN}_intermediate.v -

revised_design #${OUT_DIR}/${DESIGN}_m.v -logfile

${_LOG_PATH}/intermediate2final.lec.log > #${OUT_DIR}/intermediate2final.lec.do

##Uncomment if the RTL is to be compared with the final netlist..

##write_do_lec -revised_design ${OUT_DIR}/${DESIGN}_m.v -logfile

${_LOG_PATH}/#rtl2final.lec.log > ${OUT_DIR}/rtl2final.lec.do

puts "============================"

puts "Synthesis Finished ........."

puts "============================"

#file copy [get_attr stdout_log /] ${_LOG_PATH}/.

##quit



107

# *********************************************************

# * ATTRIBUTE Settings to Support Synopsys Pragmas

# *********************************************************

#set_attribute input_pragma_keyword synopsys /

#set_attribute synthesis_off_command translate_off /

#set_attribute synthesis_on_command translate_on /

#set_attribute input_case_cover_pragma {full_case} /

#set_attribute input_case_decode_pragma {parallel_case} /

#set_attr input_synchro_reset_pragma sync_set_reset /

#set_attr input_synchro_reset_blk_pragma sync_set_reset_local /

#set_attr input_asynchro_reset_pragma async_set_reset /

#set_attr input_asynchro_reset_blk_pragma async_set_reset_local /

# *********************************************************

# * Set maximum print of messages

# *********************************************************







# *********************************************************

# * Other common optimization directives

# *********************************************************

# You can have this attribute true almost always.

# set_attr endpoint_slack_opto true /

# Turn this medium or high if you have Multi-VT libraries.

# set_attr lp_multi_vt_optimization_effort medium /

# Turn this on always to optimize logic to reset arcs.

# set_attr time_recovery_arcs true /

Gate Area report

============================================================



Module: filter_trans


slow_highvt 1.0




============================================================



108

Gate Instances Area Library

------------------------------------------------

ADDFX1 225 3969.000 slow_normal

ADDFXL 9 158.760 slow_normal


ADDHXL 3 31.752 slow_normal










AOI2B1X1 1 4.939 slow_normal


AOI2BB1XL 1 4.234 slow_normal











INVXL 4 8.467 slow_normal

MXI2X1 3 16.934 slow_normal

MXI2XL 1 5.645 slow_normal





NAND3XL 1 3.528 slow_normal


NOR2BXL 1 3.528 slow_normal




NOR3XL 1 3.528 slow_normal



OA21XL 4 19.757 slow_normal









OAI2BB1XL 207 876.355 slow_normal









109

SDFFQX1 10 176.400 slow_normal






------------------------------------------------

total 1609 14550.883

Type Instances Area Area %

--------------------------------------

sequential 308 6068.160 41.7

inverter 99 209.563 1.4

buffer 5 20.462 0.1

logic 1197 8252.698 56.7

--------------------------------------

total 1609 14550.883 100.0

Timing report

============================================================



Module: filter_trans


slow_highvt 1.0




============================================================

Pin Type Fanout Load Slew Delay

Arrival

(fF) (ps) (ps)

(ps)

--------------------------------------------------------------------

---------

(clock clk) launch

0 R

inputreg_reg[5]/CK 100

0 R

inputreg_reg[5]/Q SDFFRQX2 2 2.6 54 +268

268 F

g773/A +0

268

g773/Y CLKBUFX3 63 118.8 674 +431

699 F

m10/a[5]

mul_15_19/A[5]

g803/A +0

699

g803/Y INVX2 4 7.5 175 +144

844 R

g790/A0 +0

844



110

g790/Y AOI22XL 2 4.3 260 +122

966 F

g768/CI +0

966

g768/S ADDFX1 2 4.0 83 +226

1192 R

g762/A0 +0

1192

g762/Y AOI21X1 1 1.6 72 +67

1259 F

g760/B0 +0

1259

g760/Y OAI2B2X1 1 1.2 115 +75

1334 R

g759/B0 +0

1334

g759/Y AOI32XL 1 1.6 171 +74

1408 F

g758/B0 +0

1408

g758/Y AOI2B1X1 2 4.0 127 +110

1518 R

g756/A0 +0

1518

g756/Y AOI21X1 1 1.6 75 +78

1596 F

g755/B0 +0

1596

g755/Y OAI2BB2X1 1 1.6 86 +70

1666 R

g754/B0 +0

1666

g754/Y OAI21X1 1 2.5 78 +73

1740 F

g753/CI +0

1740

g753/CO ADDFX1 1 2.5 80 +178

1918 F

g752/CI +0

1918

g752/CO ADDFX1 1 2.5 79 +179

2096 F

g751/CI +0

2096

g751/CO ADDFX1 2 3.4 87 +186

2283 F

g750/A +0

2283

g750/Y XNOR2X1 2 3.9 186 +94

2376 R

mul_15_19/Z[13]

g126/B +0

2376

g126/Y NAND2BX2 2 3.0 64 +64

2440 F

g124/A +0

2440

g124/Y AND2X2 13 29.8 144 +159

2599 F



111

g123/B0N +0

2599

g123/Y OAI21BX1 2 4.8 130 +186

2785 F

m10/c[3]

s9/a[3]

g1089/A +0

2785

g1089/CO ADDFX1 1 2.5 78 +254

3039 F

g1088/CI +0

3039

g1088/CO ADDFX1 1 2.5 78 +178

3217 F

g1087/CI +0

3217

g1087/CO ADDFX1 1 2.5 78 +178

3396 F

g1086/CI +0

3396

g1086/CO ADDFX1 1 2.5 78 +178

3574 F

g1085/CI +0

3574

g1085/CO ADDFX1 1 2.5 78 +178

3752 F

g1084/CI +0

3752

g1084/CO ADDFXL 1 1.6 75 +169

3921 F

g1083/A +0

3921

g1083/Y INVX1 1 2.5 42 +42

3963 R

g1082/CI +0

3963

g1082/S ADDFX1 2 3.9 81 +161

4124 R

g1080/B +0

4124

g1080/Y NAND2X2 9 6.3 70 +64

4188 F

g1071/A1N +0

4188

g1071/Y OAI2BB1XL 1 0.8 59 +112

4300 F

s9/c[8]

delay_pipeline_reg[9][8]/SI SDFFRQX2 +0

4300

delay_pipeline_reg[9][8]/CK setup 100 +209

4509 R

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - -

(clock clk) capture

12000 R

uncertainty -500

11500 R

--------------------------------------------------------------------

---------

Cost Group : 'clk' (path_group 'clk')



112

Timing slack : 6991ps

Start-point : inputreg_reg[5]/CK

End-point : delay_pipeline_reg[9][8]/SI

32 tap fir filter using hann window-b7

Documents

respect of project work

karnataka project report

bachelor of engineering

bonafied work

understanding of work

1nh06ec022 prithviraj

degree of bachelor

guide project coordinator