3gb/s sdi demo board: xilinx version€¦ · 01/08/2009 · gs4911b lock/ref status u22, u23....
TRANSCRIPT
3Gb/s SDI Demo Board: Xilinx Version
User Guide
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3Gb/s SDI Demo Board: Xilinx VersionUser Guide52857 - 1 August 2009
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Contents
1. Overview..........................................................................................................................................................4
1.1 Features ...............................................................................................................................................4
1.2 Featured Devices ..............................................................................................................................4
2. Hardware .........................................................................................................................................................5
2.1 Gennum 3Gb/s SDI Demo Board .................................................................................................5
2.2 Xilinx Spartan-3A DSP 1800 Board ............................................................................................9
3. Detailed Description.................................................................................................................................. 10
3.1 Switches and Settings ................................................................................................................... 10
3.1.1 Power Switch (SW1).......................................................................................................... 10
3.1.2 Operating Modes (SW3 Bits 1-3)................................................................................... 10
3.2 Jumpers ............................................................................................................................................. 11
3.2.1 Video Source Selection (J13, J14).................................................................................. 11
3.2.2 FPGA PROG_B (JP7) .......................................................................................................... 11
3.2.3 Optical Module Enable (JP4) .......................................................................................... 11
3.3 LED Indicators ................................................................................................................................ 12
3.3.1 Power LED (D1) .................................................................................................................. 12
3.3.2 Lock Status LEDs (U4, U5, U13, U14, U22 and U23) ............................................... 12
3.3.3 Test Pattern Generator Status LEDs (D7-14) ............................................................. 12
3.3.4 FPGA Configure Done LED (D1) ................................................................................... 12
3.3.5 FPGA Reset LED (D6) ........................................................................................................ 13
3.4 Connectors ....................................................................................................................................... 13
3.4.1 Video Inputs A IN (J3, J4) and B IN (J6) ....................................................................... 13
3.4.2 AES Audio Inputs (J10, J11) ............................................................................................ 13
3.4.3 External Sync (J12) ............................................................................................................ 13
3.4.4 Optical Connector (U30).................................................................................................. 13
3.4.5 SDI Outputs (J8, J9) ............................................................................................................ 13
3.4.6 SDI Loop-Through (J5)...................................................................................................... 13
3.4.7 Audio Outputs (J1, J2)....................................................................................................... 14
3.4.8 GSPI Header (J7)................................................................................................................. 14
3.4.9 EXP Connector (JX1) ......................................................................................................... 14
3.5 Push Buttons .................................................................................................................................... 17
3.5.1 Reset (SW4) .......................................................................................................................... 17
3.5.2 Test Pattern (SW7 & SW8) ............................................................................................... 17
3.5.3 Test Pattern Video Standard (SW5, SW6) .................................................................. 18
3.5.4 SPI PROM Programming (J10)........................................................................................ 19
Version ECR Date Changes and / or Modifications
1 152458 August 2009 Updates to Figure 2-1 and Figure 2-2. Additional information added for enabling
the Optical Module.
0 152134 June 2009 New document.
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3.5.5 JTAG Programming (J2).................................................................................................... 19
4. Getting Started............................................................................................................................................. 20
4.1 Quick Start Guide .......................................................................................................................... 20
4.2 FPGA Configuration ..................................................................................................................... 22
4.2.1 JTAG Direct.......................................................................................................................... 22
4.2.2 SPI PROM.............................................................................................................................. 22
5. Advanced User Guide ............................................................................................................................... 22
5.1 Top Level Architecture ................................................................................................................ 22
5.2 Clock Tree and Data Path ............................................................................................................ 23
5.3 Pattern Generator .......................................................................................................................... 24
5.3.1 Top Level Architecture .................................................................................................... 25
5.3.2 Reset Network .................................................................................................................... 25
5.3.3 Clock Generator ................................................................................................................. 27
5.3.4 Colour Bar Generator ....................................................................................................... 27
5.3.5 20b to 10b Mux................................................................................................................... 28
5.4 Optical Module ............................................................................................................................... 29
5.5 Data Path .......................................................................................................................................... 31
5.6 I/O Timing Closure ........................................................................................................................ 31
5.7 Clock Termination ......................................................................................................................... 32
5.8 FPGA User Constraints ................................................................................................................ 33
5.8.1 Input Data Window Specification ............................................................................... 33
5.8.2 Internal Clock Constraints.............................................................................................. 33
5.8.3 MAXDELAY Constraints ................................................................................................. 33
5.8.4 Location Constraints......................................................................................................... 33
5.8.5 Non-Clock_Dedicated_Route........................................................................................ 34
5.8.6 Input Delay Adjustment.................................................................................................. 34
5.8.7 Output Timing Adjustment ............................................................................................ 34
5.9 Host Interface and Register Map .............................................................................................. 35
5.10 Suggestions .................................................................................................................................... 35
6. Related Documents.................................................................................................................................... 36
6.1 Gennum's Documentation .......................................................................................................... 36
6.2 Xilinx's Documentation ............................................................................................................... 36
7. Appendix....................................................................................................................................................... 37
7.1 Schematics ....................................................................................................................................... 37
7.2 Board Layout ................................................................................................................................... 48
7.3 Bill of Materials ............................................................................................................................... 50
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1. Overview
The 3Gb/s SDI Demo Board is designed to demonstrate the functionality, flexibility and implementation simplicity of Gennum’s 3G/HD/SD SDI devices. The Demo Kit consists of a 3Gb/s SDI Demo Board, FPGA source code and PC software. Paired with an additional Xilinx Spartan-3A DSP 1800A Board, it makes a versatile demo/evaluation platform for Gennum's 3Gb/s products. It is expected to help the users in system design with Gennum 3Gb/s devices.
The purpose of this document is to describe the functionalities and contents of Gennum's 3Gb/s SDI Demo Board for the Xilinx Spartan-3A DSP 1800A Board. Also included are a Quick Start Guide and an Advanced User Guide. If a quick start is anticipated, Please go to 4.1 Quick Start Guide.
The Schematics, Board Layout and the Bill of Materials are given in the Appendix section at the end of this document.
1.1 Features• Three 3G-SDI inputs with associated GS2974B Equalizers;
• Two Gennum GS2970 Receivers
• One 3G-SDI loop-through output
• Two Gennum GS2970 Transmitters
• External Sync input followed by a Gennum GS4911B Clock and Timing Generator
• Provision for a Gennum GO2921 Optical Transceiver (not supplied with the board)
• HSMC Connector Interface to Xilinx FPGA Board
• Two AES inputs for audio embedding
• Two AES outputs for audio de-embedding
• A standard Gennum SPI header
• Status indication LEDs and control jumpers
• Pass-through Mode
• Dual-Link to 3Gb/s conversion
• 3Gb/s to Dual-Link conversion
• Stand alone Video Test Pattern Generator (Both Genlock or Free-run)
• Audio embedding and de-embedding
• GSPI Daisy Chain
1.2 Featured DevicesGS2970 SD/HD/3G SDI Receiver complete with SMPTE Audio and Video Processing
GS2972 SD/HD/3G SDI Transmitter complete with SMPTE Audio and Video Processing
GS2974B Adaptive Cable Equalizer
GS2978 Multi-rate Dual Slew Rate Cable Driver
GS4911B HD/SD/Graphics Clock and Timing Generator with GENLOCK
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2. Hardware
When you receive the 3Gb/s SDI Demo Board, the kit includes:
• A 3Gb/s SDI Demo Board
• A Gennum Serial Peripheral Interface (GSPI) Dongle
Other items to be supplied by the customer:
• A Spartan-3A DSP 1800 Board
• A PC or laptop with ISE or iMPACT installed (optional)
• Xilinx Parallel Cable IV or Platform Cable USB II (optional)
2.1 Gennum 3Gb/s SDI Demo BoardFigure 2-1 shows the top side of the 3Gb/s SDI Demo Board:
Figure 2-1: Top Side of the 3Gb/s SDI Demo Board
AES Audio Output 1 (J1)
SDI Loop-through (J5)
SDI Input AIN1 (J3)
SDI Input AIN2 (J4)
SDI Inputs BIN1 (J6)
SDI Output AOUTn (J8)
SDI Outputs BOUTn (J9)
GSPI Header (J7)
Power StatusLED (D1)
Des Lock Status (U4, U5)
Ser Lock Status (U13, U14)
Source Selection (J13, J14)
AES Audio Input 1 (J10)
External Sync Input (J12)
Optical Transceiver Footprint (U30)
AES Audio Output 2 (J2)
AES Audio Input 2 (J11)
GS4911B Lock/RefStatus (U22, U23)
Optical Module Enable (JP4)
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Figure 2-2 show the bottom side of the 3Gb/s SDI Demo Board:
Figure 2-2: Bottom side of the 3Gb/s SDI Demo Board
NOTE: The board you receive may not look exactly the same as the board shown in Figure 2-1 and Figure 2-2 in terms of revision code, date code, etc.
Figure 2-3 shows the Gennum SPI Dongle Board:
Figure 2-3: Gennum SPI Dongle Board + Ribbon Cable
Parallel Connector (JX1)
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Figure 2-4 shows a block diagram of the features and signal flows of the 3G/s SDI Demo Board:
Figure 2-4: Block Diagram of the 3Gb/s SDI Demo Board
GS29703Gb/s, HD, SDSDI Receiver
Optical Transceiver Footprint
GS2972
GS2972
GS2974BEQ
PowerConditioning
SPIExtender
10
5
10
5
10
10
9
3
4
To Gennum parts
Data
STAT [0:4]
PCLK
Data
PCLK
PCLK
HVF
GSPI In
To pin control
GSPI
HVF 3
Data
PCLK
4Serial Audio
4Serial Audio
Data
AES Audio
AES Audio
SyncSeparatorGS4911B
Timing
PCLK
STAT [0:4]
A In
B In
A Out
B Out
Differential
Single-ended
Bus
A Loopback
EXT Sync.
GS2974BEQ
GS2974BEQ
GS2978CD
3Gb/s, HD, SDSDI Transmitter
3Gb/s, HD, SDSDI Transmitter
GS29703Gb/s, HD, SDSDI Receiver
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Table 2-1: 3Gb/s SDI Demo Board Legend
Description Label
SDI Input AIN1 J3
SDI Input AIN2 J4
SDI Input BIN1 J6
SDI Output AOUTn J8
SDI Output BOUTn J9
GSPI Header J7
AES Audio Input 1 J10
AES Audio Input 2 J11
Parallel Connector JX1
SDI Loop-through J5
AES Audio Output 1 J1
AES Audio Output 2 J2
Power Status LED D1
Receiver Lock Status Indicators U4, U5
Transmitter Lock Status Indicators U13, U14
Video Source Selection Jumpers J13, J14
External Sync Input J12
GS4911B Lock/Ref Status U22, U23
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2.2 Xilinx Spartan-3A DSP 1800 BoardFigure 2-5 shows the Xilinx Spartan-3A DSP 1800A Board. The switches, FPGA, connectors, jumpers, push buttons and LEDs used in this Demo Kit are highlighted in this figure:
Figure 2-5: Xilinx Spartan-3A DSP 1800A Board
HSMC (JX2)
Reset Button (SW4)
PWR (SW1)
5V DC In(J5)
OP Mode (SW3)
Reset LED (D6)
PG Std & Pattern (SW5, 6, 7 & 8)
SPI HDR (J10)
PROG_B (JP7)
JTAG (J2)
LEDs (D7-14)
FPGA (U6)
FPGA Config Done (D1)
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3. Detailed Description
This section describes the frequently used devices and their functions. For unused jumpers, switches, LEDs on the FPGA board, please refer to UG485 Getting Started with the Spartan-3A DSP S3D1800A Starter Platform User Guide.
3.1 Switches and Settings
3.1.1 Power Switch (SW1)
The PWR (SW1) on the Xilinx Spartan-3A DSP 1800A Board controls the power of the boards.
3.1.2 Operating Modes (SW3 Bits 1-3)
The current release of the FPGA code supports five distinct modes of operation: Pass-through, 3G Level B to Dual-Link, Dual-Link to 3G Level B, Test Pattern with Genlock and Test Pattern with Free-run modes. The operating mode can be set through a dip switch (SW3 bits 1-3), or by programming the FPGA’s internal registers through the SPI. Table 3-1 details how the operating mode is selected by the dip switches on the Xilinx Board:
Video Pass-Through mode: Received video from input A is passed to output A, and input B passed to output B without any process. All SD, HD and 3G formats are supported. For 3G, the default setting is Level A. If Level B is anticipated, the configuration for the GS2972 must be changed through the SPI.
3G Level B to Dual-Link mode (HD): 3G Level B video from input A is passed to outputs A and B as a two HD stream output.
Dual-Link (HD) to 3G Level B mode: Two HD signals, with the same standard, from inputs A and B are multiplexed onto a 10-bit stream and passed to output A. By default, the GS2972 is configured to output a 3G Level B video signal.
Table 3-1: Operation Modes set by SW3 on Xilinx Board
Dip Switch State Operation Mode Notes
SW3: Bits 1, 2, 3 OFF/OFF/OFF Video Pass-through All standards
OFF/OFF/ON 3G Level B to Dual-Link −
ON/OFF/OFF Dual-Link to 3G Level B YCbCr 422 10b. The monitor set to 1080i59.94
ON/ON/OFF Genlock Test Pattern Selected standards
ON/OFF/ON Free-run Test Pattern All standards and patterns
SW3: Bits 4 - 8 Not defined
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Stand-alone Video Test Pattern Generator - Free-Run Mode: The system generates a video test pattern signal using clock and timing from the GS4911B, with the GS4911B in free-run mode.
Stand-alone Video Test Pattern generator - Genlock Mode: Video test patterns are generated using clock and timing signals from the GS4911B, derived from an external Genlock source.
Other modes which may be implemented through a GS2970/72 configuration change are: 3G Level A to Dual-Link and Dual-Link to 3G Level A.
NOTE: the dip-switches on the Xilinx FPGA board are found to be unreliable after hundreds of times switching.
3.2 Jumpers
3.2.1 Video Source Selection (J13, J14)
Selection of the video input can be done from either the FPGA or from the jumper headers (J13 and J14) on the 3Gb/s SDI Demo Board.
When the jumpers are open (removed from the header), the FPGA takes over the control of the video input multiplexers. When the FPGA outputs ‘ones’, the jumper can override the settings.
Table 3-2 shows the selections available through jumpers J13 and J14:
3.2.2 FPGA PROG_B (JP7)
When the SPI PROM is programmed, the FPGA may be configured with Master Serial Mode. To do that, added a shunt on JP7 and program and SPI PROM using a Xilinx programming cable. Power-down the board and remove the shunt after programming. For more details, refer to Xilinx document xapp1053.pdf, “Flash Memory Boot Loading Using SPI with Spartan-3A DSP 1800A Starter Platform”.
3.2.3 Optical Module Enable (JP4)
Add a shunt on JP4 to enable the Optical Module.
Table 3-2: Video Source Selection by Jumpers on 3Gb/s SDI Demo Board
Jumper Video Path Jumper State Input Selected
J13 A Open AIN1
Closed AIN2
J14 B Open BIN1
Closed Optical
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3.3 LED Indicators
3.3.1 Power LED (D1)
D1 on the 3Gb/s SDI Demo Board indicates the power on/off state of the boards.
3.3.2 Lock Status LEDs (U4, U5, U13, U14, U22 and U23)
U4, U5, U13, U14, U22 and U23 on the 3Gb/s SDI Demo Board are bi-colour LEDs. They indicate the lock status of the Gennum Transmitter, Receiver and Clock/Timing devices.
3.3.3 Test Pattern Generator Status LEDs (D7-14)
LEDs D7-14 on the Xilinx Board indicate the type of the test pattern, the video standard, the clock lock status, 3G/HD, and configuration status.
3.3.4 FPGA Configure Done LED (D1)
D1 on the Xilinx Board indicates the FPGA configuration done status. When D1 (blue LED) is on, the FPGA configuration is completed from either the SPI PROM or JTAG.
Table 3-3: Lock Status
LED Function Green Red
U4 GS2970 A, U8 Lock Status Locked Unlocked
U5 GS2970 B, U11 Lock Status Locked Unlocked
U13 GS2972 A, U15 Lock Status Locked Unlocked
U14 GS2972 B, U16 Lock Status Locked Unlocked
U22 GS4911B, U19 Lock Status Locked Lock Lost
U23 GS4911B, U19 Ref Status Detected Lost
Table 3-4: LED D7-14 on the Xilinx Board
LED Description
D7, D8, D9, D10 Video Standard of the Test Pattern
D11 ON = Busy in configuration
D12 ON = Test Pattern Clock Locked
D13 Test Pattern Std: ON = 3G, OFF = HD
D14 ON = Tx/Rx/Genlock devices are configured
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3.3.5 FPGA Reset LED (D6)
D6 on the Xilinx Board indicates the FPGA reset status. When it is on, the FPGA is reset by the push button (SW4) or the power-on-reset circuit.
3.4 Connectors
3.4.1 Video Inputs A IN (J3, J4) and B IN (J6)
The 3Gb/s SDI Demo Board includes three SDI inputs. The applied SDI stream will first pass through Gennum's GS2974B Cable Equalizer before entering the Micrel SY58017U Mux. The output of the Mux is fed into the SDI input pins of the GS2970.
3.4.2 AES Audio Inputs (J10, J11)
Up to four channels of audio are supported by the Demo Board. Group One can be connected directly to the GS2972 as AES (J10, J11).
This configuration is meant to allow users to have the capability of evaluating audio embedding. For SD audio, when embedding audio with both groups, the audio needs to be synchronized externally.
3.4.3 External Sync (J12)
Gennum's GS4911B may be connected to the sync separator to provide synchronization to an external video timing reference. When in Free-run mode, the GS4911B can also be used to provide clock and timing signals for the stand-alone Pattern Generator.
3.4.4 Optical Connector (U30)
Optionally, a Gennum GO2921 Optical Module (U30) may be plugged into the cage provided. The GO2921 is an optical transceiver which allows input of a signal via optical fibre, and outputs a video signal from one of the GS2972 Transmitters (U15, U16). 3Gb/s, HD and SD video signals are supported.
3.4.5 SDI Outputs (J8, J9)
Two BNC connectors for SDI outputs, J8 and J9, are connected to the two GS2972 Transmitters U15, U16 respectively.
3.4.6 SDI Loop-Through (J5)
A re-clocked or non-re-clocked buffered version of the input stream from GS2970A is available on the serial loop-through output (J5). It is designed to be SMPTE compliant for voltage level, rise/fall time and return loss at three rates (SD, HD and 3G) using the compensation network. The GS2978 Cable Driver is necessary to guarantee return loss specification.
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The signal rate on the GS2978 Cable Driver is automatically set to SD or HD mode by the RATE_DET signal from the GS2970 (U8).
3.4.7 Audio Outputs (J1, J2)
For AES mode, AES-encoded CMOS-level signals are distributed through line drivers and supplied to two BNC connectors (J1, J2).
3.4.8 GSPI Header (J7)
The standard Gennum SPI header on the 3Gb/s SDI Demo Board, along with the optional SPI dongle, allow the user to explore all settings and tuning possibilities of Gennum's 3Gb/s SDI and timing products, through a USB connection to a PC.
Gennum's GS2970, GS2972 and GS4911B devices contain sets of internal status and configuration registers. These registers are available to the host via the SPI.
3.4.9 EXP Connector (JX1)
The EXP Connector JX1 on the 3Gb/s SDI Demo Board interfaces to the Xilinx Spartan-3A DSP 1800 Board.
Input Signals:
• 2 x 10-bit video data from two GS2970s
• 2 x PCLK from two GS2970s
• 2 x STAT[0:4] outputs from two GS2970s, HVF and rate detection
• Serial audio input ACLK, WCLK, DATA1_2 and DATA3_4 from one GS2970
• HVF, PCLK and ACLK1 from GS4911B
• Inputs from GSPI header SCLK, SDIN, CS
Output Signals:
• 2 x 10-bit video data from two GS2972s
• 2 x PCLK to GS2972s
• HVF input to first GS2972
• Serial audio input to first GS2972, ACLK, WCLK, DATA1_2 and DATA3_4
• SDOUT to the GSPI header
• SCLK, SDIN, 6 x CS for the GSPI on the board
• Output from the SPI on the board SDOUT
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Table 3-5: EXP Connector Signals
FPGA Pin Xilinx Board Net Name 3Gb/s SDI Board Net Name JX1 Pin Notes
AE25 EXP2_SE_IO_1 DESA_DATA13 1 −
V16 EXP2_SE_IO_0 DESA_DATA12 2 −
AF25 EXP2_SE_IO_3 DESA_DATA14 3 −
Y17 EXP2_SE_IO_2 DESA_DATA11 4 −
AE23 EXP2_SE_IO_5 DESA_DATA15 7 −
AA18 EXP2_SE_IO_4 DESB_AUD2 8 −
AF23 EXP2_SE_IO_7 DESA_DATA16 9 −
AC20 EXP2_SE_IO_6 DESA_DATA10 10 −
AD22 EXP2_SE_IO_9 DESB_DATA15 13 −
AA17 EXP2_SE_IO_8 GSPI0 14 −
AE21 EXP2_SE_IO_11 DESA_DATA18 15 −
AC19 EXP2_SE_IO_10 GSPI1 16 −
AD21 EXP2_SE_IO_13 DESA_DATA19 19 −
AB18 EXP2_SE_IO_12 DESB_AUD3 20 −
AC21 EXP2_SE_IO_15 DESB_DATA10 21 −
V15 EXP2_SE_IO_14 DESB_DATA11 22 −
U23 EXP2_SE_IO_17 DESA_STAT0 25 −
W15 EXP2_SE_IO_16 DESB_DATA12 26 −
U24 EXP2_SE_IO_19 DESA_STAT1 27 −
AB16 EXP2_SE_IO_18 DESB_DATA13 28 −
AD20 EXP2_SE_IO_21 DESA_DATA17 31 −
M21 EXP2_SE_IO_20 DESA_STAT3 32 −
AF19 EXP2_SE_IO_23 DESB_DATA16 33 −
AC16 EXP2_SE_IO_22 DESB_DATA14 34 −
AE19 EXP2_SE_IO_25 DESB_DATA17 37 −
U22 EXP2_SE_IO_24 DESA_STAT4 38 −
AD19 EXP2_SE_IO_27 DESB_DATA18 39 −
AC15 EXP2_SE_IO_26 DESB_DATA19 40 −
R20 EXP2_SE_IO_28 DESA_STAT2 41 −
AA13 EXP2_DIFF_CLK_IN_p DESB_AUD0 42 −
AF13 EXP2_SE_CLK_IN DESA_PCLK 43 −
Y13 EXP2_DIFF_CLK_IN_n DESB_AUD1 44 −
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R19 EXP2_SE_IO_29 DESB_STAT0 47 −
V14 EXP2_SE_IO_30 RESET 48 −
Y14 EXP2_SE_CLK_OUT DESB_PCLK 49 −
U15 EXP2_SE_IO_31 GSPI2 50 −
AD14 EXP2_DIFF_p21 SERA_PCLK 53 −
V10 EXP2_DIFF_p20 DESB_STAT3 54 −
AC14 EXP2_DIFF_n21 SERA_DIN19 55 −
W10 EXP2_DIFF_n20 GSPI8 56 −
K23 EXP2_SE_IO_32 DESB_STAT1 59 −
V13 EXP2_DIFF_p18 SERA_HVF1 60 −
M22 EXP2_SE_IO_33 DESB_STAT2 61 −
W13 EXP2_DIFF_n18 SERA_HVF0 62 −
AB12 EXP2_DIFF_p19 SERA_DIN18 65 −
Y12 EXP2_DIFF_p16 SERA_HVF2 66 −
AC12 EXP2_DIFF_n19 SERA_DIN17 67 −
AA12 EXP2_DIFF_n16 DESB_STAT4 68 −
AE17 EXP2_DIFF_p17 ACLK1 71 −
W17 EXP2_DIFF_CLK_OUT_p SERA_AUD0 72 −
AD17 EXP2_DIFF_n17 GSPI4 73 −
V17 EXP2_DIFF_CLK_OUT_n SERA_DIN14 74 −
AF20 EXP2_DIFF_p15 GSPI5 77 −
V12 EXP2_DIFF_p14 SERA_AUD2 78 −
AE20 EXP2_DIFF_n15 GSPI3 79 −
W12 EXP2_DIFF_n14 SERA_DIN16 80 −
AE9 EXP2_DIFF_p13 SERA_DIN13 81 −
AD11 EXP2_DIFF_p12 SERA_AUD1 82 −
AF9 EXP2_DIFF_n13 SERA_DIN12 83 −
AC11 EXP2_DIFF_n12 SERA_DIN15 84 −
AE8 EXP2_DIFF_p11 SERA_DIN15 87 −
AF14 EXP2_DIFF_p10 SERA_AUD3 88 −
AF8 EXP2_DIFF_n11 SERA_DIN10 89 −
AE14 EXP2_DIFF_n10 PCLK4911 90 −
Table 3-5: EXP Connector Signals
FPGA Pin Xilinx Board Net Name 3Gb/s SDI Board Net Name JX1 Pin Notes
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3.5 Push Buttons
3.5.1 Reset (SW4)
When the push button (SW4) is held low on the Xilinx Board, a reset signal is applied to the FPGA. It should be pushed every time after power-up or when the operating mode has changed. The power-on-reset circuit on the FPGA Board is not functional, since it is asserted for only 400ms before the FPGA configuration is done.
3.5.2 Test Pattern (SW7 & SW8)
The pattern generator is active when in the Test Pattern operating mode.
In Genlock mode, the pattern generator is synced to the external sync input. When in Free-run mode, it does not need an external sync input.
AD7 EXP2_DIFF_p9 SERB_PCLK 93 −
AB9 EXP2_DIFF_p8 GSPI6 94 −
AE7 EXP2_DIFF_n9 SERB_DIN19 95 −
AC9 EXP2_DIFF_n8 GSPI7 96 −
AC6 EXP2_DIFF_p7 SERB_DIN18 99 −
Y10 EXP2_DIFF_p6 TIMING0 100 −
AD6 EXP2_DIFF_n7 SERB_DIN17 101 −
AA10 EXP2_DIFF_n6 TIMING1 102 −
AC8 EXP2_DIFF_p5 SERB_DIN16 105 −
W9 EXP2_DIFF_p4 TIMING2 106 −
AB7 EXP2_DIFF_n5 SERB_DIN15 107 −
Y9 EXP2_DIFF_n4 GSPI_Dongle0 108 −
AE4 EXP2_DIFF_p3 SERB_DIN14 111 −
V11 EXP2_DIFF_p2 GSPI_Dongle1 112 −
AF4 EXP2_DIFF_n3 SERB_DIN13 113 −
U11 EXP2_DIFF_n2 GSPI_Dongle2 114 −
AE3 EXP2_DIFF_p1 SERB_DIN12 117 −
AF5 EXP2_DIFF_p0 GSPI_Dongle3 118 −
AF3 EXP2_DIFF_n1 SERB_DIN11 119 −
AE6 EXP2_DIFF_n0 SERB_DIN10 120 −
NOTE: 3.3V and 2.5V Power and Ground are supplied by the Xilinx FPGA Board through JX1.
Table 3-5: EXP Connector Signals
FPGA Pin Xilinx Board Net Name 3Gb/s SDI Board Net Name JX1 Pin Notes
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The output test pattern can be changed by using two push buttons: SW7 (PB3) for UP and SW8 (PB4) for DOWN. The video test patterns are shown in Table 3-6:
3.5.3 Test Pattern Video Standard (SW5, SW6)
The video standard of the test pattern can be changed by using two push buttons: SW5 (PB1) for UP and SW6 (PB2) for DOWN (Figure 2-5). The test pattern video standards are shown in Table 3-7.
NOTE: After power-up or reset, the board does not output a test pattern signal until SW5 or SW6 is pressed.
Table 3-6: Video Test Patterns
ID Pattern
0 Check Field/Pathological
1 100% Colour Bars
2 75% Colour Bars
3 SMPTE RP219 Bars
4 EG1 Bars
5 5 Step Stair Case
6 Luma Step
7 75% Blue
8 Green
9 Red
10 100% Black
11 40% Gray
12 100% White
13 75% Colour Bars
14 75% Colour Bars
15 75% Colour Bars
Table 3-7: Test Pattern Video Standards
LED7,8,9,10 GS4911B VID_STD Standard
0000 21 1080p60 1920x1080/60/1:1 148.5 MHz
0001 22 1080p59.94 1920x1080/59.94/1:1 148.35 MHz
0010 23 1080p50 1920x1080/50/1:1 148.5 MHz
0011 29 1080p30 1920x1080/30/1:1 74.25 MHz
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3.5.4 SPI PROM Programming (J10)
To program the SPI PROM, add a shunt on JP7 of the Xilinx Board and connect the Xilinx Programming Cable (with flying leads) to J10 of the Xilinx Board. Power-down the boards and remove the shunt after programming. For more details, please refer to Xilinx document xapp1053.pdf, “Flash Memory Boot Loading Using SPI with Spartan-3A DSP 1800A Starter Platform”.
3.5.5 JTAG Programming (J2)
The FPGA may be programmed any time when power is on through JTAG (J2) on the Xilinx Board. It is a preferred mode in code debugging stage. It is quick but it is volatile after power down.
0100 31 1080p29.97 1920x1080/29.97/1:1 74.175 MHz
0101 33 1080p25 1920x1080/25/1:1 74.25 MHz
0110 35 1080p24 1920x1080/24/1:1 74.25 MHz
0111 37 1080p23.98 1920x1080/23.98 74.175 MHz
1000 25 1080i60 1920x1080/60i 74.25 MHz
1001 26 1080i59.94 1920x1080/59.94i 74.175 MHz
1010 27 1080i50 1920x1080/50i 74.25 MHz
1011 11 720p60 1280x720/60/1:1 74.25 MHz
1100 12 720p59.94 1280x720/59.94/1:1 74.175 MHz
1101 13 720p50 1280/720/50/1:1 74.25 MHz
1110 14 720p30 1280x720/30/1:1 74.25 MHz
1111 15 720p29.97 1280x720/29.97/1:1 74.25 MHz
Table 3-7: Test Pattern Video Standards
LED7,8,9,10 GS4911B VID_STD Standard
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4. Getting Started
4.1 Quick Start GuideFigure 4-1 shows the minimum requirements for a basic setup.
Figure 4-1: Quick Start Basic Setup
Please follow the steps below to achieve a quick start up:
1. Slide the PWR ON/OFF switch (SW1) to the OFF position, and apply power to the jack (J5).
2. Confirm that all jumpers and switches are set to their default state.
3. Connect the Xilinx programming cable to the board, add a shunt to JP7, power-up the board and program the SPI PROM. Skip this step if the SPI PROM has been programmed or the factory default program in the PROM will be used. Refer to the Xilinx document ds593.pdf on how to use the Programming Cable.
4. If the SPI PROM has just been programmed, power-down the Xilinx Board, unplug the programming cable and remove the shunt on JP7.
5. Plug the SDI Demo Board JX1 connector (on the bottom side of the Gennum 3Gb/s SDI Demo Board) into the JX2 connector located on the right hand side of the Xilinx Board. Secure with the hardware provided (screws, stand-offs, washers and nuts).
6. Connect a SDI video source to the AIN1(J3), AIN2(J4) and BIN1(J6) BNC connectors located on the right-hand side of the SDI Demo Board. These connectors accept SD, HD and 3G SDI input signals. A loop-through output is available on J5 of the SDI Demo Board.
Xilinx Board3Gb/s SDI
Demo Board
J1
PWRLED
RESET
PWR SW
PWR Jack
Video Source (TG700)
AC Adaptor
SDI Monitor(WFM 7120)
AC
J2
J5
J3
J4
J6
J8
J9
J12
J10
J11
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7. Connect the output video cables to the AOUTn(J8) and BOUT(J9) BNC connectors located on the right-hand side of the SDI Demo Board.
8. Connect the AES Audio Input signals to AES_IN1 (J10) and AES_IN2 (J11); AES_IN1 is for embedding audio channels 1 and 2, while AES_IN2 is for channels 3 and 4.
9. For Genlock to an external black burst signal, connect a source to EXT_SYNC (J12).
10. For de-embedded audio, connect the cables onto AUDIO_OUT1 (J1) and AUDIO_OUT2 (J2).
11. Set up the Operation Mode by SW3 (bits 1-3) on the Xilinx Board. Refer to Table 3-1: Operation Modes set by SW3 on Xilinx Board.
12. Set the PWR ON/OFF switch (SW1) to the ON position on the Xilinx Board. After D1 (a Blue LED) on the Xilinx Board is activated, manually reset the boards by pressing SW4 (RESET) button. The board performs an initialization after reset. First, the FPGA configures the I/O Expander's pins as outputs, and then the control pins on the Gennum devices are set by the I/O Expander. If required by the operating mode, the internal registers of the Gennum devices are written by the FPGA through the daisy-chained SPI to complete the initialization.
When a new operation mode is selected through the DIP switches, the devices on-board are programmed for the new mode by the FPGA via the GSPI daisy chain and the MAX 7301 I/O Expander.
The GS2970s and GS2972s are configured in SMPTE mode by default. They perform full SMPTE processing, and feature a number of signal integrity checks and measurement capabilities.
Refer to the GS2970 and GS2972 Data Sheets for a more detailed explanation of their modes of operation.
For the SDI receiver Rate Selection, the GS2970s automatically detect the input signal as SD-SDI, HD-SDI or 3G-SDI.
For the SDI Transmitter Rate Selection, the GS2972s are configured by the FPGA to output the detected rate. The FPGA reads the rate values from the SDI Receivers, and programs the RATE_SEL pins on the GS2972 accordingly via the I/O Expander.
When no video input signal is detected by either Equalizer (U6 or U7), the corresponding Receivers (U8, U11), can be placed in Standby mode. In this mode, no signal is generated at the output, and the power consumption is reduced. By default, this mode is disabled by DNP R130 and populating R131 on the SDI Demo Board.
In Pass-through Mode, Input A needs a valid signal for the board configuration to stabilize so that Input B can work without any interruption. This is due to the FPGA attempting to detect the input on A and configure the board, repeatedly.
In Test Pattern Generator Mode, the GS4911B is configured to provide the clock and timing signals of the selected standard. The test pattern output is available on SDI Output A (J8).
NOTE: After power-up or reset, the board does not output a test pattern signal until SW5 or SW6 is pressed. SMPTE RP219 Bars and EG1 EG1 Bars may not look exactly the same as that from other pattern generators.
13. In Pattern Generator Mode, the user can change the pattern by using push buttons SW7/8, or the Video Standard by using push buttons SW5/6 on the Xilinx Board.
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14. Every time, after a change to the Operating Mode, reset the boards by pressing the SW4 (RESET) button.
4.2 FPGA Configuration
4.2.1 JTAG Direct
J2 on the Xilinx Board is a JTAG port with direct access to the FPGA. The bit file may be downloaded to configure the FPGA any time after power-up, using iMPACT and Xilinx programming cables (Platform Cable USB II and Parallel Cable IV). Refer to the Xilinx documents for more details.
This method is appropriate for the code-debugging stage, since it is faster to update the configuration on the FPGA than it is to program a SPI PROM. However, it is volatile, and every time after power-up, the cable has to be used to download the code.
4.2.2 SPI PROM
When the code is fully debugged, or a live-on-power-up is anticipated, the code can be downloaded to the non-volatile SPI PROM on the Xilinx Board. The FPGA reads the data from the on-board PROM, and program itself in Master Serial Mode every time after power up.
To program the PROM, please refer to Xilinx document XAPP1053, “Flash Memory Boot loading Using SPI with Spartan-3A DSP 1800A Starter Platform”.
5. Advanced User Guide
The next step after evaluating Gennum’s 3Gb/s products, is to design the user application board, and the associated FPGA code. This chapter presents the implementation details of this demo/evaluation platform for the low cost Spartan 3A FPGA.
5.1 Top Level ArchitectureFigure 5-1 is a simplified diagram of the FPGA top level architecture. It consists of a Test Pattern Generator, Channel A/B Input Paths, a Board Control Unit, Output Mux A/B and a SPI Interface.
The Board Control Unit sets the operating mode, provides access to the internal registers via the SPI. It also sets the control pins of the Gennum devices, via Maxim's MAX 7301 I/O Expander.
The right and left side of the diagram lists the signals to or from various blocks on the board. Also illustrated are the data paths, clock paths and the major building blocks inside of the FPGA to achieve the five major operating modes. The signals in grayed-out text are reserved, and are not used in the current design.
Please refer to the FPGA code provided with the kit.
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Figure 5-1: Simplified Top Level Architecture
5.2 Clock Tree and Data PathFigure 5-2 shows the Test Pattern Generator data path, Receiver A Input Path, Receiver B Input Path, Output Muxing and Clock trees in detail.
To achieve the best performance in the low cost FPGA, the following design rules have been applied:
• No DCM is used in the Receiver A/B input/output paths to ensure low additive clock jitter to the Transmitters
• Input data are captured by the DDRs in the IOBs to ensure predictable timing margin
• Source synchronous output: DDR data and clock output both use DDR registers in the IOBs to achieve constant phase-relation, regardless of the FPGA package and S&P&R pass
• The clock trees are manually allocated, and locked so that the usage of the FPGA resources are minimized with the best performance, and there will be still some
reset_n
Desa_pclk10
Desa_pclk
Desa_stat5
Desb_pclk10
Desb_pclk
Desb_stat5
Timing3
pclk4911
Inv_pclkaInv_pclkb
clk
Sera_din10
Sera_pclk
Sera_HVF3
Serb_din10
Serb_pclk
LED_out8
To Ser A
To Ser B
From Des A
From Des B
From Genlock
System Signals
Pb_std2
Pb_patt2
dip_conf_sel2
gspi_dongle4
Dip_clk2
Dipb_clk2
To/From:Configuration I/F
FPGA
GSPI9
BoardControl
Test PatternGenerator
Channel AInput Path
Channel BInput Path
OutputMux A
OutputMux B
GSPInterface
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global clock resources available for the user. Please note; the Xilinx ISE tool is not able to automatically place and route the complicated clock trees
• The FIFO Rx_FIFO_A and Rx_FIFO_B are added for data crossing different clock domains. They are read after the rd_data_count reaches 9, and do not stop until the FIFOs are reset
Figure 5-2: Clock and Data Path
On the FPGA, the Pattern Generator produces a video signal based on the clock (PCLK4911) and timing signals (FPGA internal name FVH_in or FPGA pad name Timing[2:0]) from the GS4911B. The output multiplexer selects an output among the A and B video streams, and the Pattern Generator signal.
5.3 Pattern GeneratorThe Test Pattern Generator generates test patterns of up to sixteen HD/3G video standards and sixteen patterns, as show in Table 3-6 and Table 3-7. The GS4911B on the 3Gb/s SDI Demo Board provides the pixel clock and timing signals (HVF). It can be set for either Free-run mode or Genlock mode to an external sync signal.
Desa_pclkDesa_pclk_int
DDR_IN_3Desa_data Reg
RxFIFO
A
DESA_PCLK_sig
Reg
FIFOPatgen Reg
Desb_pclkDesb_pclk_int
DDR_IN_3Desb_data Reg
RxFIFO
B
DESB_PCLK_sig
Reg
Reg
Reg
DDR
DDR
Reg
pclk_PG
SERB_DIN
SERA_DIN
FVH_in
PCLK4911
DD
DCM_PLLx2
PatternGen &Mux
Pattern Generator
Des A input Path
Des B input Path
BUFGMUX
BUFGMUX
BUFGMUX
BUFGMUX
DDR SERA_PCLK
DDR SERB_PCLK
PCLK4911_buffed
Outputmuxing
Output Stage
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5.3.1 Top Level Architecture
Figure 5-3 illustrates the major blocks in the Pattern Generator, and the following items:
• The configuration signals from the control block of the FPGA on the left side
• The clock and timing signals from the GS4911B
• The system level clock and reset signals
• The generated test pattern data/clock/timing and lock signals on the left side
• The data flow between the blocks
The DCM_PLLX2 block generates 2x clock for all HD standards. Since the GS4911B provides 1x clock while the Transmitter is wired for 10-bit mode, this results in a requirement for a 2x clock. It also outputs DCM lock status for other blocks on the FPGA. The Pattern_Gen block generates 20-bit YCbCr data stream for the selected standard and pattern. The Max_20b_10b multiplexes the 20-bit data onto the upper 10-bit bus for all HD standards, and flows through the 20-bit data for all 3G standards. The output stage of the FPGA will multiplex 20-bit SDR (Single Data Rate) on to 10-bit DDR for all 3G standards.
Figure 5-3: Pattern Generator Top Level Architecture
5.3.2 Reset Network
Figure 5-4 shows the reset network of the design. SPI_Box, OutputMuxing, Ctrl_block, DDR in/out/clk blocks get the reset from FPGA pin (reset_n).
The Pattern Generator block (PG_TOP) is clocked by a variable clock from the GS4911B through a DCM. The reset is de-asserted after the clock is configured on the GS4911B and becomes stable on the DCM. The Pattern Generator gets a reset under the following conditions:
• The board resets when reset_n is asserted LOW; or
DCM_PLLX2
Gs4911_buffed
Clk_2x_sig
HVF_in DDPattern_Gen
HVF_in
HVF_patt_sig
Y_in
C_in
Max_20b_10b
HVF_out
Vid_out_H
Vid_out_L
Gs4911_buffed_out
Clk_out
rstclk
sys_clk
sel_20_10b_in
interlaced_inPatt_sel_in
4
Std_720p
3 DCM4911_LOCKEDDCM4911_LOCKED
3
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• The GS4911B is re-configured (indicated by ready_c), which may cause the clock frequency of the Pattern Generator to change
The reset signal to pattern_gen is held LOW until the PCLK4911 is stable, and the DCM in DCM_PLLX2 is locked to PCLK4911. The time is currently set to 1.3s, without checking GS4911B lock status. Ideally, the GS4911B clock lock status is used to reset the DCM.
Figure 5-4: FPGA Reset Network
reset_n rst_n rst
SPI_Box
OutputMuxing
Ctrl_block
DDR in/out/clk
PG_TOP
Ready_c:Indication that the modeconfiguration is done.
or
Dcm4911_locked
DCM_PLLX 2
Rst_PG
Dcm4911_locked
Pattern_Gen
rst
Rst to reset pix_countand Line_count
HV_Count.v
Rst to reset output
Rst to reset y_ramp_temp
Gen_path
Gen_Bar
clk
PCLK4911 clk_x2_sig
gs4911_buffed toctrl_block
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5.3.3 Clock Generator
The clock generator produces a 1x clock (clk0_out) and a 1x/2x switchable clock (clk2x_out). They are phase-aligned with the input clock PCLK4911. The 1x clock is used mainly by the pattern generator, and the 2x clock is used by the 20-bit to 10-bit multiplexer and the FPGA DDR data output stage.
The DCM Reset Manager extends the reset up to 1.3s after the GS4911B is configured and PCLK4911 is stable, before de-asserting the reset to the DCM.
The BUFGMUXs are wired as show in Figure 5-5, so that the DCMs within a pair may be use for the Pattern Generator. They are locked down in the UCF file, so that the timing is optimized with the minimum number of BUFGMUXs.
Figure 5-5: Clock Generator for the Pattern Generator
5.3.4 Colour Bar Generator
The Colour Bar Generator generates the patterns shown in Table 3-6, except Check Field/Pathological, which is generated by another sub-block (Gen_Path) in Pattern_Gen.
Figure 5-6 shows the signal flow of this sub-block.
PCLK4911
BUFGMUX
DCM
Clk0_buf
I0
Clk2x_buf
I1
‘0’
Clk0_out
CLKFB_IN
CLKIN_IN
BUFGMUX
I0
I1
CLK2X_OUT
CLK2X_SELECT_IN
DCM4911_L0CKED
RST_IN DCMReset
Manager
DCM_RST
sys_clk
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Figure 5-6: Colour Bar Generator in Pattern_Gen
5.3.5 20b to 10b Mux
The Max_20b_10b block multiplexes the 20-bit data on to the upper 10-bit bus for all HD standards, and flows through the 20-bit data for all 3G standards. The data output stage of the FPGA will multiplex 20-bit SDR into 10-bit DDR for all 3G standards.
YC_rd_sync sub-block is used to synchronize the H leading edge with the 10-bit chroma output.
After reset, this block will wait for the FIFO to be filled, and then begin to read the data from both the Y and the C FIFO, until the falling edge of the H is detected. It will set the sel_y_c properly for the initial value, and sel_y_c/sel_y_c_n will toggle on every clk_x2 thereafter.
The FIFOs were designed for the data to cross different clock domains.
‘0’
‘1’
Y_ramp_en
Y_out_temp[9:0]
Y_ramp[9:0]Y_ramp_block(1 clk dly)
Ctrl_y_ramp_sig
HVF_del2[2:0]clk
Y_ramp_inc[15:0]Y_ramp_sel
Patt_sel[3:0]
Sel_V_region(1clk dly)
HVF_in[1]
Luma ROM10bx32
(1 clk dly)
Chroma ROM10bx64
(1clk dly)C_out[9:0]
Rom_addr[4:0]
Chroma_sel
ROM_addr_sel
Smpte_rom_addr[4:0]EG1_rom_addr[4:0]
Region_h[3:0]
Smpte_bar_adr_sel
Smpte_barEG1_bar
Patt_sel[3:0]
Bar
Pic_count[0]
Pic_count[10:0]HVF_del2_in[2:0]
Bar
HVF_del2_in[2:0] DD HVF_out[2:0]
rstclk
clk
clk
Sel_1080_720
Sel_720pcol_bar
step5_bar
V_change_con
Smpte1_barSmpte2_barSmpte3_barCol_bar7EG1_bar2
Y_out[9:0]
Y_ramp_init[15:0]Region_v[1:0]
Sel_H_region(1clk dly)
HVF_in[2:0]
Line_count[10:0]
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Figure 5-7: Mux_20_10b
5.4 Optical ModuleA connector and cage are provided on the board for an Optical Module as a resource for evaluation; an Optical Module can be purchase for evaluation, but it is not a major operation mode in this FPGA code design. The test wiring diagram of this module is shown in Figure 5-8. To test the Optical Module, follow the setup and procedure below.
Setup:
• Add a shunt on JP4 of the 3Gb/s Demo Board to enable the Optical Module
• Use a fibre cable for loop-back connection
• Operation Mode: Test Pattern Generator (SW3 bit1-3=”ON-OFF-ON”)
• Data Path: Pattern Generator on FPGA->Ser A->Optical Tx->Fibre->Optical Rx->Des B->FPGA->Ser B->SDI Monitor
Procedures:
To enable 3G mode, connect a 3Gb/s source to J6 (BIN1), remove the shunt on J14, power-up the boards, and then reset the boards. The FPGA will detect the rate on the Des B and configure Ser B for 3G mode. Then change the test pattern standard/pattern for 3G and add the shunt on J14.
CLK
HVF_IN[2:0]
C_IN[9:0]
CLK
CLK_X2
FIFO_13X4_inst_C
Din_C[12:0]Q_C_sig[12:0]
Rdusedw_C_sig[3]Rd_C_FIFO_sig
&
Sel_y_c
Rd_Y_FIFO_sig
Sel_20_10b
rst
rst
‘0’
‘1’
Vid_out_sig[12:0]
Vid_out_int1[19:0]DFFs
Sel_20_10b
Q_Y_sig[12:0]
YC_rd_sync
CLKrst
‘0’
‘1’
‘0’
‘1’Q_C_sig[12:3]
Rd_C_FIFO_sig
HVF_out_int1[19:0]
Q_Y_sig[0]
Sel_y_c_b
FIFO_13X4_inst_Y
HVF_IN[2:0]
Y_IN[9:0]Din_Y[12:0]
CLK_X2
Q_Y_sig[12:0]
Rdusedw_Y_sig[3]
Rd_Y_FIFO_sig
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To enable HD mode, connect a HD source to J6 (BIN1), remove the shunt on J14, power-up the boards, and then reset the boards. The FPGA will detect the rate on the Des B and configure Ser B for HD mode. Change the test pattern standard/pattern for HD and add the shunt on J14.
Power-down the boards. Remove the shunt on JP4 of the 3Gb/s SDI Demo Board. Remove the Optical Module from the cage.
Figure 5-8: Optical Module Test Data Flow
SDOn
U11Des B
U15Ser A
U16Ser B
U30OPT
SDO
Fibre
AOUTnJ8
BoutJ9
1
0
J14
BIN 1J6
FPGA
R5
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5.5 Data PathFigure 5-9 shows the input data to clock phase and output data to clock phase in the FPGA. Please refer to the GS2970 and GS2972 data sheets to verify your design.
Figure 5-9: Data Clock Phase
5.6 I/O Timing ClosureThe 3Gb/s SDI Demo Board is designed to work with Xilinx FPGA Evaluation Boards with HSMC connectors. To use the limited number of the signal pins on the HSMC connector for 4 Gennum's SDI devices, parallel data busses are all wired in 10-bit mode. When the video is 1080p60, the data rate even rise up to 297Mb/s in LVCMOS DDR
Y0 Y1Cb0 Cr0DESA_DATA Y2 Cb1 Y3 Cr1
DESA_PCLK
Y0 Y1Vid_in_a_d1[9:0] Y2 Y3
Cb0 Cr0 Cb1
Y0SER_DIN Cb0 Cr0 Cb1Y1 Y2
Y0
Cb0
Y1
Cr0
Y2
Cb1
Y3
Cr1
DESA_PCLK_sig
SERA_PCLK
Delayed SERA_PCLK
Vid_in_a_d1[19:10]
Vid_out_a_d1[9:0]
Vid_out_a_d1[19:10]
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mode. The traces are around 7 inches long with the impedance uncontrolled, length unmatched on the Xilinx FPGA board. Timing has to be carefully budgeted, constrained and verified on the board for reliability. This topic will be discussed in the rest of this section. In the end user products, shorter, impedance-controlled and length-matched traces are recommended for best timing margin and signal integrity.
5.7 Clock TerminationThe FPGA drives the GS2972s in source synchronous mode. All output data bits and clock signals use DDRs in the IOBs to minimize the skew. There are some options for the clock implementation to achieve the data to clock setup/hold time required by the GS2972:
• Use a DCM to shift the clock by 90° to centre the clock edge in the data window. It provides the best timing margin but it costs the FPGA DCM/BUFG clock resources and adds clock jitter
• Use the general routing resources in the FPGA to adjust the clock delay to centre the clock edge in the data window; the clock routing has to be done manually in the FPGA each time with S&P&R (Synthesize, Place and Route pass)
• Use the drive-strength/slew-rate adjustment of the output buffers to shift data/clock; the highest drive strength can not be used because of the excessive overshoot, undershoot and crosstalk. Some low drive-strength options can not be used due to the slow fall-time of the buffers, so the delay adjustment through OBUF is very limited. It is difficult to achieve the optimal timing with this method
• Use capacitive load on the clock line to delay the clock. Based on the Xilinx WP217 and Spartan 3 DSP switching characteristics, the clock may be delayed by an external capacitive load. Simulation has been done to verify the possibility of this solution
The DDR data and clock both use DDR registers in IOBs, which means the data and clock are edge aligned off the FPGA with the same load.
When loaded with a 33pF capacitor in parallel with a 150Ω resistor, the clock is delayed by ~1.2ns on the PCLK input pin of the GS2972. Figure 5-10 illustrates this idea.
To improve the timing margin, the clock is further delayed on the GS2972 by turning on the PCLK delay line on the GS2972.
Figure 5-10: Clock Termination
GS2972
150R 33p
PCLKFPGA 50Ω transmission line
DIN50Ω transmission line
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5.8 FPGA User ConstraintsThe timing constraints need to be specified in the ucf file, to guide the ISE Tools to route the design with the timing met. For the board level timing parameters, the following work has been done to optimize the board level timing margin:
• The de-serializer output timing is sample-verified
• The FPGA output timing is simulated for signal integrity and timing
• The serializer input timing is sample verified
• FPGA I/O timing constraints are set-up based on the timing measurement and the switching parameters of the Gennum devices
Some user constraints are set in the ucf file to achieve the timing goal. To help the application designers to get the similar performance, some examples are given in this section.
5.8.1 Input Data Window Specification
The constraint below specifies the DDR data to clock timing of the channel A input. The setup time is 1.45ns and the hold time is 0.45ns on the FPGA pins:
NET “DESA_DATA<*>” TNM = Data_In_A;TIMEGRP “Data_In_A” OFFSET = IN 1.45ns VALID 1.9ns BEFORE “DESA_PCLK” RISING;
5.8.2 Internal Clock Constraints
The constraints below specify the clock periods of the internal generated clock signals. They may not be listed on the Timing Constraints GUI of ISE, but they need to be specified in the UCF file to meet the timing requirements of the design:
NET “Inst_PG_Top/gs4911_buffed” TNM_NET = “gs4911_buffed”;TIMESPEC TS_gs4911_buffed = PERIOD “gs4911_buffed” 6.6ns HIGH 50%;NET “Inst_PG_Top/clk_x2_sig” TNM_NET = “clk_x2_sig”;TIMESPEC TS_clk_x2_sig = PERIOD “clk_x2_sig” 6.6ns HIGH 50%;
5.8.3 MAXDELAY Constraints
The routing delay of the clock signals must be controlled. Here are some examples of the delay constraints for the clock signals:
NET “DESA_PCLK” MAXDELAY = 1ns;NET “DESB_PCLK“ MAXDELAY = 1ns;NET “DESA_PCLK_sig” MAXDELAY = 1.8ns;NET “DESB_PCLK_sig” MAXDELAY = 1.8ns;
5.8.4 Location Constraints
When the usage of the clock resources is high, the ISE Tool will not be able to automatically place the clock primitives to achieve the timing. The instances have to be
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manually locked down in the ucf file. Here are some examples to place the instances on the FPGA:
INST “DESB_PCLK_buf” LOC = BUFGMUX_X2Y1;INST “DESA_PCLK_buf” LOC = BUFGMUX_X1Y1;INST “Inst_OutputMuxing/BUFGMUX_inst_A” LOC = BUFGMUX_X1Y0;INST “Inst_OutputMuxing/BUFGMUX_inst_B” LOC = BUFGMUX_X2Y0;
5.8.5 Non-Clock_Dedicated_Route
When a clock input uses a non-dedicated-clock input pin or there is no associated BUFGMUX available, the clock uses general routing resources to reach a BUFGMUX or DCM.
Here is an example of this attribute and the data to clock timing constraints:
NET “PCLK4911” CLOCK_DEDICATED_ROUTE = false;NET “TIMING<*>” IFD_DELAY_VALUE= 3;NET “TIMING<*>” TNM = “GS4911_FVH”;TIMEGRP “GS4911_FVH” OFFSET = IN 5 ns VALID 6 ns BEFORE “PCLK4911” TIMEGRP “gs4911_buffed”;
5.8.6 Input Delay Adjustment
When the ISE Tool is not able to meet the input timing constraints, an adjustment of the input delay for clock and/or data may help. Here is an example:
NET “DESA_PCLK” IBUF_DELAY_VALUE=0;NET “DESA_DATA*” IFD_DELAY_VALUE=3;NET “DESB_PCLK” IBUF_DELAY_VALUE=0;NET “DESB_DATA*” IFD_DELAY_VALUE=2;
5.8.7 Output Timing Adjustment
When the FPGA output timing does not meet the requirement by GS2972s, the drive-strength and slew-rate may be adjusted to shift the clock to data phases slightly. Here is an example:
NET “SERA_DIN*” DRIVE = 8;NET “SERA_DIN*” SLEW = fast;NET “SERA_PCLK” DRIVE = 16;NET “SERA_PCLK” SLEW = FAST;NET “SERA_HVF*” DRIVE = 8;NET “SERA_HVF*” SLEW = FAST;
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5.9 Host Interface and Register MapHost_if is a configuration and status register block accessible by PC through a GSPI dongle.
Figure 5-11: Host Interface Block Diagram
5.10 Suggestions• BUFG MUXes and DDRs have some routing limitations, do a floor plan with Xilinx
Tools before PCB layout
• Try to use short traces with controlled impedance and matched length for the Data/Clock/Timing signals between the FPGA and 3G Ser/Des to gain maximized timing margin
reset
Host_ifGspi_clkGspi_cs
Gspi_sdinGspi_sdout
pclkValue_in[11:0]Patt_sel[3:0]Patt_reg_ctrlstd_sel[3:0]Std_reg_ctrl
Conf_sel_reg_ctrlConf_sel[2:0]
CSR signalsSPI_BOX
GSPI_dongle[3]Gspi_cs
GSPI_dongle[0]Gspi_sclk
GSPI_dongle[1]Gspi_din
GSPI_dongle[2]Gspi_sdout
SPI_Module_Out(0)
SPI_Module_Out(1)GSPI_Internal_CSSPI_Module_Out(11)
When Gspi_dongle[3] = ‘0’, the GSPI dongle will control Ser/Des/CSR.Otherwise, SPI_Int_Ctrl will control.
SPI_Int_Ctrl SPI_Module_Out(4)
Table 5-1: Host Interface Register Map
Address Register Name Bits Access Reset Value
Valid Range
Descriptions
0 r0r.Patt_sel 3:0 R/W 0000 0 - 15 Pattern selection register
r0r.Patt_reg_ctrl 4 R/W 0 0 - 1 0: Pattern is controlled by push buttons
1: Pattern is controlled by register
1 r1r.Std_sel 3:0 R/W 0000 0 - 15 Video standard register of the test pattern
r1r.Std_reg_ctrl 4 R/W 0 0 - 1 0: Standard is controlled by push buttons
1: Standard is controlled by register
2 r2r.Conf_sel 2:0 R/W 000 0, 1, 4, 6, 7 Operation mode selection register
r2r.Confi_sel_reg_ctrl 3 R/W 0 0 - 1 0: Operation mode is controlled by push buttons
1: Operation mode is controlled by register
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6. Related Documents
6.1 Gennum's Documentation• GS2970 Datasheet (Doc ID 47478)
• GS2972 Datasheet (Doc ID 47479)
• GS4911B Datasheet (Doc ID 36655)
• GS2974B Datasheet (Doc ID 45062)
• GO2921 Datasheet (Doc ID 47116)
• GS2978 Datasheet (Doc ID 37186)
• FPGA code
6.2 Xilinx's Documentation• UG485 Getting Started with the Spartan-3A DSP S3D1800A Starter Platform User
Guide
• Sp3A-DSP-1800A-Starter-Schematic-Rev1.pdf
• xapp1053.pdf Flash Memory Boot loading Using SPI with Spartan-3A DSP 1800A Starter Platform
• ds593.pdf Platform Cable USB II Advance Product Specification
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7. Appendix
7.1 Schematics
Figure 7-1: Top Schematic
SERA_AUD[3..0]
CONTROL_25
GNDGND
ALPBCK
GND Clips
VCC_3.3V
TOP
AUDIO_OUT1
AUDIO_OUT2
VIDEO IN
Page 02_VIDEO INPUT A AND B
AIN1
AIN2
ALPBCK
AUDIO_OUT1
AUDIO_OUT2
DESA_DATA[19..10]
DESA_STAT[4..0]
DESA_PCLK
GSPI[8..0]
RESET
BIN1
BIN2
BIN2n
DESB_DATA[19..10]
DESB_STAT[4..0]
DESB_PCLK
DESB_AUD[3..0]
CONTROL_[27..0]
SDOUT_RXB
BIN1
GNDA
DESB_PCLK
GNDA
1
3 245
J11
BCJ-FPLV01
DESB_DATA[19..10]
DESB_STAT[4..0]
BIN2
EXT SYNC
Page 08_EXTERNAL SYNC
EXT_SYNC TIMING[2..0]
PCLK4911
GSPI[8..0]
RESET
SDOUT_TXB
CONTROL_25
ACLK1
1
3 245
J1
BCJ-FPLV01
DESB_AUD[3..0]
1
2 3 4 5 6 7
J3
UCBBJE20-1
1
3 245
J2
BCJ-FPLV01
CONTROL_[27..0]
ACLK1
SERA_DIN[19..10]
GSPI_Dongle[0:3]
BIN2n
SDIA2
CONTROL_[27..0]
GSPI_Dongle[0..3]
VIDEO OUT
Page 06_VIDEO OUT
AOUT
AOUTnSERA_AUD[3..0]
SERA_DIN[19..10]
SERA_HVF[2..0]
SERA_PCLK
BOUT
AES_IN1
AES_IN2
SERB_DIN[19..10]
CONTROL_[27..0]
SERB_PCLK
RESET
GSPI[8..0]
SDOUT_RXB
SDOUT_TXB
RESET
SDOUT_RXB
AUD OUT2
GND
AUD OUT1
GND
1. Net TIMING[2:0] and PCLK4911: +/-0.5"
Extra Trace Length Matching Requirement:
1
3 245
J10
BCJ-FPLV01
SERB_DIN[19..10]
2. SERA_PCLK, SERA_HVF[2:0] and SERA_DIN[19:10]: +/-0.25"
SERB_PCLK
SDOUT_RXB
OPTIB
TIMING[2..0]
LPBCK
GNDA_CD
1
2 3 4 5 6 7
J4
UCBBJE20-1
PCLK4911
GND
AUD IN2GND
AUD IN1
1
2 3 4 5 6 7
J5
UCBBJE20-1
R14675R
OPT_TD+
GND
SYNC
AOUTn
1
2 3 4 5 6 7
J6
UCBBJE20-1
SDIB1
CONTROL_[27..0]
1
2 3 4 5 6 7
J8
UCBBJE20-1
BOUT1
2 3 4 5 6 7
J9
UCBBJE20-1
GSPI[8..0]
RESET
AES_IN1
1
3 245
J12
BCJ-FPLV01
AES_IN2
GSPI2: SDOUTGSPI1: SDINGSPI0: SCLK
EXT_SYNC
GNDA
IO Expander
Page 10_IO EXPANDER
GSPI[8..0]
CONTROL_[27..0]
RESET
AOUTSERA_PCLK
Optical
Page 14_Optical
OPT_TD+
OPT_RD+
OPT_RD-
GNDA
EXP_CONNECTOR
Page 09_FPGA INTERFACE
GSPI_Dongle[0:3]DESA_DATA[19..10]
DESA_STAT[4..0]
DESA_PCLK
DESB_DATA[19..10]
DESB_STAT[4..0]
DESB_PCLK
DESB_AUD[3..0]
SERA_DIN[19..10]
SERA_HVF[2..0]
SERA_PCLK
SERA_AUD[3..0]
SERB_DIN[19..10]
SERB_PCLK
TIMING[2..0]
PCLK4911
GSPI[8..0]
RESET
ACLK1
SDIA1
Power
Page 11_Power
RESET
DESA_DATA[19..10]
GSPI[8..0]
12345678910
J7
TSW-105-07-L-DGNDA
SDOUT_TXB
RESET
GSPI[8..0]
DESA_STAT[4..0]
CS0_0 GSPI_Dongle3
JTAG/HOSTb
BOUT
R2 10KR3 10K
GSPI
CS3_0
SDOUT_0 GSPI_Dongle2
R1 10K
SDIN_0 GSPI_Dongle1VCC_3.3VSCLK_0 GSPI_Dongle0
AIN1
1 TP1
1 TP2
GND
SERA_HVF[2..0]
GSPI[8..0]
DESA_PCLK
1 TP4
1 TP3
RESET
GSPI4: CS1 -> DESBGSPI3: CS0 -> DESA
GSPI8: CS5 -> IO EXPGSPI7: CS4 -> GS4911GSPI6: CS3 -> SERBGSPI5: CS2 -> SERA
GSPI[8..0]
AIN2
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Figure 7-2: Video Input A and B
AUDIO_OUT1 1
ALPBCK1
AIN21
AIN11DESA_PCLK 9
DESA_STAT[4..0] 9
DESA_DATA[19..10] 9
AUDIO_OUT2 1
GSPI[8..0]6,8,9,10
Standby _SERB
GSPI[8..0]
+3.3V_2974
SDOUT_RXB 6
RATE DET
R51.15K
C10
4u7
DESA_LPBCKn
DESA_LPBCK
C2710n
C241u
C2610n
C2310n
R7
0R
C2810n
C2510n
DNP
GND
VCC_3.3V
C12
4u7
C110n
CONTROL_[27..0]10CONTROL_[27..0]
Standby _SERB
GNDA
EQUALIZER A
Page 03_EQUALIZERS A
AIN1
AIN2
EQA1_SDIEQA1_SDIn
EQA2_SDIEQA2_SDIn
Standby _SERA
CONTROL_26
C4610n
C4410n
C4510n
C4310n
VCC_1.2V
GND
GNDA
C20.1u
VIDEO IN A
GS2970Apins B2, C3, C4
GS2970A GS2970B GS2970Bpins B2, C3, C4
DESERIALIZER A
Page 04_DESERIALIZER A
SWA_SDI
SWA_SDIn
DESA_DATA[19..10]
DESA_STAT[4..0]
DESA_PCLK
DESA_LPBCK
DESA_LPBCKn
AUDIO_OUT1
AUDIO_OUT2
RESET
GSPI[8:0]
XTAL_OUT
RATE DET Lock A
SDOUT_RXA
Standby _SERA
CONTROL_[4..0]
+3.3VA_2970
A SRC SEL
CONTROL_26
R128
10KR12913.7K
CONTROL_26
CABLE DRIVER
Page 12_Cable Driv er
DESA_LPBCK
DESA_LPBCKnALPBCK
RATE DET
GNDA
CONTROL_[4..0]
GS2970A
C2110n
C2210n
C2010n
C191u
EQB1_SDI
GS2970Apins B1, H1, E1
RESET11
C3010n
C3110n
C3210n
C2910n
IOVDD_2970
GS2970B pins D6, E6, F6, G6
C710n
GS2970A pins D6, E6, F6, G6
RESET
EQB1_SDIn
GNDA
C310n
C5010n
C4810n
C4910n
C4710n
Lock A
GNDA
RESET
Standby _SERA
EQA2_SDI
XTAL_OUT XTAL_OUT
EQA2_SDIn
R1413.7K
R12
10K
EQA1_SDI
CONTROL_27
EQA1_SDIn
BIN2n14
BIN214
BIN11
DESB_AUD[3..0] 9
12
J14
CONTROL_27
IN01
/IN02
VT016
IN13
/IN14
VT15
SEL6
VC
C1
8G
110
G2
11
G3
14
G4
15
Q12
/Q9
VC
C2
13
NC7
PA
D17
U2
SY58017U
SWB_SDIn
SWB_SDI
C510n
C60.1u
VIDEO IN BB SRC SEL
DESB_PCLK 9
DESB_STAT[4..0] 9
DESB_DATA[19..1
RESET
DESERIALIZER B
Page 05_DESERIALIZER B
SWB_SDI
SWB_SDIn
DESB_DATA[19..10]
DESB_STAT[4..0]
DESB_PCLK
GSPI[8..0]
DESB_AUD[3..0]
RESET
XTAL_OUT
Lock B
SDOUT_RXA
SDOUT_RXB
CONTROL_[8..5]
Standby _SERB
EQUALIZER B
Page 13_Equalizer B
BIN1
EQB1_SDIEQB1_SDIn
Standby _SERB
CONTROL_27
C391u
GSPI[8..0]
C4210n
C4010n
CONTROL_[8..5]
C4110n
GNDA
+1.2VA_2970
Standby _SERA
+3.3V_2974
GS2970Bpins B1, H1, E1
+3.3V_2974
GS2970B
Lock B
12
J13
GS2970B pins A7,D10,G10,K7GS2970A pins A7,D10,G10,K7
Lock ALock B
GND
VCC_3.3VIOVDD_2970
GND
VC
CA
1
VC
CB
10
A0 2
A13
TR04
TR16
GN
D5
OEb7
B09
B18
U3
FXL2TD245
GND
VCC_3.3V
GND
A1 green1
A2 red2
K13
K24
U5
HSMF-C165
B Lock
A1 green1
A2 red2
K13
K24
U4
HSMF-C165
A LockVCC_3.3V
R10
75R
GND
R8
75R
C9 4u7
SDOUT_RXA
R41.15K
C11 4u7
IN01
/IN02
VT016
IN13
/IN14
VT15
SEL6
VC
C1
8G
110
G2
11
G3
14
G4
15
Q12
/Q9
VC
C2
13
NC7
PA
D17
U1
SY58017U
C141u
C351u
GS2970 Power Decoupling & Filtering
C341u
C3610n
R90R
R110R
R60R
C3810n
C1310n
R130R
C3310n
C1810n
C1710n
+3.3V_2974
C3710n
C1610n
VCC_1.2V
GND
GND
VCC_3.3V
C151u
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Figure 7-3: Equalizer A
EQA1_SDIn 2
EQA1_SDI 2
AIN21
AIN11
R2237R4
EQA2_SDIn 2
EQA2_SDI 2
R2175R
C691u
GNDA
SDI2
SDI3
VE
E4
VE
E1
AGC5
AGC6
BYPASS7
MCLADJ8
TA
BT
AB
VE
E9
SDO10
SDO11
VE
E12
VC
C13
MUTE14
CD15
VC
C16
U7GS2974B
GNDA
C74470n
EQ A2
CONTROL_26 CONTROL_26
C6310n
C6610n
EQUALIZER A
C2521u
C2531u
GNDA
C6210n
C591u
GNDA
R15 75R
L2 6n2
C60470n
C5410n
+3.3V_2974
C5510n
C58 4u7
C57 4u7
CD_1R1737R4
R1675R
C561u
GNDA
SDI2
SDI3
VE
E4
VE
E1
AGC5
AGC6
BYPASS7
MCLADJ8
TA
BT
AB
VE
E9
SDO10
SDO11
VE
E12
VC
C13
MUTE14
CD15
VC
C16
U6GS2974B
GNDA
C61470n
R180R
R190R
C651u
GNDA
EQ Power Decoupling & Filtering
C641u
VCC_3.3V +3.3V_2974
GND
EQ A1
GND
VCC_3.3V
C22110n
GNDCD_2
GND
CD_1
R130
DNP
Standby _SERACONTROL_26
R1310R
Standby _SERA
I11
GN
D2
I03
Z 4VC
C5
S6
U31
NC7SP157P6X
CD_2
GNDA
C7510n
C721u
GNDA
R20 75R
L3 6n2
C73470n
C6710n
+3.3V_2974
C6810n
C71 4u7
C70 4u7
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Figure 7-4: Deserializer A
DESA_STAT[4..0] 9
DESA_DATA[19..10] 9
SWA_SDIn2
SWA_SDI2 DESA_LPBCK 12
DESA_PCLK 9
DESA_LPBCKn 12
C76
22u
CONTROL_0
SDOUT_RXA5
CONTROL_1
SDOUT_RXAR36 22R
R29 10K
R38 22R1
2
Y1 CS10-27.000M
C80 16p
C79 16p
C8410n
CONTROL_3
GNDA
GNDA
Floating or +3.3V or GND
12. Impedance controlled signals(refer to PCB layout guide).
RESET
8. Lable the connectors, LEDs, DIP sw itches and jumpers. Lable some critical signals on the connectors;
R25 DNP
DESA_DATA18
CONTROL_4
R23105R
GNDA
DESA_DATA17
+1.2VA_2970
IOVDD_2970
4. SQT and TMM series connectors are rated for 3A from 20C-80C, w ith operation temp range of -65-+125C
RESET11
R24DNP
Close to GS2970A
DESA_DATA16DESA_DATA15
R39 22R
Close to GS2970A
SWA_SDI
RESET
VCC_1.2V
5. IOVDD_2970 can be +3.3v, w hich is supplied by this board through a 1-ohm jumper, or differentvoltage supplied by the output board connected to it, in w hich case the 1-ohm jumper shall be removed;
DESA_DATA14
10. Analog pow er and ground isolation(refer to PCB layout guide).
9. Minimum of 3x trace w idth spacing for GS2970_DOUT10~19, GS2970_PCLK;
SWA_SDIn
11. Critital 3G signal layout(refer to PCB layout guide);
GSPI3GSPI0GSPI1
SDOUT_RXA
+3.3VA_2970
DESA_DATA11
DESA_DATA13
DESA_DATA10
DESA_DATA12
DESA_LPBCKn
DESA_LPBCK
7. Use BNC ground as the ground test points;
+3.3VA_2970
GSPI[8:0]5,6,8,9,10
DESA_PCLKR35 22R
13. Via size test points should be as close as possible to the pins;
CONTROL_[4..0]
6. The value of the serial resistors on video output port w ill be determined by board signal integrity test;
Standby _SERA
DESA_STAT1 V ADESA_STAT0 H A
GND
DESA_STAT2 F A
GND
123456789
10111213141516
RN1 742C163220
C78 47n
+1.2VA_2970
R32 1.15K
R27 22R
LB_CONT Settings:
DESA_DATA19
3. Pow er consumption:2. DNP(Do Not Populate);
+1.2V217GS2970_1
+3.3V75
0
Notes:
Dev ice
0GS2978 51
C77 1u
65
217mA
1. This board is GS2960/1 compatible;
GS2974
Total 191mA
CONTROL_2
Close topin C1 & D1 of GS2970A
XTAL_OUT
Standby _SERA
R37 1.15K
DESA_STAT3 Lock A
DESA_STAT4
XTAL_OUT
DESA_AOUT_1/2
AUDIO_OUT1 1AUDIO_OUT1
XTAL_OUT
R26 0R
AUDIO_OUT2 1AUDIO_OUT2
IOVDD_2970
DESA_AOUT_3/4
GND
VBGA1
LFA2
LB_CONTA3
VC
O_V
DD
A4
STAT0A5STAT1A6STAT2B5
STAT3B6
STAT4C5
STAT5C6
IO_V
DD
1A
7
PCLKA8
DOUT0K8DOUT1J8
DOUT2K9DOUT3K10DOUT4J9DOUT5J10DOUT6H9DOUT7H10DOUT8F9DOUT9F10
DOUT10E9DOUT11E10
DOUT12C8DOUT13C10DOUT14C9DOUT15B10DOUT16B9DOUT17A10DOUT18A9DOUT19B8
A_V
DD
B1
PLL
_VD
D1
B2
RSV1B3
VC
O_G
ND
B4
IO_G
ND
1B
7
SDIC1
A_G
ND
1C
2
PLL
_VD
D2
C3
PLL
_VD
D3
C4
RESETC7
SDID1
A_G
ND
2D
2
A_G
ND
3D
3
PLL
_GN
D1
D4
CO
RE
_GN
D1
D5
CO
RE
_VD
D1
D6
SW_END7
JTAG/HOSTD8
IO_G
ND
2D
9
IO_V
DD
2D
10
SD
I_V
DD
E1
A_G
ND
4E
3
PLL
_GN
D2
E4
CO
RE
_GN
D2
E5
CO
RE
_VD
D2
E6
SDOUT_TDOE7
SDIN_TDIE8
TERMF1
RSV3F2
A_G
ND
5F
3
PLL
_GN
D3
F4
CO
RE
_GN
D3
F5
CO
RE
_VD
D3
F6
CS_TMSF7 SCLK_TCKF8
RSV4G1
RSV5G2
RC_BYPG3
RSV2G4
CO
RE
_GN
D4
G5
CO
RE
_VD
D4
G6
SMPTE_BYPASSG7
DVB_ASIG8
IO_G
ND
3G
9
IO_V
DD
3G
10
BU
F_V
DD
H1
BU
F_G
ND
H2
AUDIO_EN/DISH3
WCLKH4
TIM_861H5
XTAL_OUTH6
20BIT/10BITH7 IOPROC_EN/DISH8
SDOJ1
SDO_EN/DISJ2
AOUT_1/2J3
ACLKJ4
AOUT_5/6J5
XTAL2J6
IO_G
ND
4J7
SDOK1
STANDBYK2
AOUT_3/4K3
AMCLKK4
AOUT_7/8K5
XTAL1K6
IO_V
DD
4K
7
SD
I_G
ND
E2
U8
GS2970_1
RATE DET
R28 22R
Lock A Lock A 9
R33 0RR34 0R
RATE DET 12RATE DET
CONTROL_[4..0]
DESERIALIZER A
C820.1u
C81
0.1u
A3
B4
R5
GND
2
Vcc
1
110R
U10
SN65LVDT2
C850.1u
C83
0.1u
AES AUDIO OUT
AUDIO_OUT1
AUDIO_OUT2
A3
B4
R5
GND
2
Vcc
1
110R
U9
SN65LVDT2
GNDGND
GND
VCC_3.3V
GND GND
VCC_3.3V
GND
DESA_AOUT_3/4
DESA_AOUT_1/2
Standby _SERA
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Figure 7-5: Deserializer B
DESB_DATA[19..10] 9
DESB_PCLK 9
DESB_AUD[3..0] 9
Standby _SERB Standby _SERB Standby _SERB
XTAL_OUT4 XTAL_OUT
C8910n
GNDA
GNDA
Floating or +3.3V or GND
12. Impedance controlled signals(refer to PCB layout guide).
RESET
8. Lable the connectors, LEDs, DIP sw itches and jumpers. Lable some critical signals on the connectors;
R44 DNP
DESB_DATA18
R42105R
GNDA
DESB_DATA17
+1.2VA_2970
IOVDD_2970
GSPI[8..0]
4. SQT and TMM series connectors are rated for 3A from 20C-80C, w ith operation temp range of -65-+125C
R43DNP
Close to GS2970B
DESB_DATA16DESB_DATA15
Close to GS2970B
GSPI[8..0]
XTAL_OUT
SWB_SDI
DESB_ACLK DESB_AUD1DESB_WCLK DESB_AUD0
R61 22RR62 22R
VCC_1.2V
5. IOVDD_2970 can be +3.3v, w hich is supplied by this board through a 1-ohm jumper, or differentvoltage supplied by the output board connected to it, in w hich case the 1-ohm jumper shall be removed;
DESB_DATA14
10. Analog pow er and ground isolation(refer to PCB layout guide).
9. Minimum of 3x trace w idth spacing for GS2970_DOUT10~19, GS2970_PCLK;
DESB_DATA[19..10]
SWB_SDIn
11. Critital 3G signal layout(refer to PCB layout guide);
GSPI4GSPI0SDOUT_RXA
+3.3VA_2970
DESB_DATA11
DESB_DATA13
DESB_DATA10
DESB_DATA12
7. Use BNC ground as the ground test points;
+3.3VA_2970
DESB_PCLKR52 22R
13. Via size test points should be as close as possible to the pins;
DESB_AOUT3_4 DESB_AUD3DESB_AOUT1_2 DESB_AUD2
6. The value of the serial resistors on video output port w ill be determined by board signal integrity test;
GND
R4510K
123456789
10111213141516
RN2 742C163220
C88 47n
CONTROL_6
+1.2VA_2970
R48 22R
LB_CONT Settings:
DESB_DATA19
R49 22R
3. Pow er consumption:2. DNP(Do Not Populate);
+1.2V217GS2970_1
+3.3V75
0
Notes:
Dev ice
0GS2978 51
C87 1u
65
217mA
1. This board is GS2960/1 compatible;
GS2974
Total 191mA
Close topin C1 & D1 of GS2970B
DESERIALIZER B
R54 1.15K
C86
22u
CONTROL_5
CONTROL_7
CONTROL_[8..5]10
CONTROL_8
IOVDD_2970
GND
CONTROL_[8..5]
R51 1.15K
SDOUT_RXB
R53 22RR55 22RR56 22R
SDOUT_RXB SDOUT_RXB 6
RESET11RESET
DESB_STAT3 Lock B
VBGA1
LFA2
LB_CONTA3
VC
O_V
DD
A4
STAT0 A5STAT1A6STAT2B5
STAT3B6
STAT4C5
STAT5C6
IO_V
DD
1A
7
PCLKA8
DOUT0K8DOUT1J8
DOUT2K9DOUT3K10DOUT4J9DOUT5J10DOUT6H9DOUT7H10DOUT8F9DOUT9F10
DOUT10E9DOUT11E10
DOUT12 C8DOUT13C10DOUT14C9DOUT15 B10DOUT16B9DOUT17A10DOUT18A9DOUT19B8
A_V
DD
B1
PLL
_VD
D1
B2
RSV1B3
VC
O_G
ND
B4
IO_G
ND
1B
7
SDIC1
A_G
ND
1C
2
PLL
_VD
D2
C3
PLL
_VD
D3
C4
RESETC7
SDID1
A_G
ND
2D
2
A_G
ND
3D
3
PLL
_GN
D1
D4
CO
RE
_GN
D1
D5
CO
RE
_VD
D1
D6
SW_END7
JTAG/HOSTD8
IO_G
ND
2D
9
IO_V
DD
2D
10
SD
I_V
DD
E1
A_G
ND
4E
3
PLL
_GN
D2
E4
CO
RE
_GN
D2
E5
CO
RE
_VD
D2
E6
SDOUT_TDOE7
SDIN_TDIE8
TERMF1
RSV3F2
A_G
ND
5F
3
PLL
_GN
D3
F4
CO
RE
_GN
D3
F5
CO
RE
_VD
D3
F6
CS_TMSF7 SCLK_TCKF8
RSV4G1
RSV5G2
RC_BYPG3
RSV2G4
CO
RE
_GN
D4
G5
CO
RE
_VD
D4
G6
SMPTE_BYPASSG7
DVB_ASIG8
IO_G
ND
3G
9
IO_V
DD
3G
10
BU
F_V
DD
H1
BU
F_G
ND
H2
AUDIO_EN/DISH3
WCLKH4
TIM_861H5
XTAL_OUTH6
20BIT/10BITH7 IOPROC_EN/DISH8
SDOJ1
SDO_EN/DISJ2
AOUT_1/2J3
ACLKJ4
AOUT_5/6J5
XTAL2J6
IO_G
ND
4J7
SDOK1
STANDBYK2
AOUT_3/4K3
AMCLKK4
AOUT_7/8K5
XTAL1K6
IO_V
DD
4K
7
SD
I_G
ND
E2
U11
GS2970_1
GSPI0
DESB_STAT4
GSPI4R59 22R
SDOUT_RXA4 SDOUT_RXA
R60 22R
DESB_STAT[4..0] 9
DESB_STAT1 V BDESB_STAT0 H B
DESB_STAT2 F B
SWB_SDIn
SWB_SDI
SWB_SDIn2
SWB_SDI2
Lock B 9Lock B
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Figure 7-6: Serializer A
SERA_DIN[19..10]9
SERA_AUD[3..0]9
AOUTn 14
AOUT 1
SERA_HVF[2..0]9
C90
22u
SDOUT_RXB5
SERB_Locked
C9210n
C11010n
SERB Pins G1,H10
SERA_PCLK9
CONTROL_2
GND
SDOUT_RXB
C2181u
R80 75RSERB Pins A6,B6
10. Impedance controlled signals(refer to PCB layout guide).
R69150R
C121 4u7
R78 75R
IOVDD_2972
R75 75R
C12610n
C1081u
C113
10n
C101 1u
C114
10n
C1041u C99
10n
C97 10u
C9510n
R640R
SERB_Locked
C119 4u7
C12210n
R76750R
C12510n
C941u
C1071u
L5 5n6
C1241u
R810R
R77 75R
R700R
R66 200R
R790R
AOUT
C9310u
AOUTn
Return Loss compensation Network
R63105R
C1231u
SERA Pins A5,E1,K8,G10
C102 100p
SERA_SDI_SDOn
C10910n
SERA_SDI_SDO
VC
O_V
DD
B7
VBGA8
VC
O_G
ND
B8
TDIE7
RSV7A9
TIM_861G3
PCLKB4
IO_V
DD
1G
1
DIN18A2 DIN19B3
LFA7
AV
DD
A10
AG
ND
2B
10
DIN17A1
CO
RE
_VD
D3
K8
GRP1_EN/DISH6
DETECT_TRSF3
CO
RE
_GN
D5
E6
AG
ND
1B
9
DIN16B2
CO
RE
_VD
D4
G10
PLL
_VD
D1
A6
PLL
_VD
D2
B6
RSV1D5
STANDBYD3
ACLK1K7
WCLK1J7
AIN_1/2J6
DIN14C2 DIN15B1
CO
RE
_GN
D2
C5
CO
RE
_GN
D1
B5
RSV4D6
RSV5D7
DVB_ASIG5
LOCKEDH4
GRP2_EN/DISH5
AIN_3/4K6
DIN12C3 DIN13C1
RSV6D8
TMSE8TDOF8
RATE_SEL0E3
CO
RE
_GN
D4
E5
CO
RE
_VD
D2
E1
ACLK2K5
IO_V
DD
2H
10
DIN10D2 DIN11D1
RSV3F4
TCKJ8
CO
RE
_GN
D8
G9
20BIT/10BITG4
CO
RE
_GN
D6
F5
CO
RE
_VD
D1
A5
WCLK2J5
IO_G
ND
1G
2
DIN8F2 DIN9F1
RSV2F7
CD
_GN
D4
F9
CD
_GN
D3
E9
IOPROC_EN/DISG7
SMPTE_BYPASSG6
RESETG8
AIN_5/6J4
ANC_BLANKH3
DIN6H2 DIN7H1
CD
_GN
D2
D9
CO
RE
_GN
D3
E2
AUDIO_INTH7
CS_TMSK9
SCLK_TCKJ10
SDOUT_TDOJ9
AIN_7/8K4
H/HSYNCA4
DIN4J2 DIN5J1
CO
RE
_GN
D7
F6
PLL
_GN
D3
C8
PLL
_GN
D2
C7
PLL
_GN
D1
C6
SDO_EN/DISD4
SDIN_TDI K10
V/VSYNCC4
IO_G
ND
2H
9
DIN2K2 DIN3K1
RSETF10
CD
_VD
DE
10
SDOC10
SDOD10
CD
_GN
D1
C9
JTAG/HOSTH8
F/DEA3
RATE_SEL1E4
DIN0K3 DIN1J3
U15GS2972
C120 10n
C9810n
C10610n
C112
10n
C1031u
C111
10n
CONTROL_[27..0] 10
RESET11
GNDA
GSPI[8..0] 4,5,8,9,10GNDA
GNDA
GNDA
GNDA
GNDA
VCC_3.3V
VCC_3.3V
VCC_1.2V
VCC_1.2V
CDVDD_2972
+1.2VA_2972
IOVDD_2972
+1.2VA_2972
+1.2VA_2972 IOVDD_2972
CDVDD_2972
VCC_1.2V
GNDACDVDD_2972
GND
CDVDD_2972
GND
GND
GND
GND
GND
GND
GND
C10533p
GSPI[8..0]
Close toGS2972A
+3.3VA_2972
SERA_PCLK
R730R
R670R
SERB_Locked7
SERA_Locked
SERA_WCLK1SERA_AUD0SERA_ACLK1SERA_AUD1
SERA_AIN3_4SERA_AUD3SERA_AIN1_2SERA_AUD2
5. Use BNC ground as the ground test points;3. Pow er consumption:
2. DNP(Do Not Populate);
235mA
C2201u
GND
Close to GS2972A
+1.2V
SERA_VSERA_HVF1SERA_FSERA_HVF2
SERA_HSERA_HVF0
86+3.3V
RESET
SERA_DIN14SERA_DIN15SERA_DIN16
GS2972 Power Decoupling & Filtering
SERA_DIN19SERA_DIN18SERA_DIN17SERB Pin E10
SERA_DIN11SERA_DIN10
SERA_DIN12SERA_DIN13
GS2972Dev ice
6. Lable the connectors, LEDs, DIP sw itches and jumpers. Lable some critical signals of the connectors;
Notes:
0Others 3
CONTROL_15CONTROL_14
CONTROL_13
CONTROL_11CONTROL_12
CONTROL_16
0 5LEDs
11. Via size test point should be as close as possible to the pin;
SERA Pin A10
VCC_3.3V
1. This board is GS2962 compatible;
SERA Pins A6,B6
SDOUT_RXBGSPI0GSPI5
SDOUT_TXA
SERA Pin E10
235mATotal 94mA
7. Minimum of 3x trace w idth spacing for GS2972_DIN10~19, GS2972_PCLK;
4. IOVDD_2972 can be +3.3v, w hich is supplied by this board through a 1-ohm jumper, or differentvoltage supplied by the input board connected to it, in w hich case the 1-ohm jumper shall be removed;
8. Analog pow er and ground isolation(refer to PCB layout guide);
CONTROL_[27..0]
SERA_DIN[19..10]
9. Critital 3G signal layout(refer to PCB layout guide);
SERA Pins G1,H10 VCC_3.3VTx A Lock
A1 green1
A2 red2
K13
K24
U13
HSMF-C165GND
GND
R65
75R
GND
SERA_Locked
VCC_3.3VIOVDD_2972
VC
CA
1
VC
CB
10
A02
A13
TR04
TR16
GN
D5
OEb7
B09
B18
U12
FXL2TD245
GND
GSPI0
SERB Pins A5,E1,K8,G10
C2171u
75 OHM CONTROLLED IMPEDANCE
GSPI5
CONTROL_9
L4
BEAD_FERRITE_SM
C10010n
SERIALIZER A
SDOUT_TXA 7
+3.3VA_2972
75 OHMCONTROLLEDIMPEDANCE
SERB Pin A10
R12610K
C12710n
C12810n
C2191u
CONTROL_1
C117
10n
C116
10n
C118
10n
C115
10n GND
C9110n
L6 5n6
C9610n
VCC_3.3VTx B Lock
GND
R71
75RA1 green
1A2 red
2
K13
K24
U14
HSMF-C165
CONTROL_10
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Figure 7-7: Serializer B
SERB_LockedSERB_Locked 6
CONTROL_24
SERB_SDI_SDOn
BOUT
SERIALIZER B
R92
75R
75 OHM CONTROLLED IMPEDANCE
CONTROL_23CONTROL_22
CONTROL_20CONTROL_21
CONTROL_19
+3.3VA_2972
75 OHMCONTROLLEDIMPEDANCE
C129
22u
GNDA
CONTROL_6
R94105R
SERB_AIN_1/2
R12710K
R93105R
C131 1u
10. Impedance controlled signals(refer to PCB layout guide).
GND
SERB_AIN_3/4
Return Loss compensation Network
CONTROL_18
SERB_SDI_SDO
C134 4u7
CONTROL_[27..0]
Close toGS2972B
SERB_PCLK
SERB_Locked
3. Pow er consumption:
2. DNP(Do Not Populate);5. Use BNC ground as the ground test points;
235mA
GSPI[8..0] 4,5,8,9,10GSPI[8..0]
GSPI6GSPI0
GND
Close to GS2972B
+1.2V86+3.3V
RESET
SERB_DIN14
SERB_DIN16SERB_DIN15
SERB_DIN18SERB_DIN17
SERB_DIN19
SERB_DIN11SERB_DIN10
SERB_DIN13SERB_DIN12
GS2972Dev ice
6. Lable the connectors, LEDs, DIP sw itches and jumpers. Lable some critical signals of the connectors;
GND
SERB_AIN_3/4
C139
0.1u
VCC_3.3V
GNDC1400.1u
A3
B4
R5
GND
2
Vcc
1
110R
U18
SN65LVDT2
GND GND
Notes:
0 3Others50LEDs
11. Via size test point should be as close as possible to the pin;
SDOUT_TXB 8
1. This board is GS2962 compatible;
SDOUT_TXAGSPI0GSPI6
SDOUT_TXB
235mA 94mATotal
7. Minimum of 3x trace w idth spacing for GS2972_DIN10~19, GS2972_PCLK;
4. IOVDD_2972 can be +3.3v, w hich is supplied by this board through a 1-ohm jumper, or differentvoltage supplied by the input board connected to it, in w hich case the 1-ohm jumper shall be removed;
8. Analog pow er and ground isolation(refer to PCB layout guide);
SERB_DIN[19..10]
L7 5n6
9. Critital 3G signal layout(refer to PCB layout guide);
C132 100p
R82105R
R89750R
VC
O_V
DD
B7
VBGA8
VC
O_G
ND
B8
TDIE7
RSV7 A9
TIM_861G3
PCLKB4
IO_V
DD
1G
1
DIN18A2 DIN19B3
LFA7
AV
DD
A10
AG
ND
2B
10
DIN17A1
CO
RE
_VD
D3
K8
GRP1_EN/DISH6
DETECT_TRSF3
CO
RE
_GN
D5
E6
AG
ND
1B
9
DIN16B2
CO
RE
_VD
D4
G10
PLL
_VD
D1
A6
PLL
_VD
D2
B6
RSV1D5
STANDBYD3
ACLK1K7
WCLK1J7
AIN_1/2J6
DIN14C2 DIN15B1
CO
RE
_GN
D2
C5
CO
RE
_GN
D1
B5
RSV4 D6
RSV5D7
DVB_ASIG5
LOCKED H4
GRP2_EN/DISH5
AIN_3/4K6
DIN12C3 DIN13C1
RSV6D8
TMSE8TDOF8
RATE_SEL0E3
CO
RE
_GN
D4
E5
CO
RE
_VD
D2
E1
ACLK2K5
IO_V
DD
2H
10
DIN10D2 DIN11D1
RSV3F4
TCKJ8
CO
RE
_GN
D8
G9
20BIT/10BITG4
CO
RE
_GN
D6
F5
CO
RE
_VD
D1
A5
WCLK2J5
IO_G
ND
1G
2
DIN8F2 DIN9F1
RSV2F7
CD
_GN
D4
F9
CD
_GN
D3
E9
IOPROC_EN/DISG7
SMPTE_BYPASSG6
RESETG8
AIN_5/6J4
ANC_BLANKH3
DIN6H2 DIN7H1
CD
_GN
D2
D9
CO
RE
_GN
D3
E2
AUDIO_INTH7
CS_TMSK9
SCLK_TCKJ10
SDOUT_TDOJ9
AIN_7/8K4
H/HSYNCA4
DIN4J2 DIN5J1
CO
RE
_GN
D7
F6
PLL
_GN
D3
C8
PLL
_GN
D2
C7
PLL
_GN
D1
C6
SDO_EN/DISD4
SDIN_TDI K10
V/VSYNCC4
IO_G
ND
2H
9
DIN2K2 DIN3K1
RSETF10
CD
_VD
DE
10
SDOC10
SDOD10
CD
_GN
D1
C9
JTAG/HOSTH8
F/DEA3
RATE_SEL1E4
DIN0K3 DIN1J3
U16GS2972
SERB_AIN_1/2
SERB_AIN_3/4
R83 200R
C13333p
C130 10u
R86150R
R88 75R
AES_IN11
BOUT 1
AES_IN21
SERB_DIN[19..10]9
SERB_PCLK9
RESET11
GNDA
CONTROL_[27..0] 10
+1.2VA_2972
GNDA
GNDA
IOVDD_2972
+1.2VA_2972
CDVDD_2972
VCC_1.2V
GND
CDVDD_2972
GND
GND
GND
IOVDD_2972
SDOUT_TXA 6
C138 4u7
R90 75R
R91 75R
C136 10nGNDA
CDVDD_2972
75 OHM CONTROLLED IMPEDANCE
CONTROL_17
GND
C135
0.1uC1370.1u
VCC_3.3V
GND
A3
B4
R5
GND
2
Vcc
1
110R
U17
SN65LVDT2
SERB_AIN_1/2
GND GND
3Gb/s SDI Demo Board: Xilinx VersionUser Guide52857 - 1 August 2009
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Proprietary & Confidential
Figure 7-8: External Sync
PCLK4911 9
TIMING[2..0] 9
EXT_SYNC1
RE
SE
T
1V8_GS4911
VDD_XTAL_GS4911
12
Y2
CS10-27.000M
C171
24p
R10210K
C170
38p
IO_V_GS4911
LOCK_LOSTREF_LOST
R1001M
GND
VCC_3.3VIO_V_GS4911
GND
GND
VC
CA
1
VC
CB
10
A02
A13
TR04
TR16
GN
D5
OEb7
B09
B18
U21
FXL2TD245
GND
VCC_3.3V
GND
A1 green1
A2 red2
K13
K24
U23
HSMF-C165
REF_LOST
VCC_3.3V
A1 green1
A2 red2
K13
K24
U22
HSMF-C165LOCK_LOST
R107
75R
R108
75R
PCLK4911SDOUT_TXB7
TP6
SDOUT_TXB
XTAL1
VBLANK2
SYNCLOCK3
PWDN4
SDENB5
SCL6
SDA7
GN
DD
18
HIN9
SYNCIN10
VERTIN11
LEVEL12
GN
DA
113
VC
CA
114
VC
CA
215
GN
DA
216
GN
DD
217
VC
CD
118
SYNCOUT19
BACKPORCH20
HOUT21
VERTOUT22
ODD/EVEN23
XTALN24
U20
EL4511CUZ
C1730.1u
VCC_3.3VVCC_3.3V
C1720.1u
R101 10K
C175(NP)
R106 22RR105 22R
ACLK1
R104 22R
GSPI2
IO_V
_GS
4911
ACLK1
GSPI7
CONTROL_25
EXTERNAL SYNC.
RESET11
GS4911_H
RESET
R149DNP
GS4911_F
R150200R
GS4911_V
GS4911_V
GS4911_F
GS4911_H
CONTROL_2510
TIMING[2..0]
C174
0.1u
VID_PLL_GND4 VID_PLL_VDD3
XTAL_VDD5
X16
X27
XTAL_GND8
CORE_GND9
PH
S_G
ND
55
PH
S_V
DD
54
ANALOG_VDD10
NC111
ANALOG_GND12
AUD_PLL_GND13
AUD_PLL_VDD14
10FID15
HSYNC16
VS
YN
C17
IO_V
DD
18
FS
YN
C19
NC
220
VID
_ST
D0
21
VID
_ST
D1
22
VID
_ST
D2
23
VID
_ST
D3
24
VID
_ST
D4
25
VID
_ST
D5
27
AC
LK1
28
AC
LK2
29
AC
LK3
30
IO_V
DD
31
CO
RE
_VD
D26
AS
R_S
EL2
32
ASR_SEL133ASR_SEL0 34TIMING_OUT135TIMING_OUT236
IO_VDD38TIMING_OUT439
TIMING_OUT3 37
TIMING_OUT540
LVDS/PCLK3_VDD45PCLK346
LVDS/PCLK3_GND48
PCLK347
PC
LK2
49
PC
LK1&
2_G
ND
52
PC
LK1
51
IO_V
DD
50
TIMING_OUT641TIMING_OUT742TIMING_OUT843
PC
LK1&
2_V
DD
53
LOCK_LOST1
REF_LOST2
GE
NLO
CK
64
CORE_VDD44
JTA
G/H
OS
T56
SC
LK_T
CLK
57S
DIN
_TD
I58
SD
OU
T_T
DO
59C
S_T
MS
60R
ES
ET
61IO
_VD
D62
NC
363
GND_PAD65
U19
GS4911
GND
GND
R1030R
TIMING0
IO_V_GS4911
TIMING1
LOCK_LOST
C15410n
C14510n
C14910n
C14810n
C14710n
C15010n
DECOUPLING@ PIN 5
GND
1V8_Core_GS4911VCC_1.8V
C15610uC166
10u
R990R C167
0.1uC1650.1u
C16910n
REF_LOST
C16810n
IO_V_GS4911
GND
CONTROL_25
C1570.1u
DECOUPLING @ PINS18,31,38,50,62
C1600.1u
R980R C161
10nC16410n
C16310n
C16210n
TIMING2
C15510n
VCC_3.3V
C15810u
C15910u
DECOUPLING @PINS 26,44
GND
VDD_XTAL_GS4911VCC_3.3V
C15310u
C15210u
R960R
C1510.1u
GS4911 decoupling
GND
1V8_GS4911VCC_1.8V
C14310uC142
10u
GSPI0
R950R C144
0.1uC1410.1u
GS
PI7
C14610n
DECOUPLING @ PINS 3,10,14,45,53,54GSPI[8..0]
GSPI[8..0]4,5,6,9,10
GS
PI2
TP5
SD
OU
T_T
XB
1V8_Core_GS4911
GS
PI0
GND
GND
GND
R9710K
V_Sy ncH_Sy nc
GND
PC
LK49
11
IO_V
_GS
4911
IO_V_GS4911
1V8_GS4911
1V8_GS4911
1V8_GS4911
1V8_
Cor
e_G
S49
11
F_Sy nc
1V8_
GS
4911
1V8_
GS
4911
IO_V
_GS
4911
V_STD_Sel
IO_V
_GS
4911
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Figure 7-9: FPGA Interface
Figure 7-10: SPI I/O Expander
AC6
+2.5V RAW
DESB_AUD[3..0]
DESA_DATA[19..10]
GSPI_Dongle[0:3]
DESA_DATA[19..10]4
DESA_PCLK4
DESA_STAT[4..0]2,4
GND
DESB_AUD[3..0]5
DESB_PCLK5
DESB_STAT[4..0]2,5
DESB_DATA[19..10]5
SERA_AUD[3..0] 6
SERA_PCLK 6
SERA_HVF[2..0] 6
SERA_DIN[19..10] 6
PCLK49118
TIMING[2..0]8
SERB_PCLK 7
SERB_DIN[19..10] 7
GSPI0GSPI[8..0]4,5,6,8,10
DESA_STAT0
SERB_DIN19
SERA_AUD[3..0]
SERA_DIN15
EXP CONNECTOR
SERA_DIN14
DESA_DATA11
AC19
GND
DESB_STAT3
AD19
DESA_STAT0
AC9
SERA_DIN18
AD6
TIMING[2..0]
SERA_DIN14
DESB_AUD2
GSPI_Dongle0
GSPI1
AB18
DESB_DATA12
R20*
SERB_DIN18
Y10
AC8
SERA_AUD2
DESA_STAT1 DESB_DATA10
DESA_DATA10
GSPI8
AF13
V15
SERA_DIN13
GSPI2
SERA_DIN16
DESB_DATA18
SERB_DIN11
AA10
AB7
DESB_AUD3
SERB_DIN17
DESA_STAT2
R19*
GSPI_Dongle1
DESA_DATA17
W15
DESB_DATA17
SCLK_FPGA
GSPI4
GSPI3
SERA_DIN12
DESA_STAT1
W9
AE4
DESA_STAT3
DESB_AUD0
SERA_AUD0
DESB_PCLKY14
SERB_DIN16
SERA_DIN19
AB16
SERB_DIN12
DESB_DATA16
Y9
AF4
GSPI4
SERA_DIN11
DESB_AUD3
GSPI_Dongle2
SERA_AUD3
AD14
DESB_DATA15
DESA_STAT2DESB_AUD0
DESA_DATA19
*M21
TIMING0
SERA_AUD1DESB_STAT2
DESB_DATA15
SERB_DIN15
DESB_STAT0
V11
AE3
DESB_DATA19
DESA_PCLK
GSPI5
AC14
SERA_DIN10
SERA_DIN12
SERB_DIN13
AC16
DESA_DATA18
GSPI_Dongle3
DESB_DATA14
U11
+3.3V RAW
AF3
DESA_DATA15
DESA_STAT3
SERA_PCLK
SERA_AUD2
SERA_DIN18
TIMING1
SERB_DIN14
GSPI6
DESB_STAT1
K23*
RESET
*U22
* indicates that this signal is routedthrough a FET switch (U5) on the Xilinxboard; only STAT signals allowed on pinsmarked with a *.
DESA_DATA17
DESB_DATA18
DESB_DATA13
AF5
SERA_DIN[19..10]
SERA_DIN11
SERA_DIN17
M22*
GND
TIMING2
DESB_STAT2 SERA_AUD3
SERB_PCLK
SERB_DIN14
SERB_DIN13
DESA_STAT4AC15
DESA_DATA16
GSPI7
DESB_DATA12
AE6
GSPI2
SERB_PCLK
V13
AB12
ACLK1
DESB_STAT3
SERA_DIN16
DESA_DATA15
AA13
DESB_DATA17
SERB_DIN12
AE25
DESB_DATA11
GSPI6
SERA_DIN10
SERA_HVF[2..0]
W13
SERB_DIN15
AC12
ACLK1
GSPI0
Y13
DESB_STAT4
DESA_DATA14
DESB_STAT0
AF25
DESB_DATA[19..10]
DESB_DATA10
CS1 = DESBCS0 = DESA
SERB_DIN11
GSPI7
Y12
AE17
DESA_DATA13
V14
RESET 8RESET
DESA_DATA16AE23
CS2 = SERA
SERA_PCLK
DESB_PCLK
SERB_DIN16
ACLK1
DESA_STAT4
AA12
AD17
DESA_DATA12
GSPI1
GSPI8
AF23
SERA_HVF1
GSPI[8..0]
U15
CS3 = SERB
SERB_DIN10
PCLK4911
DESA_DATA19
GND
CS4 = GS4911
DESA_DATA11
AD22
W17
AF20
DESB_DATA14
SERB_DIN[19..10]
DESB_AUD2
SERA_DIN17
CS5 = IO EXP
DESB_STAT1
SERB_DIN17
SERA_HVF0
DESA_PCLK
AE21
DESA_DATA10
V17
GSPI3AE20
V10
DESA_DATA18
PCLK4911
AD21
SERA_HVF0
DESA_DATA14
V12
AE9
W10
SERA_HVF2
AC21
AF9
DESB_DATA16
DESA_STAT[4..0]
W12
DESB_DATA13
TIMING0
SERA_AUD1
V16
SERA_HVF1
SERB_DIN19
U23*
DESA_DATA13
AE8
DESB_STAT4
AD11
Y17
SERA_HVF2
U24*
AC11
AF8
GND
TIMING1
SERA_DIN13
SERB_DIN18
AA18
R148 22R
DESA_DATA12
AD20SERA_DIN19
AF14
AD7
SERA_AUD0
AC20
GSPI5
DESB_DATA19
AF19
TIMING2
AE14
AE7
GSPI_Dongle[0:3]1
DESB_STAT[4..0]
GND
SERA_DIN15
DESB_AUD1
SERB_DIN10
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4242
4444
4646
4848
5050
5252
5454
5656
5858
6060
6262
6464
6666
6868
7070
7272
7474
7676
7878
8080
8282
8484
8686
8888
9090
9292
9494
9696
9898
100100
102102
104104
106106
108108
110110
112112
114114
116116
118118
120120
11
33
55
77
99
1111
1313
15 15
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
45 45
4747
4949
51 51
5353
5555
5757
5959
6161
6363
6565
6767
6969
7171
7373
7575
7777
7979
8181
8383
8585
87 87
8989
9191
9393
9595
9797
9999
101101
103103
105105
107107
109109
111111
113113
115115
117117
119119
122122
124124
126126
128128
130130
132132
121121
123123
125125
127127
129129
131131
JX1
QSE-060-01-L-D-A
AA17
AE19
+2.5V RAW
GSPI_Dongle0
GSPI_Dongle2GSPI_Dongle1 +3.3V RAW
DESB_DATA11
DESB_AUD1
AB9
GSPI_Dongle3
CONTROL_[27..0] 2,4,5,6,7,8
GSPI[8..0]4,5,6,8,9
CONTROL_21
CONTROL_4CONTROL_4 DESA_SW_EN
CONTROL_22
CONTROL_26SOURCE A
CONTROL_5CONTROL_5 DESB_TIM861R109
39k
CONTROL_23
CONTROL_27SOURCE B
CONTROL_6CONTROL_6 B_SMPTE_BYPASSn
CONTROL_24
CONTROL_7CONTROL_7 DESB_IO_PROC_EN/DISb
CONTROL_25CONTROL_26
CONTROL_8CONTROL_8 DESB_SW_EN
CONTROL_27
GSPI8
CONTROL_9CONTROL_9 SERA_TIM861CONTROL_10CONTROL_10 SERA_STDBY
Control Register Address:Control_0: 24
CONTROL_11CONTROL_11 SERA_RATE_SEL0 Control_1: 25
R151DNP
R152200R
Control_3: 27Control_2: 26CONTROL_12CONTROL_12 SERA_RATE_SEL1
VCC_3.3V
Control_7: 2BControl_6: 2AControl_5: 29Control_4: 28
Control_8: 2C
Control_11: 2FControl_10: 2EControl_9: 2D
Control_14: 32Control_13: 31Control_12: 30
Control_15: 33
CONTROL_13CONTROL_13 SERA_IO_PROCE_EN/DISb
Control_19: 37Control_18: 36Control_17: 35Control_16: 34
V+35
GND238 GND137
ISET36
DIN33
CSn34
SCLK32
DOUT40
P3129
P3027
P2925
P2823
P2722
P2621
P2519
P2418
P430
P528
P626
P724
P81
P93
P105
P117
P122
P134
P14 6
P158
P169
P1710
P1812
P1913
P2014
P2115
P2216
P2317
GND339
N.C131
N.C220
N.C311
TA
BT
AB
U24
MAX7301ATL+
Control_21: 39Control_20: 38
Control_23: 3BControl_22: 3A
CONTROL_[27..0]
CONTROL_14CONTROL_14 SERA_DETECT_TRS
VCC_3.3V
C1761u
CONTROL_15CONTROL_15 SERA_ANC_BLANKb
GSPI1
CONTROL_16CONTROL_16 SERA_GRP1_EN_DISb
Control_25: 3DControl_24: 3C
Control_27: 3FControl_26: 3E
GSPI0GSPI1
DESA_TIM861
CONTROL_17CONTROL_17 SERB_TIM861
A_SMPTE_BYPASSnA_DVBASIDESA_IO_PROC_EN/DISbDESA_SW_ENDESB_TIM861B_SMPTE_BYPASSnDESB_IO_PROC_EN/DISbDESB_SW_ENSERA_TIM861SERA_STDBYSERA_RATE_SEL0SERA_RATE_SEL1
CONTROL_0CONTROL_0 DESA_TIM861
SERA_IO_PROCE_EN/DISb
CONTROL_18CONTROL_18 SERB_STDBY
SERA_DETECT_TRSSERA_ANC_BLANKbSERA_GRP1_EN_DISbSERB_TIM861SERB_STDBYSERB_RATE_SEL0SERB_RATE_SEL1SERB_IO_PROCE_EN/DISb
C17747n
GSPI8
CONTROL_19CONTROL_19 SERB_RATE_SEL0
CONTROL_20SERB_RATE_SEL1
SERB_DETECT_TRSSERB_ANC_BLANKbSERB_GRP1_EN_DISb
CONTROL_21SERB_IO_PROCE_EN/DISb
4911 GenlockSOURCE ASOURCE B
GSPI[8..0]
CONTROL_22SERB_DETECT_TRS
SPI I/O EXPANDER
CONTROL_23SERB_ANC_BLANKb
CONTROL_1CONTROL_1 A_SMPTE_BYPASSn
CONTROL_24SERB_GRP1_EN_DISb
CONTROL_20
CONTROL_254911 Genlock
CONTROL_2CONTROL_2 A_DVBASI
GSPI0
CONTROL_3CONTROL_3 DESA_IO_PROC_EN/DISb
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Figure 7-11: Power
Figure 7-12: Cable Driver
POWER
C1880.1u C223
0.1u
C189
4u7
Heat sinkon copper
500mA+2.5V RAW
GND
VCC_1.8VTP8
+1.8V
GND
TP7+1.2V
1500mA
Heat sinkon copper
+2.5V RAW
Debuggingpower supply
C187
1u
1
2
3JP1
RESET
R1125k1
GND
+2.5V RAW
L8 BEAD_FERRITE_SM
RESET 4,5,6,7,8
L9
BEAD_FERRITE_SM
PWR
R110
240R
GND
D1
LNJ311G8PRA
C18022u
C178
22u
C1790.1u
C1811u
+3.3V RAW TP9 VCC_3.3V
GND
+3.3V
+2.5V RAW
VCC_3.3V
C2431u
C2761uC244
10u
C24210u
C24510n
C182470u
R1431.15K
R142576R
IN15
IN26
IN37
IN48
BIAS10
PG9
OUT11
OUT418OUT319OUT220
NC617
FB16EN
11
SS15
GN
D12
NC
413
NC
514
NC
12
NC
23
NC
34
Pad
21
U25
TPS74201_RGW
GND
GNDGND
VCC_3.3V
VCC_1.2V
VIN1
EN3 VOUT5
BYP4
GN
D2
U26MIC5319-1.8YD5 TR
RATE DET4
SDI1
SDI2
NC
15
GN
D3
DISABLE6
NC
414
SD/HD10
TA
B17
NC
28
SDO11
SDO12
NC
515
NC
313
NC7
RSET4 V
CC
9
NC
616
U28GS2978
R1210R
R116 75R
R11575R
R117 75RR11849R9
C1971u
R11949R9
C1981u
C19210n
R113750R
C193 4u7
C19610n
L10 5n6
C19510n
C19110n
C194 4u7
R11475R
R1200R
C19910n
DESA_LPBCK4
ALPBCK 1DESA_LPBCKn4
GNDA_CD
+3.3V_2978
+3.3V_2978
GNDA_CD
GNDA_CDGNDA_CD
+3.3V_2978
GND
VCC_3.3V
GNDA_CD
GNDA_CD
C28010n
75-ohm traces
CABLE DRIVER ONVIDEO CHANNEL ALOOP-THROUGH
CD Power Decoupling & Filtering
GNDA_CD
50-ohm traces
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Proprietary & Confidential
Figure 7-13: Equalizer B
Figure 7-14: Optical Transceiver
R12375R
C204 4u7
R12437R4
C20010n
SDI2
SDI3
VE
E4
VE
E1
AGC5
AGC6
BYPASS7
MCLADJ8
TA
BT
AB
VE
E9
SDO10
SDO11
VE
E12
VC
C13
MUTE14
CD15
VC
C16
U29GS2974B
L11 6n2
CD_3
R122 75R
C2021u
C2051u
C20810n
EQ B1
C20110n
C207470n
C203 4u7
C206470n
BIN11
EQB1_SDIn 2
EQB1_SDI 2
CONTROL_27
+3.3V_2974
GNDA
GNDA
GNDA
GNDA
C2541u
EQUALIZER B
Standby _SERB
Standby _SERB
C22210n
GND
VCC_3.3V
GND
GND
CD_3
CONTROL_27R132
0RR133DNP
I11
GN
D2
I03
Z4V
CC
5
S6
U32
NC7SP157P6X
C2100.1u
R12549R9
C2120.1u
C2160.1u
L13
1uH
C2140.1u
VEE11
TX_FAULT2
NC13
VEE24
I2C_CLK5
I2C_DATA6
VEE37
RX_LOS8
NC29
NC310 VEE4 11RD-12RD+13VEE5 14VCC_RX15VCC_TX16VEE617TD+18TD-19TX_DIS20
M1
21
M2
22
M3
23
M4
24
M5
25
M6
26
M7
27
M8
28
M9
29
M10
30
M11
31
U30
GO2921
L12
1uH
OPT_TD+ 6
OPT_RD- 2
OPT_RD+ 2
VCC_3.3V
VCC_3.3V
R13475R
Remove this resistor when theoptical module is installed.
GNDA
GNDA
GNDA
C20910u
GNDA
C21110u
GNDA
GNDA
GNDA
U33 U34
C21310u
C21510u
OPTICAL TRANSCEIVER
12
JP4
GND
EN_Transceiver
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Proprietary & Confidential
7.2 Board LayoutThe 3Gb/s SDI Demo Board is a 8-layer board with controlled impedance requirement. The layers are Top, Gnd1, Pwr1, Pwr2, Gnd2, Sig1, Gnd3 and Bottom. Figure 7-15 and Figure 7-16 show the Top and Bottom layers of the board. The Allegro brd file and Gerber files are provided as part of the kit where the details of all layers may be viewed.
Figure 7-15: Top Layer
3Gb/s SDI Demo Board: Xilinx VersionUser Guide52857 - 1 August 2009
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Figure 7-16: Bottom Layer
3Gb/s SDI Demo Board: Xilinx VersionUser Guide52857 - 1 August 2009
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7.3 Bill of MaterialsTable 7-1 lists all of the parts used on the 3Gb/s SDI Demo Board. For additional information of the parts, such as manufacturer and part numbers, please refer to the Excel spread sheet provided with the kit.
Table 7-1: Bill of Materials
Quantity Reference Designator Description
30 C1, C3, C5, C7, C13, C23, C33, C54, C55, C62, C63, C66, C67, C68, C75, C84, C89, C98, C106, C122, C191, C192, C196, C199, C200, C201, C208, C221, C222, C245
Capacitor; ceramic 10000pF 16V 10% X7R 0402
22 C2, C6, C81, C83, C135, C139, C141, C144, C151, C157, C160, C165, C167, C172, C173, C179, C188, C210, C212, C214, C216, C223
Capacitor; ceramic 0.10μF 10V X7R 0402
10 C9, C10, C11, C12, C57, C58, C70, C71, C203, C204 Capacitor; ceramic 4.7μF 6.3V X5R 0402
30 C14, C24, C34, C64, C65, C77, C87, C94, C101, C103, C104, C107, C108, C123, C124, C131, C176, C181, C187, C197, C198, C217, C218, C219, C220, C243, C252, C253, C254, C276
Capacitor; ceramic 1μF 10V X5R 0402
4 C15, C19, C35, C39 Capacitor; ceramic 1μF 10V X5R 0402
62 C16, C17, C18, C20, C21, C22, C25, C26, C27, C28, C29, C30, C31, C32, C36, C37, C38, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C91, C92, C95, C96, C99, C100, C109, C110, C111, C112, C113, C114, C115, C116, C117, C118, C125, C126, C127, C128, C145, C146, C147, C148, C149, C150, C154, C155, C161, C162, C163, C164, C168, C169
Capacitor; ceramic 10000pF 16V 10% X7R 0402
6 C56, C59, C69, C72, C202, C205 Capacitor; ceramic 1μF 10V X5R 0402
6 C60, C61, C73, C74, C206, C207 Capacitor; ceramic 0.47μF 6.3V X5R 0402
6 C76, C86, C90, C129, C178, C180 Capacitor; ceramic 22μF 10V X5R 0805
3 C78, C88, C177 Capacitor; ceramic 47000pF 10V 10% X7R 0402
2 C79, C80 Capacitor; ceramic 16pF 50V S 0402 UHI Q
2 C82, C85 Capacitor; ceramic 0.10μF 10V X7R 0402
15 C93, C97, C130, C142, C143, C152, C153, C156, C158, C159, C166, C209, C211, C213, C215
Capacitor; ceramic 10μF 6.3V X5R 0603
2 C102, C132 Capacitor; ceramic 100pF 25V NP0 0402
2 C105, C133 Capacitor; ceramic 33pF 50V 5% C0G 0402
6 C119, C121, C134, C138, C193, C194 Capacitor; ceramic 4.7μF 6.3V X5R 0402
2 C120, C136 Capacitor; ceramic 10000pF 16V 10% X7R 0402
3 C137, C140, C174 Capacitor; ceramic 0.10μF 10V X7R 0402
1 C170 Capacitor; ceramic 39pF 50V 5% C0G 0402
1 C171 Capacitor; ceramic 24pF 50V C0G 0402
1 C182 Capacitor; tantalum 470μF 10V 10% LOESR SMD
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1 C189 Capacitor; ceramic 4.7μF 6.3V X5R 0402
2 C195,C280 Capacitor; ceramic 10000pF 16V 10% X7R 0402
2 C242, C244 Capacitor; ceramic 10μF 6.3V X5R 0603
1 D1 LED; pure green face up 1206
1 JX1 Connector, receptacle; hi-speed dual 120-position
5 J1, J2, J10, J11, J12 Connector, 75Ω BNC; front chassis-mount right-angle
6 J3, J4, J5, J6, J8, J9 Connector; RF/Coaxial
1 J7 Connector, header; 10-position 0.100" DL gold
3 J13, J14, JP4 Connector, header; 0.100 single STR 36-position
3 L2, L3, L11 Inductor; 6.2nH 300mA 0402
3 L4, L8, L9 Filter Chip; 120Ω 3A 0603
4 L5, L6, L7, L10 Inductor; 5.6nH 300mA 0402
2 L12, L13 Inductor; 1.0μH 20% 445mA 1210
2 RN1, RN2 Resistor, array; 22Ω 16-term 8RES SMD
12 R1, R2, R3, R12, R29, R45, R97, R101, R102, R126, R127, R128 Resistor; 10kΩ 1/16W 5% 0402 SMD
7 R4, R5, R32, R37, R51, R54, R143 Resistor; 1.15kΩ 1/16W 1% 0402 SM
19 R6, R7, R9, R11, R13, R18, R19, R64, R67, R70, R73, R79, R81, R95, R96, R98, R99, R120, R121
Resistor; 0Ω 1/10W 5% 0402 SMD
8 R8, R10, R65, R71, R107, R108, R116, R146 Resistor; 75.0Ω 1/16W 1% 0402 SMD
2 R14, R129 Resistor; 13.7kΩ 1/16W 1% 0402 SMD
18 R15, R16, R20, R21, R75, R77, R78, R80, R88, R90, R91, R92, R114, R115, R117, R122, R123, R134
Resistor; 75.0Ω 1/16W 1% 0402 SMD
3 R17, R22, R124 Resistor; 37.4Ω 1/16W 1% 0402 SMD
4 R23, R42, R63, R82 Resistor; 105Ω 1/10W 1% 0603 SMD
5 R26, R33, R34, R131, R132 Resistor; 0Ω 1/10W 5% 0402 SMD
20 R27, R28, R35, R36, R38, R39, R48, R49, R52, R53, R55, R56, R59, R60, R61, R62, R104, R105, R106, R148
Resistor; 22.0Ω 1/16W 1% 0402 SMD
3 R66, R83, R150 Resistor; 200Ω 1/16W 1% 0402 SMD
2 R69, R86 Resistor; 150Ω 1/16W 1% 0402 SMD
3 R76, R89, R113 Resistor; 750Ω 1/16W 1% 0402 SMD
2 R93, R94 Resistor; 105Ω 1/10W 1% 0603 SMD
1 R100 Resistor; 1.00MΩ 1/16W 1% 0402 SMD
1 R103 Resistor; 0Ω 1/10W 5% 0402 SMD
Table 7-1: Bill of Materials
Quantity Reference Designator Description
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1 R109 Resistor; 39kΩ 1/16W 5% 0402 SMD
1 R110 Resistor; 240Ω 1/16W 1% 0402 SMD
3 R118, R119, R125 Resistor; 49.9Ω 1/16W 1% 0402 SMD
1 R142 Resistor; 576Ω 1/16W 1% 0402 SMD
1 R152 Resistor; 200Ω 1/16W 1% 0402 SMD
1 R112 Resistor; 5.1kΩ 1/16W 1% 0402 SMD
2 U1, U2 IC; MUX 2:1 DIFF PREC HS 16-MLF
3 U3, U12, U21 Translator; 2-bit LV DL 10MICROPAK
4 U4, U5, U22, U23 Agilent HSMF-C165 Miniature Bi-colour Surface Mount Chip LED
3 U6, U7, U29 Gennum GS2974B Adaptive Cable Equalizer
2 U8, U11 Gennum GS2970 3G/HD/SD-SDI Deserializer
5 U9, U10, U17, U18 IC; diff line DVR/RCVR HS SOT23-5
2 U13, U14 Agilent HSMF-C165 Miniature Bi-colour Surface Mount Chip LED
2 U15, U16 Gennum GS2972 3G/HD/SD-SDI Serializer
1 U19 Gennum GS4911B Clock and Timing Generator
1 U20 IC; VID Sync Separator HDTV 24QSOP
1 U24 IC; I/O Port Expander 40-TQFN
1 U25 IC; LDO REG 1.5A w/PROG SS 20QFN
1 U26 IC; REG LDO 500mA 1.8V TSOT23-5
1 U28 Gennum GS2978 Cable Driver
1 U30 Connector and Cage for Gennum SFP Optical Module
2 U31, U32 IC; MUX ULP 2-INP NONINV SC70-5
2 Y1, Y2 Crystal; 27.0000 MHz 18pF SMD
Table 7-1: Bill of Materials
Quantity Reference Designator Description
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OTTAWA232 Herzberg Road, Suite 101 Kanata, Ontario K2K 2A1 Canada
Phone: +1 (613) 270-0458
Fax: +1 (613) 270-0429
CALGARY3553 - 31st St. N.W., Suite 210 Calgary, Alberta T2L 2K7 Canada
Phone: +1 (403) 284-2672
UNITED KINGDOMNorth Building, Walden Court Parsonage Lane, Bishop’s Stortford Hertfordshire, CM23 5DB United Kingdom
Phone: +44 1279 714170
Fax: +44 1279 714171
INDIA#208(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar 751009 India
Phone: +91 (674) 653-4815
Fax: +91 (674) 259-5733
SNOWBUSH IP - A DIVISION OF GENNUM439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada
Phone: +1 (416) 925-5643
Fax: +1 (416) 925-0581
E-mail: [email protected]
Web Site: http://www.snowbush.com
MEXICO288-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 20900
Phone: +1 (416) 848-0328
JAPAN KKShinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo, 160-0023 Japan
Phone: +81 (03) 3349-5501
Fax: +81 (03) 3349-5505
E-mail: [email protected]
Web Site: http://www.gennum.co.jp
TAIWAN6F-4, No.51, Sec.2, Keelung Rd. Sinyi District, Taipei City 11502 Taiwan R.O.C.
Phone: (886) 2-8732-8879
Fax: (886) 2-8732-8870
E-mail: [email protected]
GERMANYHainbuchenstraße 2 80935 Muenchen (Munich), Germany
Phone: +49-89-35831696
Fax: +49-89-35804653
E-mail: [email protected]
NORTH AMERICA WESTERN REGIONBayshore Plaza 2107 N 1st Street, Suite #300 San Jose, CA 95131 United States
Phone: +1 (408) 392-9454
Fax: +1 (408) 392-9427
E-mail: [email protected]
NORTH AMERICA EASTERN REGION4281 Harvester Road Burlington, Ontario L7L 5M4 Canada
Phone: +1 (905) 632-2996
Fax: +1 (905) 632-2055
E-mail: [email protected]
KOREA8F Jinnex Lakeview Bldg. 65-2, Bangidong, Songpagu Seoul, Korea 138-828
Phone: +82-2-414-2991
Fax: +82-2-414-2998
E-mail: [email protected]
DOCUMENT IDENTIFICATIONUSER GUIDEInformation relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Gennum assumes no liability for any errors in this document, or for the application or design described herein. Gennum reserves the right to make changes to the product or this document at any time without notice.
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Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.
All other trademarks mentioned are the properties of their respective owners.
GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.
© Copyright 2009 Gennum Corporation. All rights reserved.
www.gennum.com
GENNUM CORPORATE HEADQUARTERS4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada
Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055
E-mail: [email protected] www.gennum.com
CAUTIONELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION