45nm high-k + metal gate strain-enhanced transistors · 40 conclusions • high-k + metal gate...
TRANSCRIPT
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45nm High-k + Metal Gate Strain-Enhanced Transistors
C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi,
J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren%, V. Souw, K. Tone,
F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, C. Wiegand
Portland Technology Development, %PTMIntel Corporation
2
Outline
• Introduction• Metal-Gate + Strain Integration• Transistor/Circuit Results• Manufacturing• Conclusions
3
Introduction• SiON scaling running out of atoms• Poly depletion limits inversion TOX scaling
– > Need High-K + Metal Gate
Silicon
PolySiON
1
10
350nm 250nm 180nm 130nm 90nm 65nm
Elec
tric
al (I
nv) T
ox(n
m)
0.01
0.1
1
10
100
1000
Gat
e Le
akag
e (R
el.)
4
High-k + Metal Gate Benefits• High-k gate dielectric
– Reduced gate leakage– TOX scaling
• Metal gates– Eliminate polysilicon depletion– Resolves VT pinning and poor mobility
for high-k gate dielectrics
5
Metal Gate Flow OptionsGate-First
Dep Hi-k & Met 1
Patt Met 1 & Dep Met 2
Patt Met 2 & Etch Gates
S/D formation & Contacts
Dep & PattHik+Gate
S/D formation &ILD dep/polish
Rem Gate & Patt Met 1
Dep Met 2+Fill &Polish
Hik-First, Gate-Last
6
Metal Gate-Last Benefits• High Thermal budget available for Midsection
– Better Activation of S/D Implants
• Low thermal budget for Metal Gate– Large range of Gate Materials available
• Significant enhancement of strain– Both NMOS and PMOS benefits
• Low cost– Total wafer cost adder - 4%
7
Outline
• Introduction• Metal-Gate + Strain Integration• Transistor/Circuit Results• Manufacturing• Conclusions
8
Methods of NMOS Strain at 65nm
•Tensile Nitride Cap
•Stress Memorization→Gate + S/D
9
Methods of NMOS Strain at 65nm
•Tensile Nitride Cap
•Stress Memorization→Gate + S/D
10
NMOS strain: Tensile Cap Layer • Running out of space for Nitride Cap Layer
– Pitch degradation increases with pinchoff of film– Requires higher stress & thinner films
5
7
9
11
13
100150200250300Pitch (nm)
Idsa
t% g
ain
11
Tensile Contact Stress • Use Tensile trench contacts to
stress channelTrenchContacts
Poly
12
Tensile Contact Stress • Use of Tensile trench contacts provide 10% Idsat
improvement• Matched Contact Resistance
+10%
1
10
100
1000
0.70 0.90 1.10 1.30Idsat (mA/m)
Ioff
(nA
/ m
)
Tensile FillControl
VDD = 1.0V
13
NMOS strain: Metal Gate Stress• Gate Stress Memorization incompatible with Gate-
Last• Compressive Gate fill material induces strain
directly*– *C. Kang, et al, IEDM 2006
65nm 45nm
CompressiveGate Fill
14
Compressive Gate Stress • Compressive Gate Fill shows 5% Idsat improvement• Additive with Tensile Trench contacts
+5%
1
10
100
1000
0.9 1.1 1.3 1.5Idsat (mA/m)
Ioff
(nA
/ m
)
Compressive GateControl
VDD = 1.0V
15
Mitigation of NMOS stress on PMOS• Tensile Contact fill mitigated by raised SiGe S/D• Metal Gate Strain compensated by PMOS WFM
NMOS PMOS
Different gate stack Raised S/D
16
Gate Fill scalability for Gate-Last• Capability to <30nm demonstrated
0.5
1.0
1.5
2.0
20 30 40 50 60Gate Length (nm)
Nor
mal
ized
she
et rh
o
P-type gateN-type gate
30nm
17
PMOS strain: Pitch dependence • Embedded SiGe S/D mobility enhancement
strongly dependent on pitch
0.8
0.9
1.0
1.1
1.2
1.3
1.4
65nm 45nm
Nor
mal
ized
Idsa
t
Pitch scaling
Technology node
18
Embedded SiGe S/D• Continued Scaling for SiGe S/D
1. Ge concentration inc. to 30%
2. Gate → S/D distance reduced
65nm
45nm
15
25
35
90nm 65nm 45nmTechnology node
Ge
Con
c. (%
)
0
10
20
30
40
Gat
e-to
-SiG
e S/
D (n
m)
19
PMOS Strain: Gate-Last Flow• Use of Gate-Last Flow enhances Embedded SiGe S/D*
– *J. Wang, et al, VLSI 2007
• Removal of poly gate increases channel stress by 50%
Before gate removal After gate removal
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PMOS Strain Components • Three methods used enhance PMOS performance
1. Increase Ge Concentration in Embedded SiGe S/D
2. Move Embedded SiGe S/D closer to Gate
3. Remove dummy poly gate with Metal Gate-Last flow
Increase%Ge↑
Move SiGe
Remove Gate
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PMOS strain: Pitch dependence• Stress degraded due to Pitch Scaling
0.8
0.9
1.0
1.1
1.2
1.3
1.4
65nm 45nm
Nor
mal
ized
Idsa
t
Pitch scaling
Technology node
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PMOS strain: Pitch dependence• Proximity scaling recovers majority of pitch
degradation
0.8
0.9
1.0
1.1
1.2
1.3
1.4
65nm 45nm
Nor
mal
ized
Idsa
t
ProximityReduction
Technology node
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PMOS strain: Pitch dependence• %Ge provides strain benefit
0.8
0.9
1.0
1.1
1.2
1.3
1.4
65nm 45nm
Nor
mal
ized
Idsa
t Increase to30% Ge
Technology node
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PMOS strain: Pitch dependence• Gate-Last provides significant increase in
performance
0.8
0.9
1.0
1.1
1.2
1.3
1.4
65nm 45nm
Nor
mal
ized
Idsa
tRemoval of Gate
Technology node
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Metal Gate Stress (MGS)+ S/D Stress Memorization
Gate Stress Memorization + S/D Stress Memorization
Tensile Trench ContactsTensile Nitride Cap
NMOSNMOS
Replacement Gate Enhancement
Embedded SiGe S/D (higher %Ge + reduced S/D)
Embedded SiGe S/D
PMOSPMOS
45nm Method65nm Method
Strain Comparison
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Outline
• Introduction• Metal-Gate + Strain Integration• Transistor/Circuit Results• Manufacturing• Conclusions
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Gate Leakage • Gate leakage is reduced >25X for NMOS
and 1000X for PMOS
0.00001
0.0001
0.001
0.01
0.1
1
10
100
-1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2
VGS (V)
Nor
mal
ized
Gat
e Le
akag
e SiON/Poly 65nm
HiK+MG 45nm
NMOS PMOS
HiK+MG 45nm
SiON/Poly 65nm
65nm: Bai, 2004 IEDM
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Excellent short channel effects• Subthreshold slope - 100mV/decade• DIBL - 140mV/V NMOS & 200mV/V PMOS
0.00010.0010.010.1
110
1001000
10000
-1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2Vgs (V)
Id (
A/
m)
|Vds|=1.0V
|Vds|=0.05V
PMOS NMOS
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NMOS IDSAT vs. IOFF
1.36 mA/m at IOFF = 100 nA/m & 1.0V12% better than 65 nm
160 nm
• Best drives for 45nm or 32nm technology
1
10
100
1000
0.8 1.0 1.2 1.4 1.6Idsatn (mA/m)
Ioffn
(nA
/ m
)
65nm [Tyagi, 2005 IEDM]
VDD = 1.0V
12%
30
NMOS IDlin vs. IOFF
0.192 mA/m at IOFF = 100 nA/m8% better than 65 nm
160 nm
1
10
100
1000
0.13 0.15 0.17 0.19 0.21Idlin (mA/m)
Ioff
(nA
/ m
)
VDS = 0.05V
65nm [Tyagi,2005 IEDM]
8%
31
PMOS IDSAT vs. IOFF
1.07 mA/m at IOFF = 100 nA/m & 1.0V51% better than 65nm
160 nm
• Best drives for 45nm or 32nm technology
1
10
100
1000
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3Idsatp (mA/m)
Ioffp
(nA
/ m
)
65nm [Tyagi, 2005 IEDM]
VDD = 1.0V
51%
32
PMOS IDlin vs. IOFF
0.178 mA/m at IOFF = 100 nA/m72% better than 65nm!
7% from NMOS
160 nm
1
10
100
1000
0.08 0.11 0.14 0.17 0.2Idlin (mA/m)
Ioff
(nA
/ m
)
VDS = 0.05V
65nm [Tyagi, 2005 IEDM]
72%
33
SOC Application
NMOS: 1.04 mA/m at IOFF = 1 nA/m & 1.1VPMOS: 0.88 mA/m at IOFF = 1 nA/m & 1.1V
• LSTP benchmark (1nA & 1.1V)
0.01
0.1
1
10
100
0.4 0.6 0.8 1.0 1.2 1.4Idsatn (mA/m)
Ioffn
(nA
/ m
)
65nm @ 1.2V [Post, 2006 IEDM]
0.01
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2
Idsatp (mA/m)
Ioffp
(nA
/m
)
65nm @ 1.2V [Post, 2006 IEDM]
34
Metal Gate Last flow enables 23% reduction in RO delay at the same leakage
Ring Oscillator Speed
3
4
5
6
7
8
9
10 100 1000 10000IOFFN + IOFFP (nA/um)
DEL
AY
PER
STA
GE
(pS)
65nm @ 1.2V
45nm @1.1V
FO=2
+2Cjunction
-8Cgate/Cov
Benefit (%)
Component
+23Total
-7Voltage Scaling
+2NMOS Idlin
+3NMOS Idsat
+18PMOS Idlin
+13PMOS Idsat
+2Cjunction
-8Cgate/Cov
Benefit (%)
Component
+23Total
-7Voltage Scaling
+2NMOS Idlin
+3NMOS Idsat
+18PMOS Idlin
+13PMOS Idsat
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Power: SRAM VCCmin• Low active VCCmin important for low power
applications• 3Mb SRAM
– 0.346m2 cell median active VCCmin of 0.70V– 0.382m2 cell median active VCCmin of 0.625V
36
Outline
• Introduction• Metal-Gate + Strain Integration• Transistor/Circuit Results• Manufacturing• Conclusions
37
193nm Dry lithography - Poly• Critical Layers patterned with 193nm Dry lithography
– Lower cost & Mature toolset – Transistor Formation Mask Count Neutral with 65nm
• Double Patterning used at Poly– Array of Poly lines are patterned– Discrete allowed pitches– Poly lines are Cut
Post 1st layer
Poly
Post 2nd layer
Cuts
65nm SRAM 45nm SRAM
38
Multiple Microprocessors
Single Core Dual Core
Quad Core Six Core
39
Defect Reduction Trend• Record yields demonstrated <2 years after 65 nm
– Fastest Ramp to high yield ever at Intel
Defect Density
(log scale)2yrs
2001 2002 2003 2004 2005 2006 2007 2008 2009
90 nm 65 nm 45 nm
40
Conclusions• High-k + Metal Gate transistors have been integrated
with Novel Strain techniques
• Gate-Last flow provides significant strain enhancements both on NMOS and PMOS– Key driver for process flow decision– Achieve record drive currents at tight gate pitch
• 193nm Dry lithography can be extended to the 45nm technology node
• The technology is already in high volume manufacturing– High yields demonstrated on multiple microprocessors
41
Acknowledgements• The authors gratefully acknowledge the
many people in the following organizations at Intel who contributed to this work:– Portland Technology Development – Quality and Reliability Engineering– Process & Technology Modeling– Assembly & Test Technology Development
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For further information on Intel's silicon technology, please visit our Technology & Research page at
www.intel.com/technology