544 ieee transactions on components, packaging and … · 2018-08-13 · 544 ieee transactions on...

544 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 4, APRIL 2017

Via-First Process to Enable Copper Metallization ofGlass Interposers With High-Aspect-Ratio,

Fine-Pitch Through-Package-ViasTimothy B. Huang, Bruce Chou, Jialing Tong, Tomonori Ogawa, Venky Sundaram,

and Rao R. Tummala, Life Fellow, IEEE

Abstract— A via-first process for metallizing copper on glasssubstrates is presented using a thin, patternable polymerfilm, electroless copper deposition, and semiadditive processing.A procedure for partially precuring the polymer was developedin order to achieve a tented via structure after dry-film lamina-tion and curing. The flexibility of the process is demonstratedby the use of plasma etching, CO2, and UV laser ablationas patterning technologies. Metallization by electroless copperdeposition and semiadditive processing is shown to be conformal,continuous, and without defects on the surface and in the viasas demonstrated by cross-sectional analysis. Glass of 100 µmthickness with vias of 10–20 µm diameter and 40 µm pitchwas metallized to demonstrate the dimensional capability of theprocess. Thermomechanical reliability was validated by copperpeel testing after highly accelerated stress testing and daisy-chainresistance measurements taken throughout thermal cycle testing.

Index Terms— Electronics packaging, glass interposer,metallization, reliability.

I. INTRODUCTION

DRIVEN by increasing demands for higher logic-memory bandwidth in high-performance applications,

next-generation 2.5-D and 3-D system packages requirefine-pitch copper through-package-vias (TPVs) to support fine-pitch fan-out and fine-pitch bumps. Glass was proposed as theprime substrate material for low-loss and high-performanceapplications, having superior mechanical properties to that oforganic composites and better electrical properties and lowermaterial cost compared to silicon [1], [2]. A method capableof achieving high-quality copper metallization on ultrathinglass substrates (≤100 μm) with fine-pitch (≤120 μm), small-diameter (≤60 μm) TPVs, while demonstrating satisfactory

Manuscript received June 27, 2016; revised November 18, 2016; acceptedJanuary 2, 2017. Date of publication February 7, 2017; date of current versionApril 18, 2017. This work was supported by the Low-Cost Glass Interposerconsortium at the 3D Systems Packaging Research Center, Georgia Instituteof Technology. Recommended for publication by Associate Editor D. Lu uponevaluation of reviewers’ comments.

T. B. Huang and R. R. Tummala are with the Materials Science andEngineering Department, Georgia Institute of Technology, Atlanta, GA 30332USA (e-mail: [email protected]; [email protected]).

B. Chou, J. Tong, and V. Sundaram are with the Electrical andComputer Engineering Department, Georgia Institute of Technology,Atlanta, GA 30332 USA (e-mail: [email protected]; [email protected];[email protected]).

T. Ogawa is with Asahi Glass Co., Tokyo 100-8405, Japan (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2017.2654219

copper adhesion and thermomechanical reliability usingelectroless metallization, is crucial for the glass substratetechnology.

Meeting these criteria is challenging for several reasons.Fundamentally, copper and glass do not adhere well due totheir differing chemical structures; the covalent oxide networkof glass and the metallic lattice of copper do not readily formchemical bonds at the interface. Chemical bonding can bepromoted by chemically treating the glass surface prior toelectroless deposition [3], [4], but this alone is insufficient toprovide satisfactory adhesion. Adhesion can also be improvedby roughening the glass surface, leading to mechanical anchor-ing at the copper–glass interface [5]–[7]. However, it wasshown that roughness in conductor interfaces can degradehigh-frequency electrical performance because of the skineffect [8]. The high degree of mismatch in the coefficientof thermal expansion (CTE) of glass (3 ppm/K) and copper(17 ppm/K) will further challenge the interfacial adhesionwhen subjected to stresses in thermal cycle testing (TCT), anindustry-standard reliability test. Finally, the requirement ofsmall-diameter, high-aspect-ratio TPVs in glass is challengingfor metallization techniques that are nonconformal in nature(e.g., sputtering). Several methods have been recently demon-strated to address some of these challenges, all of which utilizean intermediate adhesion layer between glass and copper.

Via metallization processes can be divided into two cat-egories: via-last, where TPVs are formed after other priorprocessing, and via-first, where TPVs in glass are formedbefore any subsequent processing. One via-last process, shownin Fig. 1, demonstrated that laminating a polymer film ontoglass followed by TPV formation and electroless metallizationyields a stable structure [9]–[11]. The polymer film serves asan intermediate adhesion layer by forming chemical bondsto glass through silane coupling agents on one side andmechanical anchoring to electroless copper on the other side.The polymer also functions as a mechanical stress buffer andaids in the handling of ultrathin glass.

Recently, however, glass substrate manufacturers havedeveloped via formation technologies that are incompat-ible when polymer films are present. The most recentdemonstrations have focused on via-first metallizationprocesses in glass. Sputtering titanium or chromium, whichare known to form chemical bonds to glass, followed by thedesired metal that does not adhere strongly to glass directly

2156-3950 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

HUANG et al.: VIA-sFIRST PROCESS TO ENABLE COPPER METALLIZATION OF GLASS INTERPOSERS 545

Fig. 1. Schematic process flow of metallizing glass interposers by a via-lastprocess.

is a well-known method of depositing metals onto glass[12]–[17]. Due to the line-of-sight nature of sputtering,depositing metal onto the TPV sidewalls that are parallel tothe flux of sputtering is not as straightforward as the planarsurface that is perpendicular to the flux of sputtering. It followsthat there is an inherent upper limit to the aspect ratio ofvias that can be metallized conformally by sputtering beforethe TPV centers are unable to receive sufficient sputteringflux. A method to address this issue was demonstrated bysubsequently using electroless metallization to fill any discon-tinuities in the previous sputtering step [18]. Another recentlydemonstrated glass metallization technology uses a thin metal-oxide film that forms chemical bonds to glass and mechanicalbonding to electroless copper. The deposition is done by sol-gel processing to enable conformal TPV coverage [19]–[23].

This paper describes a novel process that utilizes a thin,patternable polymer film as an intermediate layer betweenglass and electroless copper. The reduced polymer thicknessfacilitates the patterning process to re-expose the glass vias.Finally, a copper seed layer is deposited by electroless metal-lization, making the substrate ready for semiadditive process-ing. The methodology of each processing step is described,and a fully fabricated two metal layer structure is proven tobe thermomechanically reliable after TCT to 1000 cycles andhighly accelerated stress testing (HAST) for 96 h.

II. FABRICATION PROCESS

The basic process flow for the via-first metallization processis shown in Fig. 2. TPVs are initially formed in a glass panel.Then, a thin polymer film is laminated on both sides of thesubstrate, covering the vias. Next, the polymer areas over thevias are patterned to open the vias. Details of each processingstep are described in Sections II-A–II-C.

Glass substrates were prepared as follows. Low-CTE(∼3 ppm/K) glass substrates of 100 and 130 μm thicknesswere used (EN-A1 from Asahi Glass Co. and SGW3 from

Fig. 2. Schematic process flow of metallizing glass interposers by a via-firstprocess.

Corning Inc.). Substrates were panels 76.2 × 76.2 mm2 orlarger in size. For daisy-chain resistance structures, glassthrough-vias with 60 μm entrance diameter and 120 μm pitchwere formed into arrays by the glass supplier. Glass substrateswere cleaned with acetone and isopropyl alcohol, followed byan O2 plasma clean. Finally, a silanization step was done topromote chemical adhesion between the polymer and glass [1].

A. Polymer Preparation and Lamination

In this process, the laminated polymer film will ideally“tent” over the vias; i.e., the film lies over without flowinginside the vias. However, polymers are expected to flow withdecreased viscosity at the elevated temperatures during thecuring process. Polymer flow into the vias will increase thethickness of polymer in the TPV region, making it difficultfor subsequent etch patterning. Steps were taken to partiallyprecure the polymer film prior to lamination in order to reducethe viscosity of the curing polymer and therefore the degreeof flowing into the vias.

An epoxy-based polymer film of 5 μm thickness waschosen as the dry-film polymer due to its excellent dielectricproperties and known compatibility with electroless copperplating. Normally stored at −40 °C, the polymer films wereexposed to elevated temperatures for extended periods of time,and Fourier transform infrared spectroscopy (FTIR) was usedto qualitatively observe the degree of precuring in the epoxy-based films prior to lamination. The uncured film is composedof an epoxy resin and phenol-based hardener. During thecuring process, they are exposed to elevated temperatures andreact to form a cross-linked polymer network [Fig. 3(a)]. Thedegree of curing can therefore be qualitatively observed bythe reduction in absorption intensity of the uncured epoxygroup at 912 cm−1 [24]. The FTIR absorbance spectrumof the polymer film after three different curing conditionsis shown in Fig. 3(b), and the corresponding cross sections


Fig. 3. (a) Reaction of uncured epoxy resin and phenol-based hardener duringpolymer curing. (b) FTIR absorption spectra showing epoxy peak after variousamounts of polymer curing: (—) uncured; (– –) precured at room temperaturefor 12 h; (- - · – ·) precured at room temperature for 12 h followed by 100 °Cfor 20 min; (– · -) fully cured at 180 °C for 30 min.

Fig. 4. Optical micrographs of cross sections after lamination with variousdegrees of polymer precuring. (a) With no precuring, significant flow ofpolymer into vias is observed. (b) After a low amount of precuring, polymerflow is reduced but still apparent. (c) With sufficient precuring, polymer flowis prevented and tenting is achieved.

after lamination are shown in Fig. 4. The fully cured filmwas prepared by heating at 180 °C for 30 min and producedthe lowest absorption intensity, as expected. In contrast, theuncured film produced the highest absorption intensity, andlamination onto the glass resulted in a significant amountof polymer flow into the TPVs, leaving an air-filled void,as shown in Fig. 4(a). The film was then kept at roomtemperature for 12 h prior to lamination. A slightly diminishedabsorption intensity was observed compared to the uncuredfilm, indicating that a small degree of precuring has occurred.The result was confirmed by observing the cross section of thelaminated film, which shows a significantly reduced volumeof polymer flow into the TPV after lamination [Fig. 4(b)]compared to the case with no precuring. Finally, the polymerwas kept at room temperature for 12 h followed by heating

Fig. 5. Top-down optical micrographs of vias after polymer material waspatterned by (a) plasma etching, (b) CO2, and (c) UV laser ablation.

at 100 °C for 20 min. The epoxide absorption intensity wasfurther reduced, and the cross section after lamination showsthat with sufficient precuring the polymer can completelytent the TPVs [Fig. 4(c)]. This tented structure is ideal forsubsequent polymer patterning to re-expose the TPVs.

B. Polymer Patterning

There are many methods of etch patterning thin polymerfilms. This paper investigates plasma etching and laser ablationas they are scalable and widely adopted technologies in panel-size microelectronics fabrication.

Plasma etching requires an etch mask to differentiate thepolymer regions over the vias from the regions over blankglass. Dry-film photoresist with a thickness greater than theunderlying polymer film was used as the etch mask. Afterlamination onto the polymer-tented glass substrate, the pho-toresist was exposed and developed to expose the tentingpolymer regions over the vias. An RF plasma (400 W power)of O2 and CF4 gas (1:1 mixture) at 100 °C was used to etchthe exposed polymer over a duration of about 15 min. Finally,the photoresist was stripped. Fig. 5(a) shows a top-down viewafter patterning by plasma etching, and it is apparent that theglass vias have been fully exposed.

Two different lasers were used to directly pattern the lami-nated polymer films. One was a CO2 laser (λ = 10.6 μm)with a maximum output of 80 W, which used ten pulsesat about 20% power. The second was a UV laser(λ = 266 nm), which only required one pulse at 90% power.Top-down micrographs of polymer-tented glass substrates pat-terned by CO2 and UV lasers can be seen in Fig. 5(b) and (c),respectively.

The results from each patterning technique are comparable.In all cases, the etched polymer region has a diameter ofabout 80 μm, and a small (∼5 μm) ring of bare glass isleft exposed around the glass TPVs. Of these technologies,laser ablation is a relatively simpler process as it does not


Fig. 6. Top-down optical micrograph of fabricated daisy-chain structuresafter semiadditive processing.

require additional steps for lithography. However, laser abla-tion has the potential to induce unwanted modification tothe underlying glass and has a lower theoretical throughputcompared to plasma etching, which is a planar process. Thismetallization process is not limited to these examples. Anypolymer patterning method can be used provided it resultsin fully opened vias and that the polymer provides stronginterfacial adhesion to subsequent electroless metallization andmeets the necessary dielectric requirements.

C. Copper Metallization

After polymer films were patterned, about 350 nm of copperwas conformally deposited using a commercial electrolessplating bath (Atotech Inc.). Electroless copper depositionresulted in continuous, conformal coverage on the polymer-laminated surface and on the sidewalls of the glass vias.After electroless plating, copper daisy chains were fabricatedby semiadditive processing with a final copper thickness ofabout 20 μm and annealed at 160 °C for 1 h. For this paper,the vias were conformally plated by electrolytic Cu deposition.Compared to fully filled vias, conformal plating providescomparable electrical performance in RF and millimeter-waveapplications due to the skin effect [25] while reducing process-ing costs.

The fabricated daisy chains were observed to be free of anyapparent blisters, delamination, or other metallization defectson the surface (Fig. 6). Cross sections of the conformal-plateddaisy chains were prepared to assess the metallization coverageat each interface. As seen in Fig. 7, about 20 μm of copperwas deposited after electrolytic plating without any observabledefects at the copper/glass or copper/polymer interfaces.

III. RELIABILITY TESTING

A. HAST and Peel Strength

Copper peel testing was performed to determine if thecopper adhesion to the polymer film was negatively impactedby introducing the precuring step compared to the standard

Fig. 7. Top: optical micrograph of a daisy-chain cross section after completedfabrication. Bottom: scanning electron micrograph showing continuous andvoid-free copper metallization of vias in glass.

Fig. 8. Comparison of 90° peel strength of copper on polymer laminated withtenting and nontenting conditions. Error bars represent one standard deviation.

polymer lamination and curing procedure. Substrates were pre-pared with and without tenting lamination conditions, followedby electroless copper deposition and electrolytic plating toa final thickness of 25 μm. In HAST, the polymer absorbsmoisture that migrates to the Cu-polymer interface whereCu oxidation is induced. The formation of CuO and Cu2Ocreates a weak interface with the bulk metallic Cu and leadsto reduced adhesion strength [26]. To investigate the effect ofmodifying the dielectric processing conditions on Cu adhesion,peel tests were conducted at an angle of 90° before and after24, 48, and 96 h of unbiased HAST performed accordingto JEDEC Standard JESD22-A118 Condition A, having atemperature of 130 °C and a relative humidity of 85%.

The peel strength results are shown in Fig. 8. As expected,the peel strength decreased in both cases with increasedexposure to HAST conditions. After 48 h of exposure, thepeel strength ceased to decrease and remained constant.At all times, however, the difference in peel strength betweensamples with and without tenting conditions was within the


Fig. 9. Design of daisy-chain structures. The number of vias in each daisychain is labeled near the traces for the respective daisy chain. Green andred lines represent copper traces on the top and bottom sides of the glass,respectively, and the yellow rings represent the glass vias.

measured deviation. This suggests that changes in the lami-nation conditions had a negligible effect on the mechanismof mechanical failure at the Cu-polymer interface. Adhesionbetween the copper and polymer is strongly determined bythe roughness induced as part of the preparation for electrolessplating. The modified precuring procedure of this polymer filmtherefore does not have a significant effect on the resultingCu-polymer interfacial strength characteristics.

B. Thermal Cycle Testing

For daisy-chain resistance and TCT, structures consisting ofKelvin resistance structures were designed with eight differentlengths ranging from 2 to 66 vias in the 16 × 16 array of viasas depicted in Fig. 9. Daisy-chain resistances were measuredbefore and throughout 1000 thermal cycles using the standardfour-point method of driving a 50-mA current source from oneend of the chain to the other and sensing the voltage drop usinga multimeter (Keithley Instruments). TCT was performedaccording to JEDEC Standard JESD22-A104D Condition B,having a maximum and minimum temperature of 125 °Cand −55 °C, respectively. A soak time of 15 min was used atthe maximum and minimum temperatures.

The initial resistances for one set of daisy chains are shownin Fig. 10. A least-squares linear fit set with a y-interceptof 0 yielded a slope corresponding to a resistance of 10.0 m�per via and a correlation coefficient of 0.9922. As expected, thedata correlates well with the linear fit since the total resistanceis determined by the length of the copper daisy chain and isdirectly proportional to the number of vias in the chain. Thedaisy-chain resistance was then monitored after 250, 500, and1000 thermal cycles (Fig. 11). The standard deviation in theresistance among daisy chains of the same length was lessthan 10%. However, the largest change in resistance for anydaisy chain with a length of 66 vias was only 1.18% after 1000thermal cycles. The deviation in resistance among daisy chainsof the same length is attributed to variations in electrolyticplated copper thickness from sample to sample. Therefore, the

Fig. 10. Initial resistance of eight daisy chains from one 16 × 16 array ofvias.

Fig. 11. Daisy-chain resistance measured throughout thermal cycle testing.Four of eight measured daisy chain lengths are shown for simplicity. Errorbars represent one standard deviation.

change in resistance was negligible for any individual daisychain.

No copper delamination was observed by optical inspectionof the surface and in the vias after cross sectioning. Thisprocess involves the plating of copper directly on the glassvia sidewall without a polymer adhesion layer. On the smoothglass surface (Ra < 1 nm), copper is mechanically anchoredto the rough polymer film. At the via sidewall interface, thenecessary adhesion between copper and bare glass is attributedto mechanical anchoring of copper to the micro- and nano-roughened via sidewall that results from glass via formationprocessing [9], [27], [28]. A previous study showed that asubmicro-roughened glass surface was sufficient to pass a tapetest after electroless copper deposition [29]. As expected, therobustness of the Cu/polymer/glass structure was validated andis consistent with previous studies using a similar structure,despite not having a polymer coating on the via sidewalls.

IV. DISCUSSION

The via-first process demonstrated in Section II isnot limited to any specific polymer materials and


Fig. 12. Scanning electron micrograph of cross section showing glassof 100 μm thickness with vias of diameter 20 and 40 μm pitch afterpolymer lamination, polymer patterning, electroless copper deposition, andsemiadditive processing.

processing techniques. In general, any polymer film thatis compatible with electroless metal deposition can be usedin conjunction with an appropriate patterning process. Forexample, a photo-sensitive polymer film could be used fordirect patterning instead of laser ablation. Depending on theneeds of specific applications, the most suitable materials andprocesses can be chosen accordingly.

Finer via pitch is desirable in digital high-performanceapplications such as 2.5-D and 3-D IC. A preliminary testwas done to assess the capability of the via-first processto metallize glass with small diameter and fine-pitch vias.Glass substrates were obtained having 100 μm thickness andvias with an entrance and exit diameter of 20 and 10 μm,respectively, and 40 μm pitch. The previously describedprocesses were successfully completed, and a cross sectionof the metallized glass with daisy-chain structures is shown inFig. 12. The copper coverage is uniform along the polymer-lined surface and the sidewalls of the glass vias. In this case,the via aspect ratio was as high as ten. The aspect ratio, higherthan what is readily achievable by sputtering, is limited onlyby the practical limits of electroless and electrolytic copperdeposition. The smallest diameter and finest achievable pitchdepends on the polymer patterning capability because theamount of excess polymer etched around the glass vias willlimit the amount of polymer coverage between adjacent vias.Fine-pitch metallization requires the diameter of the etchedpolymer region to be as close as possible to that of theunderlying glass via.

The ability to scale to fine pitch is not only desirable indigital high performance applications. Closely packed viascan be used to design impedance-matched high-speed signalsfrom chip to board [30], with via guard wall acting as elec-tromagnetic interference (EMI) shield to protect the adjacentsignals from crosstalk [31]. The high-speed and EMI-shieldedsignals are crucial for radio-frequency, millimeter-wave, andoptoelectronic applications [32]. Closely packed power and

ground vias can also mitigate the power handling concerns ofconformal filled vias to ensure power that integrity is met.

V. CONCLUSION

A via-first process was shown that enables electroless cop-per metallization on glass substrates. The process utilizes athin (5 μm thickness) polymer film that serves as an inter-mediate adhesion layer between glass and electroless copper.A polymer precure step proved to be necessary in order toprevent polymer flow into the vias during lamination andcuring. Optimized polymer precuring results in no observableflow of polymer into the vias, and this tented structure pro-vides the ideal conditions for subsequent patterning. Severalmethods of polymer patterning were used, including plasmaetching as well as CO2 and UV laser ablation. Each processwas capable of opening the vias, and the patterning qualitywas comparable across all methods. A conformal copperseed layer was deposited by electroless deposition. Finally,daisy chains were patterned by semiadditive processing. Cross-sectional analysis showed that the plated copper was contin-uous and without plating defects on the glass via sidewallsand on the polymer-laminated glass surface. The adhesionbetween copper and polymer was measured by peel testingbefore and throughout 96 h of HAST conditions and showednegligible changes in copper adhesion between the polymerfilms laminated with precured (tenting) and normal (nontent-ing) conditions. Additionally, the maximum change in daisy-chain resistance was only 1.18% after 1000 thermal cycles,validating the thermomechanical reliability of the structurefabricated by this process. Vias with 10–20 μm diameterwith 40 μm pitch in 100-μm-thick glass were successfullymetallized to demonstrate the dimensional capability of thisprocess.

ACKNOWLEDGMENT

The authors would like to thank C. White and J. Bishop fortheir guidance and support in sample fabrication.

REFERENCES

[1] V. Sukumaran, T. Bandyopadhyay, V. Sundaram, and R. Tummala,“Low-cost thin glass interposers as a superior alternative to siliconand organic interposers for packaging of 3-D ICs,” IEEE Trans.Compon., Packag., Manuf. Technol., vol. 2, no. 9, pp. 1426–1433,Sep. 2012.

[2] G. Kumar, T. Bandyopadhyay, V. Sukumaran, V. Sundaram, S. K. Lim,and R. Tummala, “Ultra-high I/O density glass/silicon interposers forhigh bandwidth smart mobile applications,” in Proc. 61st IEEE ECTC,Jun. 2011, pp. 217–223.

[3] Z.-C. Liu, Q.-G. He, P. Hou, P.-F. Xiao, N.-Y. He, and Z.-H. Lu,“Electroless plating of copper through successive pretreatment withsilane and colloidal silver,” Colloids Surf. A, Physicochem. Eng. Aspects,vols. 257–258, pp. 283–286, May 2005.

[4] W. Su, L. Yao, F. Yang, P. Li, J. Chen, and L. Liang, “Electroless platingof copper on surface-modified glass substrate,” Appl. Surf. Sci., vol. 257,pp. 8067–8071, Jul. 2011.

[5] X. Cui, D. Bhatt, D. A. Hutt, K. Williams, and P. P. Conway, “Copperdeposition and patterning for glass substrate manufacture,” in Proc. 9thEPTC, Dec. 2007, pp. 37–42.

[6] S. Bamberg et al., “P-66: Wet chemical metallization for high-end flatpanel display manufacturing,” in SID Symp. Dig. Tech. Papers, vol. 42.2011, pp. 1351–1354.

[7] S. Bamberg et al., “Challenges of adhesion promotion for the metalliza-tion of glass interposers,” in Proc. 46th Int. Symp. Microelectron., 2013,pp. 000635–000640.


[8] G. Brist, S. Hall, S. Clouser, and T. Liang, “Non-classical conductorlosses due to copper foil roughness and treatment,” in Proc. Electron.Circuit World Conv., Feb. 2005, pp. 22–24.

[9] V. Sukumaran et al., “Through-package-via formation and metallizationof glass interposers,” in Proc. 60th ECTC, Jun. 2010, pp. 557–563.

[10] V. Sukumaran et al., “Design, fabrication, and characterization ofultrathin 3-D glass interposers with through-package-vias at same pitchas TSVs in silicon,” IEEE Trans. Compon., Packag., Manuf. Technol.,vol. 4, no. 5, pp. 786–795, May 2014.

[11] S. Cho, V. Sundaram, R. R. Tummala, and Y. K. Joshi, “Impact ofcopper through-package vias on thermal performance of glass inter-posers,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 5, no. 8,pp. 1075–1084, Aug. 2015.

[12] P. Benjamin and C. Weaver, “The adhesion of evaporated metal filmson glass,” Proc. Roy. Soc. London A, Math. Phys. Sci., vol. 261,pp. 516–531, May 1961.

[13] M. P. Borom and J. A. Pask, “Role of ‘adherence oxides’ in thedevelopment of chemical bonding at glass-metal interfaces,” J. Amer.Ceram. Soc., vol. 49, no. 1, pp. 1–6, 1966.

[14] Y. H. Kim, Y. S. Chaug, N. J. Chou, and J. Kim, “Adhesion of titaniumthin film to oxide substrates,” J. Vac. Sci. Technol. A, Vac. Surf. Films,vol. 5, pp. 2890–2893, Feb. 1987.

[15] S. W. Russell et al., “Enhanced adhesion of copper to dielectrics viatitanium and chromium additions and sacrificial reactions,” Thin SolidFilms, vol. 262, pp. 154–167, Jun. 1995.

[16] N. Jiang and J. Silcox, “Observations of reaction zones atchromium/oxide glass interfaces,” J. Appl. Phys., vol. 87,pp. 3768–3776, Jan. 2000.

[17] J. Keech, S. Chaparala, A. Shorey, G. Piech, and S. Pollard, “Fabri-cation of 3D-IC interposers,” in Proc. 63rd IEEE ECTC, May 2013,pp. 1829–1833.

[18] P. Ogutu, E. Fey, P. Borgesen, and N. Dimitrov, “Hybrid method formetallization of glass interposers,” J. Electrochem. Soc., vol. 160, no. 12,pp. D3228–D3236, 2013.

[19] H. Fu, S. Hunegnaw, Z. Liu, L. Brandt, and T. Magaya, “Adhesiveenabling technology for directly plating copper onto glass/ceramicsubstrates,” in Proc. 64th IEEE ECTC, May 2014, pp. 1652–1655.

[20] S. Hunegnaw, L. Brandt, H. Fu, Z. Liu, and T. Magaya, “Adhe-sion enabling technology for reliable metallization and patterning ofglass interposers,” in Proc. Int. Symp. Microelectron., Oct. 2014,pp. 000393–000396.

[21] K. Mukai, T. Magaya, L. Brandt, L. Zhiming, H. Fu, and S. Hunegnaw,“Adhesive enabling technology for directly plating copper onto glass,”in Proc. 9th IMPACT, Jan. 2014, pp. 170–173.

[22] S. Hunegnaw et al., “VitroCoat GI—Ultra-thin adhesive layer formetallization of glass interposer,” in Proc. 10th IMPACT, Oct. 2015,pp. 149–152.

[23] Z. Liu et al., “A metal oxide adhesion layer prepared with water basedcoating solution for wet Cu metallization of glass interposer,” in Proc.Int. Symp. Microelectron., Oct. 2015, pp. 000365–000369.

[24] X. Ramis, J. M. Salla, C. Mas, A. Mantecón, and A. Serra, “Kineticstudy by FTIR, TMA, and DSC of the curing of a mixture of DGEBAresin and γ -butyrolactone catalyzed by ytterbium triflate,” J. Appl.Polym. Sci., vol. 92, pp. 381–393, Apr. 2004.

[25] D. M. Pozar, Microwave Engineering, 4th ed. Hoboken, NJ, USA: Wiley,2011.

[26] S.-J. Cho, K.-W. Paik, and Y.-G. Kim, “The effect of the oxidation ofCu-base leadframe on the interface adhesion between Cu metal andepoxy molding compound,” IEEE Trans. Compon., Packag., Manuf.Technol. B, vol. 20, no. 2, pp. 167–175, May 1997.

[27] K. Demir et al., “Thermomechanical and electrochemical reliabil-ity of fine-pitch through-package-copper vias (TPV) in thin glassinterposers and packages,” in Proc. 63rd IEEE ECTC, May 2013,pp. 353–359.

[28] M. Broas, K. Demir, Y. Sato, V. Sundaram, and R. Tummala,“A comparative reliability study of copper-plated glass vias, drilled withCO2 and ArF excimer lasers,” in Proc. ESTC, Sep. 2014, pp. 1–5.

[29] T. Huang, V. Sundaram, P. M. Raj, H. Sharma, and R. Tummala,“Adhesion and reliability of direct Cu metallization of through-packagevias in glass interposers,” in Proc. 64th IEEE ECTC, May 2014,pp. 2266–2270.

[30] N. Kim, D. Wu, J. Carrel, J. H. Kim, and P. Wu, “Channel designmethodology for 28Gb/s SerDes FPGA applications with stacked sil-icon interconnect technology,” in Proc. 62nd IEEE ECTC, Jun. 2012,pp. 1786–1793.

[31] S. Sitaraman, J. Min, M. R. Pulugurtha, M. S. Kim, V. Sundaram,and R. Tummala, “Modeling, design and demonstration of integratedelectromagnetic shielding for miniaturized RF SOP glass packages,”in Proc. 65th IEEE ECTC, May 2015, pp. 1956–1960.

[32] B. Sawyer et al., “Design and demonstration of 2.5D glass interposersas a superior alternative to silicon interposers for 28 Gbps signaltransmission,” in Proc. 66th IEEE ECTC, Jun. 2016, pp. 972–977.

Timothy B. Huang received the B.S. and M.S.degrees in materials science and engineering fromthe University of Illinois at Urbana–Champaign,Champaign, IL, USA, in 2010 and 2012, respec-tively. He is currently pursuing the Ph.D. degree inmaterials science and engineering with the GeorgiaInstitute of Technology, Atlanta, GA, USA.

He was a Research and Development Intern atAtotech USA, Inc., Englewood, CO, USA. He iscurrently a Graduate Research Assistant with the3-D Systems Packaging Research Center, Georgia

Institute of Technology. His current research interests include interfacialadhesion characterization and process development for Cu metallization onglass interposers as well as electrochemical analysis of organic additives inelectrolytic Cu plating baths.

Bruce Chou received two B.S. degrees in electricalengineering and mathematics and the M.S degreein electrical engineering from the Universityof Florida, Gainesville, FL, USA, in 2004 and2006, respectively, and the Ph.D. degree inelectrical engineering from the Georgia Institute ofTechnology, Atlanta, GA, USA, in 2016.

From 2006 to 2011, he was a ComponentDesign Engineer at Intel Corporation,Hillsboro, OR, USA, where he designedinterface circuit blocks for Intel’s 32-, 22-, and

14-nm process libraries. He is currently a Photonics Packaging Engineerwith Rockley Photonics Inc., Pasadena, CA, USA. His research interestsincluded high-performance electronic and optoelectronic packaging.

Dr. Chou was a recipient of the 2013 and 2016 IEEE CPMT Society TravelAwards and the Best Student Paper Award at the International Symposiumof Microelectronics in 2015.

Jialing Tong received the B.S. degree in informa-tion engineering from Southeast University, Nanjing,China, in 2009, and the M.S. and Ph.D. degrees inelectrical engineering from the Georgia Institute ofTechnology, Atlanta, GA, USA, in 2015 and 2016,respectively.

From 2009 to 2012, he was a Graduate ResearchAssistant at the Center for Microwave and RF Tech-nologies, Shanghai Jiao Tong University, Shanghai,China. He is currently a Senior Engineer atQualcomm Technologies, San Diego, CA, USA. His

current research interests include electrical modeling, design, and characteriza-tion of through-package-vias in silicon and glass interposers, electromagneticsimulations, signal and power integrity analysis, and millimeter-wave charac-terization.

Dr. Tong was a recipient of the Best Student Paper Award at the 2015Global Interposer Technology Workshop, the Bosch Scholarship in 2011, andthe Research in Motion Scholarship in 2010.

Tomonori Ogawa received the M.E. degree ininnovative and engineered materials from the TokyoInstitute of Technology, Tokyo, Japan.

In 2000, he joined Asahi Glass Company, Tokyo,where he was involved in the electronics division forproduction process development for the company’sspecialized synthetic silica glass. Since 2014, hehas been a Visiting Engineer with the 3-D Sys-tems Packaging Research Center, Georgia Instituteof Technology, Atlanta, GA, USA, where he hasbeen involved in a global industry-academia research

consortium about glass interposers.


Venky Sundaram received the B.S. degree fromthe Indian Institute of Technology (IIT) Bom-bay, Mumbai, India, and the M.S. and Ph.D.degrees in materials science and engineering fromthe Georgia Institute of Technology, Atlanta,GA, USA.

He is currently the Director of Research andIndustry Relations with the 3-D Systems PackagingResearch Center, Georgia Institute of Technology.He is a globally recognized expert in packagingtechnology and the Co-Founder of Jacket Micro

Devices, Decatur, GA, USA, an RF/wireless start-up acquired by AVX. Hehas authored 100 publications and holds over 15 patents. His current researchinterests include system-on-package technology, 3-D packaging and inte-gration, ultra-high-density interposers, embedded components, and systemsintegration research.

Dr. Sundaram was a recipient of several best paper awards. He is theCo-Chairman of the IEEE Components, Packaging, and Manufacturing Tech-nology Technical Committee on High-Density Substrates and is the Directorof Educational Programs with the Executive Council of the InternationalMicroelectronics Assembly and Packaging Society. He is the Program Directorof the Low-Cost Glass Interposer and Packaging Industry Consortium withmore than 25 active global industry members.

Rao R. Tummala (M’88–SM’90–F’94–LF’16)received the B.S. degree from the Indian Institute ofScience, Bangalore, India, and the Ph.D. degree fromthe University of Illinois at Urbana–Champaign,Champaign, IL, USA.

He is an IBM Fellow, pioneering the first plasmadisplay and multichip electronics for mainframesand servers. He is currently a Distinguished and anEndowed Chair Professor, and the Founding Directorof the National Science Foundation EngineeringResearch Center with the Georgia Institute of Tech-

nology, Atlanta, GA, USA, pioneering Moore’s law for system integration. Hehas authored about 500 technical papers, the first modern book Microelectron-ics Packaging Handbook (Springer, 1988), the first undergraduate textbookFundamentals of Microsystems Packaging (McGraw-Hill, 2001), and the firstbook Introduction to System-on-Package Technology (McGraw-Hill, 2008),and holds 74 patents and inventions.

Prof. Tummala is a member of the National Academy of Engineering, andwas the President of the IEEE Components, Packaging, and ManufacturingTechnology Society and the International Electronic Packaging Society. Hereceived many industry, academic, and professional society awards, includ-ing the Industry Week’s Award for improving U.S. competitiveness, theIEEE’s David Sarnoff Award, the International Microelectronics Assemblyand Packaging Society’s Dan Hughes Award, the Engineering MaterialsAward from the American Society for Metals, and the Total Excellencein Manufacturing Award from the Society of Manufacturing Engineers. Hereceived the Distinguished Alumni Awards from the University of Illinois atUrbana–Champaign, the Indian Institute of Science, and the Georgia Instituteof Technology, and the Technovisionary Award from the Indian SemiconductorAssociation and the IEEE Field Award for contributions in electronics systemsintegration and cross-disciplinary education in 2011.

544 ieee transactions on components, packaging and … · 2018-08-13 · 544 ieee transactions on...

Documents