7th International Meeting on Front-End Electronics, Montauk NY – May 18 th - 21st, 2009

Cyclic-ADC developmentsfor Si calorimeter of ILC

Laurent ROYER,

on behalf of the MicRhAu designers collaboration

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 2

"Pole" MicRhAu: collaboration for µelectronics

Laboratoire de Physique Corpusculairede Clermont Ferrand

Institut de Physique Nucléairede Lyon

12 µelectronic designers analog/mixed ASIC for physic experiments and applications (medical):

MICro-electronic RHone AUvergne

Collaboration for µelectronic designs:

Charge preamplifier Shaper, filter ADC

OTA, drivers T&H Comparators

http://

micr

hau.in2p3.fr

(still

under constr

uction)

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 3

Projects @ MicRhAu

VFE for liquid argon TPC

LHCb: preshowerALICE: dimuon triggerCMS: preshower & Ecal

INNOTEP Readout chip for PET

T2K

ILC

Readout chip for SiW Ecal

Readout chip for DHcal

Now TomorrowYesterday

S-ATLAS

S-CMS

Under discussion …STAR

Readout chip for ECG sensor

LHC

Taranis Etoile

Si detector for satellite Beam Hodoscop of PM

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 4

ADC developments @ MicRhAu

Resolution

Speed

Pipeline10 bits – 4 MS/s

35 mW

Cyclic12 bits – 0.15 MS/s

3.5 mW

0.1 MS/s

1 MS/s

10 MS/s

100 MS/s

8 bits 10 bits 12 bits6 bits

Wilkinson12 bits – 0.0125 MS/s

2.9 mW0.01 MS/s

Flash6 bits * – 20 MS/s

1 mW

Pipeline8 bits – 100 MS/s

240 mW

Flash8 bits – 50 MS/s

60 mW

* with missing codeat high dynamic range

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 5

ILC: challenges for Si-W Calorimeter

Sandwich structure of: thin wafers of silicon diodes (~200 µm) & tungsten layers

High granularity : diode pad size of 5x5 mm2

High segmentation : ~30 layers

Large dynamic range (15 bits)

0.1 MIP -> ~3 000 MIPS

Embedded Very Front End (VFE) electronics

Minimal cooling available

> 100.106 channels

Ultra-low power : 25 µW per VFE channel

Low POWERis the KEY issue(CdlT)

« Tracker electronics withcalorimetric performance »

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 6

C

AMPLI. 1

10

Fast

Shaper

Shaper

Shaper

Shaper

Chargepre-amplifier

Discri.

ANALOG

SCA

MEMORY

ANALOG

DIGITAL

TO

ADC

12 bits

channel n

TRIGGER

SCAchannel n+1

pre-amplified signal

filtered signal

ADC

12 bits

Main requirements for the ADC:– Die area:

as small as possible…

– Resolution: 12 bits with 2-gain shaping

– Time of conversion: time budget of 500 µs to convert all data of all triggered channels

– Ultra low power: 2.5 µW/ch (10% of the VFE power

budget) Memory depth of 5 0.5 µW per

conversion Power pulsing needed

VFE electronics of Si-W Ecal

Analog electronics busy

1ms (.5%)

A/D conv..5ms (.25%)

DAQ.5ms (.25%)

IDLE MODE198ms (99%)

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 7

Single or multi-channel ADC ?

Short analog sensitive wires from memory to ADC

A digital Data Bus far from sensitive analog signals

Only ADCs of triggered channels powered ON

Conversions of channels done in parallel

Integrity of analog signals saved

Power saved

Pedestal dispersion of ADC "added" to the dispersion of the analog part …. but calibrated

With one-ADC-per-channel architecture:

preamp

shaper 10

analog memory

analog memory

shaper 1

12-bit ADC

preamp

shaper 10

analog memory

analog memory

shaper 1

12-bit ADC

preamp

shaper 10

analog memory

analog memory

shaper 1

12-bit ADC

preamp

shaper 10

analog memory

analog memory

shaper 1

12-bit ADC

....

32 channels ....

preamp

shaper 10

analog memory

analog memory

shaper 1

12-bit ADC

preamp

shaper 10

analog memory

analog memory

shaper 1

12-bit ADC

preamp

shaper 10

analog memory

analog memory

shaper 1

12-bit ADC

preamp

shaper 10

analog memory

analog memory

shaper 1

12-bit ADC

....

32 channels ....D

igit

al

Data

Bu

s

Digital electronics

64-channel VFE chip

No "fast" ADC required

preamp

shaper 10

analog memory

analog memory

shaper 1

preamp

shaper 10

analog memory

analog memory

shaper 1

preamp

shaper 10

analog memory

analog memory

shaper 1

preamp

shaper 10

analog memory

analog memory

shaper 1

....

n channels ....

Dig

ital

Dat

a B

us

Digital electronics

64-channel VFE chip

12-bit ADC

MUX

analog

analog memory

analog memory

12-bit ADC

MUX

analog

analog memory

analog memory

analog memory

analog memory

analog memory

analog memory

n channels

Single-channel ADC scenario Multi-channel ADC scenario

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 8

One cycle = two phases of amplification and sampling At each cycle (one clock period), 2 bits are delivered MSB then MSB-1, …..until LSB For an n-bit ADC, n/2 cycles are required The key block: gain-2 amplifier (switched capacitors amplifier)

The precision of the gain-2 amplification gives the precision of the ADC

+

-0

VinLogic

b0 -Vref 0

DAC

x2 + x2 +Vin < -Vref ... +Vref >

Vinb0

DAC1

Vinb0

DAC2

SC Networks

Digital data processing

Final output

Conventional 2-stage Cyclic architecture

MSB MSB-1

A1 A2

A1 A2

one cycle

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 9

+ 1 redundant bit at each cycle

Precision of the ADC becomes insensitive to the offset

of the comparators up to ± 1/8 of the dynamic range (± 125mV for 2 V)

Number of comparators is doubled

1,5 bit/stage Cyclic architecture

+

-

+

--Vref/4

Vref/4

VinLogic

b0 b1-Vref

0+Vref

DAC

x2 + x2 +

Vinb0, b1

DAC1

Vinb0, b1

DAC2

SC Networks

Digital data processing

Final output

Vin < -Vref ... +Vref >

2 2

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 10

Enhanced architecture: "Flip-around amplifier "

A single amplifier shared by the two stages As main of the power is consumed by amplifier reduction of power up to 40%

x2 + +Vin

Vinb0, b1

DAC1

Vinb0, b1

DAC2

SC Networks

D igita l data processin g

2

x2+ +Vin

Vinb0, b1

DAC1

Vinb0, b1

DAC2

SC Networks

2

Phase 1 Phase 2

D igita l data processin g

MSB MSB-1

A A

one cycle

A A

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 11

1 MHz clock

C2

AMPLIFIER

C4

VREF1

bit1_H

bit1_L

VTH_H

VTH_LVREF2DAC

PHASE 1

Sampling

Amplification

clk+

VTH_H

VTH_L DACclk-

C2

AMPLIFIER

C4

VTH_H

VTH_L DAC

PHASE 2

Sampling

Amplification

clk+

bit2_H

bit2_L

VTH_H

VTH_LVREF1DACclk-

VREF2

"Start conversion " signal

1 2 3

4

56

11

10

12

8

97

Output signal of the amplifier

Two phases of conversion with a single amplifier

Enhanced architecture: "Flip-around amplifier "

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 12

The cyclic ADC designed

Clock frequency: 1MHz

Supply voltage : 3.5V

Technology: 0.35 µm CMOS Austriamicrosystems (reliable and cheap !!)

ADC designed with the validated building blocks (Amplifier & Comparator) of a 10-bit pipeline ADC (published in IEEE NSS in June 08) but optimized for the 12-bit precision requirement

Power pulsing system implemented

Digital process of the bits (1.5 bit/stage algorithm) performed by an external FPGA

Fully differential ADC: analog signal, reference, clock…

Die area of the core = 0.175mm2

"Fully-Differential Circuits have very good PSRR and cross-talk rejection" "Fully-Differential Circuits have very good PSRR and cross-talk rejection" Michael K. … and also a good rejection of common mode noise induced by Michael K. … and also a good rejection of common mode noise induced by digital electronicsdigital electronics

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 13

Comparator

Measured performance Sensitivity = input noise : < 280 µV (95% C.L.)

Offset: 20mV ± 9 mV (68 % C.L.) far from the ± 125 mV tolerated by the 1.5bit/stage architecture

Comparator Fully differential latched architecture Power consumption: 280µW

CLOCK

Latched comparator

V+in-V+

ref Sw

+3.5V

+3.5V

OUT

OUT

Dynamic memory

V-in-V-

ref

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 14

AmplifierAmplifier

Fully differential and rail-to-rail 2 amplification stages Resistive CMFB Power consumption: 2870 µW Capacitive load (feedback + sampling):

3 x 0.8pF

Requirement@ 12 bits/1MHz

Performance

Open LoopDC Gain

16k 19.6k

Fc à -3dB 174 Hz 2,5 kHz

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 15

Charge injection: Bottom plate sampling

S1 remains ON, S2 turns OFF • Ground impedance smaller than1/j(CF+CS)

charges mainly injected to the ground

• Residual charge is constant and cancelled by differential structure of the gain-2 amplifier

S1 turn OFF, S2 remains OFF• Input (Vin) impedance smaller than 1/j(CP+CJ)

charges mainly injected back to the input

VinCF

Cs

S1

S1

S2

CF

Cs

S1

S1

CP

CJ

CJ

VinHardware delay introduced betweencontrol signals of S1 & S2 gates

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 16

Measurement setup for ADC

Test Bench: Generic board for ADC tests Analogue signal generator: DAC 16 bits (DAC8830)

PC/LabView Slow Control through USB interface Data processing with Scilab package

Chip under testUSB link

Static measurements : Input ADC signal: ramp from 0 to 2V > 4096 steps -- 50 measurements / step

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 17

Power pulsing measurement

Master current sourcesswitched OFF

1 µs for recovery time included after power ON

Measurement of consumption with duty cycle power ON/OFF

Integrated consumptionwith ILC timing : 0.12 µW per conversion

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 18

Measurements of the performance

But Yield ≈ 60% designed of a new "process-hard" gain-2 amplifier

Differential Non-Linearity

Noise

Integral Non-Linearity

DNL<+/-1 LSB No missing code

Standard deviation = 0.84 LSB (420µV)

INL<+/-1 LSB

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 19

New designs

4 new ADC with 4 new amplifiers designed and submitted to foundry

in March Reduction of power supply voltage: 3.5V to 3.0V and optimization

(reduction) of BW performance of the amplifier Improvement of the yield: reduction of biasing variation versus

process fluctuation single stage amplifier

Layout of the chip submitted in March 09

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 20

CMFB

+3V

+3V

VMC

Out1 Out2

Out1 Out2

Vin1 Vin2M1 M2

M0

M3 M4

M5

M10M9

M8M7

M6

Vb0

Io

Io

T0

T1

T3

Io

Io

T2

T5T4 T6

T8

T7

VMC VMC

+3V

+3V

Out1 Out2

Vin1 Vin2M1 M2

M0

M3 M4

M5

M10M9

M8M7

M6

Vb0

Io

Io

T0

Io

Io

VMC VMC

Out1 Out2

VMC

Out1 Out2 Out1 Out2

T0

New Amplifiers

Folded cascode structure Current CMFB (reduced

consumption)

Folded cascode structure Voltage CMFB

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 21

CMFB

+3V

+3V

VMC

Out1 Out2

Out1 Out2

Vin1 Vin2M1 M2

M0

M3 M4

M5

M10M9

M8M7

M6

Vb0

Io

Io

T0

T1

T3

Io

Io

T2

T5T4 T6

T7

VMC VMC

New Amplifiers

Folded cascode structure

(different sizing of transistors) Voltage CMFB

Boosted folded cascode

structure Voltage CMFB

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 22

Architecture CMFBDC Gain

Consum. BW

Folded cascode Voltage 23 k 570 µW 436 HzFolded cascode Current 23 k 450 µW 318 Hz

Boosted Folded cascode Voltage 22 k1470

µW1700

Hz

Folded cascode Voltage 28 k1020

µW428 Hz

New Amplifiers performance

Previous amplifier consumption: 2870 µW

Simulated INL of the 4 new ADC

> 174Hz required

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 23

Summary

Measured performance in accordance with Si-W ECAL VFE

requirements Time conversion = 7µs

Consumption < 0.6µW per channel (analog memory depth of 5 and power

pulsing included)

2.5% of the power budget of one VFE channel

Linearity: DNL < +/1 LSB & INL < +/-1 LSB

Standard deviation of Noise < 0.9 LSB

Improvement of consumption and of the yield expected with the design

of the new amplifiers chips have to be tested (received last week)

The acquired experience with this cyclic ADC can be exported to other

project and/or to faster pipeline architecture

L.ROYER – FEE 09 @ Montauk – May 18-21, 2009 24

A cyclic "machine" ??

Thank you for your attention !!