8-channel a/d & d/a zynq ultrascale+ rfsoc processor - 3u vpx · integrator block diagrams, all...

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8-Channel A/D & D/A Zynq UltraScale+ RFSoC Processor -3U VPXModel 5950

General InformationThe Quartz Model 5950 is a high-per-

formance 3U OpenVPX board based on theXilinx Zynq UltraScale+ RFSoC FPGA. TheRFSoC integrates eight RF-class A/D andD/A converters into the Zynq’s multipro-cessor architecture, creating a multichanneldata conversion and processing solutionon a single chip. The Model 5950 bringsRFSoC performance to 3U VPX with acomplete system on a board.

Complementing the RFSoC’s on-chipresources are the 5950’s sophisticatedclocking section for single board and multi-board synchronization, a low-noise frontend for RF input and output, up to 18 GBytesof DDR4, a PCIe interface, a gigabit serialoptical interface capable of supporting dual100 GigE connections and general purposeserial and parallel signal paths to the FPGA.

Board ArchitectureThe 5950 board design places the

RFSoC as the cornerstone of the architec-ture. All control and data paths areaccessible by the RFSoC’s programmablelogic and processing system. A full suiteof Pentek developed IP and softwarefunctions utilize this architecture to pro-vide data capture and processingsolutions for many of the most commonapplication requirements. For many ap-plications the Model 5950 can be usedwith simply the built-in functions, requir-ing no FPGA IP to be developed.

Extendable IP DesignFor applications that require specialized

functions, users can install their own cus-tom IP for data processing. The PentekNavigator FPGA Design Kits (FDK) includethe board’s entire FPGA design as a blockdiagram that can be edited in Xilinx’sVivado IP Integrator. In addition to the IPIntegrator block diagrams, all source codeand complete IP core documentation isincluded. Developers can integrate theirown IP along with the Pentek factory-in-stalled functions or use the Navigator kit tocompletely replace the Pentek IP with theirown.

The Navigator Board Support Package(BSP), the companion product to the Navi-gator FDK, provides a complete C-callablelibrary for control of the 5950’s hardwareand IP. The Navigator FDK and BSP librariesmirror each other where each IP function iscontrolled by a matching software func-tion, simplifying the job of keeping IP andsoftware development synchronized.

The Navigator BSP includes support forXilinx’s PetaLinux running on the ARMCortex-A53 processors. When runningunder PetaLinux, the Navigator BSP librar-ies enable complete control of the 5950either from applications running locally onthe ARMs, or using the Navigator API,control and command from remote sys-tem computers.

A/D Converter StageThe front end accepts analog IF or RF

inputs on eight front panel MMCX connec-tors with transformer-coupling into the RFsignal chain of the RFSoC. Inside theRFSoC, the analog signals are routed toeight 4 GSPS, 12-bit A/D converters. Eachconverter has built-in digital downconverterswith programmable 1x, 2x, 4x or 8x deci-mation and independent tuning. The A/Ddigital outputs are delivered into theZynq’s programmable logic and processorsystem for signal processing, data captureor for routing to other resources.

In addition to the A/D’s built-in decima-tion, an additional stage of IP baseddecimation provides another 16x stage ofdata reduction, ideal for applications thatneed to stream data from all eight A/Ds.

D/A Converter StageThe RFSoC’s eight D/A converters ac-

cept baseband real or complex data streamsfrom the FPGA’s programmable logic.Each 6.4 GSPS, 14-bit D/A includes a digitalupconverter with independent tuning andinterpolations of 1x, 2x , 4x and 8x. EachD/A output is transformer coupled to afront panel MMCX connector.

Clocking and SynchronizationThe 5950 front panel includes inputs for

sample clock, reference clock, referencesync and gate/trigger. In addition to thefront panel, these same signals are alsoavailable on the VPX P2 connector for dis-tribution through the backplane.

The on-board timing bus generatoruses these signals, in addition to a fre-quency synthesizer, to create the requiredA/D and D/A clocks and a SysRef for op-eration of the data converters. The timingbus generator supports an internal clockmode where the sample clock is driven bythe programmable frequency synthesizerand no additional clock needs to be pro-vided. In an alternate mode, the on-boardsample clock can be synchronized to a10 MHz reference clock received eitherthrough a front panel connector or theVPX P2 connector. The Model 5950 can

Features■ Supports Xilinx Zynq

UltraScale+ RFSoC FPGAs

■ 18 GB of DDR4 SDRAM■ On-board GPS receiver■ PCI Express (Gen. 1, 2 and 3)

interface up to x8■ LVDS connections to the

Zynq UltraScale+ FPGA forcustom I/O

■ Optional VITA-66.4 opticalinterface for backplanegigabit serial communication

■ Dual 100 GigE UDPinterface

■ Compatible with severalVITA standards including:VITA-46, VITA-48, VITA-66.4, VITA-57.4 and VITA-65(OpenVPXTM SystemSpecification)

■ Ruggedized and conduction-cooled versions available

■ Unique QuartzXM eXpressModule enables migration toother form factors

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also accept an external sample clockthrough a front panel connector orthrough the VPX P2 connector. This modebypasses the on-board sample clock.

A multi-function gate/trigger input isavailable on the front panel as well as theVPX P2 connector for external control ofdata acquisition and playback.

Expandable I/OThe Model 5950 supports the VITA-66.4

standard providing up to eight 28 Gb/secfull duplex optical lanes to the backplane.With the built-in 100 GigE UDP interfaceor installation of user provided serial pro-tocol, the VITA-66.4 interface enablesgigabit communications between boardsindependent of the PCIe interface.

12 pairs of LVDS connections are pro-vided between the FPGA and the VPX P2connector for custom I/O.

Memory ResourcesThe 5950 architecture supports a

10 GByte bank of DDR4 SDRAM memoryaccessible from the Programmable Logic.User-installed IP, which, along with thePentek supplied DDR4 controller corewithin the FPGA can take advantage of thememory for custom applications.

An 8 GByte bank of DDR4 SDRAM isavailable to the Processing System as pro-gram memory and storage.

PCI Express InterfaceThe Model 5950 includes an industry-

standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the module.

GPSAn optional GPS receiver provides time

and position information to the FPGA andARM processors. This information can beused for precise data tagging. The GPSprovides a 1 PPS and 10 MHz referenceclock to the FPGA.

Rear Transition ModuleThe Model 5901 RTM compliments the

5950 by providing rear backplane access tostandard interfaces including: JTAG, USB 3,1 GigE, DisplayPort and RS-232. The RTMalso includes Pentek’s μSync connector forsynchronizing multiple boards, and a gen-eral purpose FPGA I/O connector thatprovides access to 12 LVDS pairs from theFPGA.


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Optimized IPXilinx has created an integrated processing solution in the RFSoC that is unprecedented. The key to unlocking the po-

tential of the RFSoC is efficient operation using optimized IP and application software. Pentek helps streamline theprocess from development to deployed application by providing a full suite of built-in functions. These address the dataflow and basic processing needed for some of the most common applications. For each example that follows the board’sincluded IP is all that is needed to demonstrate the application and may satisfy the full set of requirements for any particu-lar application. These applications can also be the starting point for adding additional IP from the Pentek Navigator IPlibrary or for adding custom IP.

Example Application 1 - Digital RF Memory (DRFM)A common requirement for countermeasures applications is a Digital RF Memory (DRFM). The DRFM must be able to effec-

tively create a programmable delay between the analog signal received by the A/D and the same analog signal output bythe D/A. In all cases the delay time must be deterministic and very often a short interval. The RFSoC’s on-chip A/Ds andD/As use low-latency parallel interfaces to transfer data between the converters and the Programmable Logic, ideal forimplementing these types of delays with on-chip memory. The 5950’s DRFM function provides a programmable delayfrom 1 to 32768 data samples.

Example Application 2 - High Bandwidth Data StreamingThe RFSoC’s eight 4 GSPS A/Ds are capable of producing an aggregate data rate of 64 GBytes/sec when all channels are enabled.

While capturing this much raw data is not feasible, the A/Ds built-in digital down converters can reduce this data throughput in manyapplications to a rate reasonable for the data streaming and storage components downstream in the system.

In some applications capturing the raw, full bandwidth data is crucial. The 5950’s dual 100 GigE UDP engine provides a highbandwidth path for moving data off of the board. Along with the built-in data acquisition IP, the 5950 can stream two full band-width A/D data streams over optical cable to a downstream storage or processing subsystem.


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Example Application 3 - Waveform and Radar Chirp GeneratorThe 5950’s IP includes a flexible waveform generator engine. Multiple waveforms can be loaded into the 5950’s DDR4 SDRAM

through the PCIe interface. These waveforms can then be output through the D/As based on user programmed sequences and trig-gers. In an alternate mode, waveforms can be streamed directly to the D/As via the 100 GigE interface.

The 5950 also includes a chirp generator ideal for radar applications. Chirp parameters like length, frequencies and sweep can beprogrammed and triggered by the front panel trigger input or through a software command.

Example Application 4 - Multi-mode Data Acquisition SystemIn some applications multiple data acquisition modes may need to be operated at the same time. A required dataflow could be full

bandwidth streaming of a single A/D channel over 100 GigE to a data recorder while another channel of A/D data is stored assnapshots in the boards DDR4 SDRAM and read by the ARM processor while yet other A/D channels are down converted us-ing the A/Ds’ built-in DDCs and streamed over PCIe. The 5950 provides these modes with built-in IP supporting complex datastreaming scenarios without the need for creating custom IP.


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Flexible Modular DesignWhile the Model 5950 follows the form

factor of a standard 3U OpenVPX board,the unique modular design of Pentek’sModel 6001 QuartzXM eXpress Moduleprovides the flexibility to deploy this solu-tion in many different situations. Theheart of the QuartzXM is a system onmodule containing all of the key compo-nents including the RFSoC FPGA, DDR4SDRAM, and power and clock manage-ment.

In the case of the 5950 the QuartzXM ismounted on a 3U OpenVPX carrier whichcomplements the design with a timing busgenerator, analog signal conditioning, aGPS receiver and an 8x 28 Gbps opticaltransceiver. As a module and carrierboard set, the 5950 becomes a complete,ready to deploy 3U OpenVPX solutionavailable for a range of operating environ-ments from commercial to rugged andconduction cooled.

The Model 6001 QuartzXM can also bemounted on other carriers available fromPentek to support standard form factors,or for applications that require a non-stan-dard footprint, Pentek supports themodule with a design kit for users to engi-neer and build their own custom carrier.As a complete and tested module, theQuartzXM encapsulates best in class electri-cal and mechanical design, eliminatingsome of the most challenging aspects ofembedded circuit design and allowing theuser to focus on the application specificcarrier design.

Specifications - Model 5950Field Programmable Gate Array

Xilinx Zynq UltraScale+ RFSoCXCZU27DR-1Option -002: XCZU27DR-2, -2 speedgrade

RFSoC RF Signal ChainFront Panel Analog Inputs:

Quantity: 8Connectors: MMCXInput Type: Transformer-coupledTransformer Type: Mini-CircuitsTCM1-83X+Full Scale Input: +4 dBm into 50ohms (includes matching network)3 dB Passband: 10 MHz to 4000MHz

A/D Converters:Quantity: 8Sampling Rate: 4.0 GHzResolution: 12 bits

Digital Downconverters:Quantity: 1 per A/DDecimation Range: 1x, 2x, 4x and8xLO Tuning Freq. Resolution:48 bits, 0 to ƒsFilter: 80% pass band, 89 dBstop-band attenuation

Front Panel Analog Outputs:Quantity: 8Connectors: MMCXInput Type: Transformer-coupledTransformer Type: Mini-CircuitsTCM1-83X+Full Scale Output: +4 dBm into 50ohms3 dB Passband: 10 MHz to 4000MHz

D/A Converters:Quantity: 8Sampling Rate: 6.4 GHzResolution: 14 bits

Digital Upconverters:Quantity: 1 per D/AInterpolation Range: 1x, 2x, 4x and8xLO Tuning Freq. Resolution: 48 bitsFilter: 80% pass band, 89 dBstop-band attenuation

Sample Clock Source: On-board pro-grammable clock source or extrenalclock source received on front panelMMCX connector or on VPX-P2Reference Clock, Reference Sync andGate/Trigger: Received on front panelMMCX connectors or on VPX-P2

RFSoC RF Processing SystemARM Cortex-A53:

Quantity: 4Speed: 1.5 GHz

ARM Cortex-R5:Quantity: 2Speed: 600 MHz

Custom FPGA I/OParallel: 12 pairs of LVDS connectionsbetween the FPGA and the VPX P2 con-nector for custom I/OOptical (Option -110): VITA-66.4, 8Xfull duplex lanes @ 28 Gb/sec

MemoryProcessing System:

Type: DDR4 SDRAMSize: (standard) 4 GBytes;

Option 150: 8 GBytesSpeed: 1200 MHz (2400 MHz DDR)

Programmable Logic:Type: DDR4 SDRAMSize: (standard) 5 GBytes;

Option 150: 10 GBytesSpeed: 1200 MHz (2400 MHz DDR)


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PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4 or x8;

EnvironmentalStandard: L0 (air cooled)

Operating Temp: 0° to 50° CStorage Temp: –20° to 90° CRelative Humidity: 0 to 95%, non-condensing

Option -702: L2 (air cooled)Operating Temp: –20° to 65° CStorage Temp: –40° to 100° CRelative Humidity: 0 to 95%, non-condensing

Option -763: L3 (conduction cooled)Operating Temp: –40° to 70° CStorage Temp: –50° to 100° CRelative Humidity: 0 to 95%, non-condensing

Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)OpenVPX Compatibility: The Model 5950

is compatible with the following moduleprofile, as defined by the VITA 65OpenVPX Specification:

SLT3-PAY-2F1F2U1E-14.6.6-1

Ordering InformationModel Description

5950 8-Channel A/D & D/AZynq UltraScale+ RFSoCProcessor - 3U VPX

Options:

-002 -2 FPGA speed grade,-1 standard

-110 VITA-66.4 8X opticalinterface

-150 8 GBytes processorsystem memory, 10GBytes programmablelogic memory

-180 GPS support

-702 Air cooled, Level L2

-763 Conduction cooled,Level L3

Model Description

5901 Rear Transition Module -3U VPX

Option:

-950 Support for Model 5950

Model Description

8257 1-Slot 3U VPXDevelopment ChassisSee 8257 Datasheet forOptions

Specifications - Model 5901 RTMRear Panel Connections:

USB 3:Connector Type: Type-AQuantity: 1

1 GigE:Connector Type: RJ45Quantity: 1

DisplayPort:Connector Type: Mini DisplayPortQuantity: 1

RS-232:Connector Type: Micro USBQuantity: 1

Sync Bus:Connector Type: μSyncQuantity: 1Signals: Sample Clock, ReferenceClock, Reference Sync,Gate/Trigger

FPGA GPIO:Connector Type: 50-pin SMCQuantity: 1Signals: 12 LVDS pairs

Additional Connections:JTAG:

Connector Type: 2x7 pin, 2mm pitchheader, Xilinx JTAG standard pin-outQuantity: 1

Model 8257The Model 8257 is a 1-Slot

3U VPX chassis. Offered as aconvenient, low cost solutionfor hosting the 5950, it includespower and cooling to match the5950’s requirements in a por-table desk top package.

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8-channel a/d & d/a zynq ultrascale+ rfsoc processor - 3u vpx · integrator block diagrams, all...

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