PROMISE OF TUNNEL DIODEINTEGRATED CIRCUITS

Alan SeabaughDepartment of Electrical Engineering

University of Notre DameNotre Dame, IN

Acknowledgements: P. Barrios, B. Bate, P. Berger, T. Blake,B. Brar, T. Broekaert, K. Clark, M. Dashiell, X. Deng, W. Frensley,

G. Frazier, J. Gunther, J. Hellums, K. Hobart, W. Kirk,J. Kolodzey, R. Lake, J. Lyding, E. Maldonado, C. Marrian,

P. Mazumder, T. Moise, F. Morris, G. Pomrenke, S. Rommel,G. Spencer, P. Thompson, T. Troeger, P. van der Wagt, G. Witt.

A. Seabaugh, Promise of Tunnel Diode Integrated Circuits, Tunnel Diode and CMOS/HBTIntegration Workshop, December 9, 1999, Naval Research Laboratory, Washington, DC.

THE p+n+ TUNNEL DIODEHigh speed, multivalued I-V, with negative differential resistance

n p

depletion region

EC

EVEF

-0.05

0

0.05

0.1

0.15

-0.25 0 0.25 0.5 0.75

Cur

rent

(m

A)

Voltage (V)

1N2927 Si tunnel diode

Si Plot 1

300 K

Scanning electron micrographs of a Si 1N2927(no longer sold, Microsemi Corp., CA)

70 m

20 m

The demise of the tunnel diode [in the 1960s] was signaled by the arrival in force of theSwartz, In perspective: the tunnel diode, 1986 IEEE Int. Solid-State

Circuits Conf., pp. 278-280. Until recently, processes for forming tunnel diodes were still basedon the discrete approach shown above.

MAIN POINTS

Circuit simulations using tunnel diodes (TD) show benefit

RTD/HEMT technology shows feasibilty

Silicon TDs now demonstrated: Matsushita, Toshiba, U. Delaware,NRL, Raytheon, Hughes, Max-Planck Institute

Time is right to add TD to silicon bipolar and MOS

Relatively low risk

High benefit/cost

Figure 1. Circuit schematic diagrams for (a) RTD/HEMTand (b) HEMT comparators designed for 25 GHzoperation.

A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, Resonant-Tunneling Mixed-Signal Circuit Technology, Solid State Electronics 43 (1999) 1355-1365.

CIRCUIT DESIGNS SHOWTD PERFOMANCE BOOST

SPICE models: 18c07 0.25 mm CMOS and resonant tunneling diode modelsfit to both dc and S-parameter measurements

TD in combination with CMOS reduces the number of devices,interconnects, and delay stages

TD improves area, speed, and power by the following factors:Area Speed Active Power Static Power

Embedded RAM: vs. 6T 2.2x (3x) - 8x vs. 1T (1.4x) same - 23xLatches, flip flops, and

shift registers1.6-3x 1.7-2.2x 2.1-2.4x (1.1-1.7x)

Dynamic logic andpass-transistor logic

1.3-1.4x 1.2-2.3x 1.5-1.8x same

Quantizers 3.5x 2.2x 5.8x 2.3x( ) performance reduction

Numbers which are not in parenthesis represent improvements obtained using the tunnel diode,e.g. in line 1, the tunnel diode embedded RAM occupies 2.2x less area than the 6T cell and

dissipates 8x less standby power, while numbers in parenthesis indicate a performance reduction,e.g. again in line 1, 3x slower access speed for the TD circuit vs the 6T SRAM.

A. Seabaugh, X. Deng, T. Blake, B. Brar, T. Broekaert, R. Lake, F. Morris, and G. Frazier,Transistors and Tunnel Diodes For Analog/Mixed-Signal Circuits and Embedded Memory,IEDM Technical Digest 1998, pp. 429-432

Tunnel Diode For Embedded Memory

I1I2I3

I2+I3

I3 TD1 I1

I2TD2BL

1V

WL

0V

0V

NODE VOLTAGE (V)

CU

RR

EN

T (

pA

)

0

4

8

12

16

0 0.4 0 .8

(a) (b)Fig. 3: CMOS/TD SRAM cell: (a) schematic diagramand (b) current-voltage relations.

TABLE 1COMPARISON OF CMOS/TD SRAM CELLS WITH CMOS

EMBEDDED DRAM AND 6T SRAM

ProcessCell

Area(mm2)

DensityRatio(x6T)

CycleTime(ns)

StandbyCurrent

(pA)CMOS 6T

SRAM7.00 1.0 4 7

CMOS 1T+1CgDRAM

5.79 1.2 18 31

CMOS+TD

1T+1Cg+2TDSRAM

7.02 1.0 18 3

CMOS+Cap

1T+1CstDRAM

2.26 3.1 12 21

CMOS+Cap+TD

1T+1Cst+2TDSRAM

3.15 2.2 12 0.9

A. Seabaugh, X. Deng, T. Blake, B. Brar, T. Broekaert, R. Lake, F. Morris, and G. Frazier,Transistors and Tunnel Diodes For Analog/Mixed-Signal Circuits and Embedded Memory,

IEDM Technical Digest 1998, pp. 429-432

TD-Simplified Keeper Circuit

OUT

CK

INOUT

CK

CK

IN

VD DVD D

CK

(a) (b)

Fig.6: Static shift register comparison: (a) CMOS/TDand (b) CMOS only.

A. Seabaugh, X. Deng, T. Blake, B. Brar, T. Broekaert, R. Lake, F. Morris, and G. Frazier,Transistors and Tunnel Diodes For Analog/Mixed-Signal Circuits and Embedded Memory,IEDM Technical Digest 1998, pp. 429-432.

0 200 400 600 800 10000

0.01

0.02

0.03

0.04

0.05

OU

T (

V)

TIME (ps) 3771trtf plot

Figure 19. Resonant tunneling diode clock generator: (a)schematic diagram and (b) 6.5 GHz output signal

waveform.A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, Resonant-Tunneling Mixed-Signal Circuit Technology, Solid State Electronics 43 (1999) 1355-1365.

Figure 6. Scanning electron micrograph of a completedRTD/HEMT quantizer circuit showing the three-dimensional integration of RTDs on HEMT source anddrain contact regions.

A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, Resonant-Tunneling Mixed-Signal Circuit Technology, Solid State Electronics 43 (1999) 1355-1365.

WHAT ARE THE RISKS

No new materials

Similar to adding resistor, capacitor, or diode

Key technical challenges:

Milestones Risk

Low High

Demonstrate production compatible tunnel diode (TD) vDemonstrate TD uniformity v

Demonstrate TD reproducibility v

Demonstrate TD reliability v

BENEFITS FROM SUCCESSFULIMPLEMENTATION OF Si TD

1. Extends life of existing facilities by increasing circuit performance without scaling

2. Provides a technology differentiator, like low k, or Cu interconnect

QMOS ROADMAP

Integration of the quantum device (tunnel diode) with CMOS iscalled QMOS.

1

10

100

1000

1996 1999 2002 2005 2008 2011

Cos

t (uc

/dev

ice)

Del

ay x

Pow

er (f

J/de

vice

)

Silicide,Localinterconnect

CuLow k

SOI?

QMOS?

702009

Feature SizeProduction Year

1502001

1002006

2501997

1801999

1302003

502012

1000

10

10

1

No known solutions - SIA 97

Datapoints: SIA National Roadmap, 1997 Ed.

1 logic function = 4 devices in CMOSLines: qualitative

CONCLUSIONSCircuit simulations using tunnel diodes (TD) show benefit

RTD/HEMT technology shows feasibilty

Silicon TDs now demonstrated: Matsushita, Toshiba, U. Delaware,NRL, Raytheon, Hughes, Max-Planck Institute

Time is right to add TD to silicon bipolar and MOS

Relatively low risk

High benefit/cost