MIXED SIGNAL LETTER

A 0.5–1 GHz single stage linear-in-decibel VGA with 80 dB gainrange in 0.18 lm CMOS

Masoud Ayat • Behjat Forouzandeh •

Samad Sheikhaei

Received: 27 April 2013 / Revised: 19 September 2013 / Accepted: 22 September 2013

� Springer Science+Business Media New York 2013

Abstract Communication systems require a wide gain

range. For example the code-division multiple access sys-

tem (CDMA) requires more than 80 dB of gain range so

that, many variable gain amplifiers (VGAs) must be used,

resulting in high power consumption and low linearity

because of VGA non-linearity factors. In this paper, a one-

stage VGA in 0.18 lm technology is presented. The VGA

based on the class AB power amplifier is designed and

simulated for a high linearity and an 80 dB tuning range.

For the linear-in-decibel tuning range, transistors in sub-

threshold region is used. The current control circuit of the

VGA changes gain continuously from -68 to 18 dB at

0.5 GHz and -60 to 20 dB at 1 GHz with gain error of less

than 2 dB. The power consumption enjoys a highest value

about 13.5 mW in the maximum gain and P1dB is also

about -3.4 dBm at 0.5 GHz and 2.2 dBm at 1 GHz.

Keywords VGA � Linear-in-decibel � Linearity

1 Introduction

Using CMOS-based circuits for wireless communication

recently have widely grown. Low cost and power con-

sumption and high integration allows designers to implement

low power and low cost single chips. As known, power

amplifiers (PAs) are critical blocks in transmitters. The

output power, linearity and efficiency are the significant

factors in the PA performance. If non-constant envelop sig-

nal enters PA, non-linearity effects distort the signals. PAs

have a proper operation under saturated power. The below

saturated power region, inter-modulation distortion (IMD)

does not lead to distorted signals. However the PA in the

saturated power offers the maximum efficiency. As a result,

using the variable gain amplifier (VGA) before the PA is

necessary for improving linearity, efficiency and output

power. The PA output detection is illustrated in Fig. 1. It can

be seen from Fig. 1 that the control circuit will be complex, if

the VGA is non-linear. One of the most Important charac-

teristics of the VGA is that the gain must be an exponential

function of the control signal. However this exponential

relation is not easily obtained in CMOS technology owing to

the square-law I–V characteristic of CMOS transistors in

saturation and linear mode operation.

2 Related work

VGAs are categorised according to the control circuit into

Analog and digitally controlled.

2.1 Digitally controlled VGA

The digitally controlled VGA is simpler than analog, such

that simplicity of the VGA leads to decrease in the sizes

and lower area. In [12], in order to obtain linear-in-decibel

gain and a wide gain range , the transistor sizes are changed

and the amplifying blocks in cascade are used respectively.

The shortcomings are low one-stage gain range and low

frequency. In [19], The gain is varied by tuning the resis-

tors. The positive point is the small gain error. In contrast,

low frequency and low gain range are the drawbacks.

M. Ayat (&) � B. Forouzandeh � S. Sheikhaei

Nanoelectronics Center of Excellence, School of Electrical and

Computer Engineering, College of Engineering, University of

Tehran, Tehran, Iran

e-mail: masood.ayat@ut.ac.ir

B. Forouzandeh

e-mail: bforooz@ut.ac.ir

123

Analog Integr Circ Sig Process

DOI 10.1007/s10470-013-0185-9

2.2 Analog controlled VGA

The analog controlled VGA reduces the large number of

control bits required in digitally controlled VGAs. Next

and foremost, for a code-division multiple access (CDMA)

system requiring a power control rang larger than 80 dB,

VGA with continuously variable gains is preferred because

it avoids phase discontinuity [13]. The VGA circuits based

on various technologies such as bipolar, BiCMOS, and

CMOS have been introduced in the literature [3, 17, 21].

Recently however, CMOS VGAs are preferred due to the

low cost and easy integration with other CMOS analog and

digital parts. An important requirement for a CMOS VGA

is a decibel-linear gain control characteristic, where the

gain of the VGA changes exponentially with the control

signal. Although a transistor operating in a sub-threshold

region has an exponential characteristic, it is generally not

preferred due to other unfavorable effects such as band-

width [25].

Another possible method is to use parasitic bipolar

transistors to generate the desired exponential function.

This is strongly dependent on the temperature [5, 13].

Using Taylor Concept is the common method to get the

exponential gain control. In this method, ex is estimated by

polynomial functions produced by CMOS. The more near

to exponential the equations, the higher is the range

variations.

In some works, fractional functions are used to model

the exponential functions. In [4, 6], this simple function1þax1�ax

is employed to achieve a 12 dB gain range with 0.5 dB

error. Reference [16] has utilized an analog multiplier to

reduce the power consumption and supply voltage. It is

while if one of the inputs changes exponentially, this

multiplier converts to a linear in decibel VGA. The

employed circuit in this work uses the circuit current

division for modeling the function. The work has 30 dB

gain range. Therefore, to increase the gain range, the better

approximation for the exponential function seems to be

necessary. Although this kind of functions improves the

gain range, complex circuits increase the error. The

functionkþð1þaxÞ2

kþð1�axÞ2 used in [14] and [3], produce 60 and

35 dB gain range with 1 and 0.5 dB error respectively. The

Taylor series are also utilized as polynomial expressions. In

[11] and [2] an exponential current generator approximates

the exponential function with k(1 ? (1 ? ax)2) and the

gain ranges are obtained 17 and 15 dB.

As can be seen from Fig. 2. The polynomials are

strongly sensitive to the coefficients whereas the small

changes result in a large reduction in the gain range. A

control signal converter used in the special current control

region enjoys exponential gain which shows the gain var-

iation range of 26 dB in a single-stage VGA [22].

3 Topology concept

As can be seen in Fig. 3, if the VGA gain logarithmically

change with respect to the exponential control voltage, can

give rise to the linear-in-decibel changes. Therefore gm

must have an exponential characteristics. Hence two cir-

cuits, one for logarithmic gain as the VGA core and the

other to generate exponential voltage are used.

3.1 VGA

The current of CMOS in linear region is expressed in

Eq. 1.

Id ¼ kn

W

LVGS � vTHð ÞVDS½ �; VDS � 1 ð1Þ

from (2) gm can be achieved.

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2−40

−30

−20

−10

0

10

20

30

40

X

f(x)

k=0.4

k=0.45

k=0.5

k=0.55

Fig. 2 Plots of Taylor series approximation equations for different

values of k in [3]

Complex Power Detector

VGA

PA

Fig. 1 PA with an amplitude control circuit

Analog Integr Circ Sig Process

123

gm ¼oId

oVGS

¼ lnCox

W

L

� �� VDS ð2Þ

According to (2), the gain changes exponentially when the

VDS is swept exponentially. To change drain-source voltage

exponentially, a transistor in sub-threshold region is used.

Equation 3 expresses the MOS current in sub-threshold

region.

Id ¼W

LleC�ox

kT

q

� �2

n� 1ð ÞeqðVGS�VTH Þ=nkT ð3Þ

As shown, the Id changes exponentially in terms of the VGS.

From (2) and (3), Eq. 4 can be concluded.

vejðVGS�VTHÞ ¼ nVGS;VTH� VDS ð4Þ

The proposed circuit to generate logarithmic gain is shown

in Fig. 4. It can be seen that the input and cascode

transistors are in the triode and the sub-threshold region,

respectively. Equation 5 illustrates the relation between the

VGS of the cascode transistor and the VDS of the input

transistor.

vejðVControl�VDÞ ¼ n� VD ð5Þ

In Eq. 5, Vcontrol and VD are the gate voltage of the cascode

transistor and the drain voltage of the input transistor

respectively. In Fig. 5, VD versus VControl given in (5) is

illustrated. The change has a linear relation. Hence (5) can

be converted to (6).

VD ¼ f� VControl ð6Þ

where f is a constant. Equation 6 shows that the expo-

nential increase of VControl leads to exponential increase of

VD. Therefore the gain changes as linear-in-decibel. In

Fig. 6, the logarithmic gain is compared with the ideal state

in which the control voltage rises from 0.1 to 1.6 V. In

regard to the voltage over 0.8 V, the input transistor exits

from the triode region and increases the error. Since the

control voltage above 0.8 V increases the error, the

Control Circuit

VGA

Fig. 3 Block diagram of the proposed VGA

Sub-ThersholdRegion Transistor

Fig. 4 Schematic diagram of the proposed VGA core based on the

class AB power amplifier Fig. 5 Drain voltage (VD) versus VControl of Eq. 5

Analog Integr Circ Sig Process

123

maximum gain is considered about 20 dB, however The

gain range is commonly about 130 dB.

3.2 The exponential voltage converter

For producing an exponential form of VControl, the expo-

nential converter (Fig. 7) is employed [15]. In the figure,

iOUT is given as [18]

v3 ¼v1 þ v2

2¼ vTH þ

1

2

ffiffiffiffiffiffi2i0p

kþ

ffiffiffiffiffiffi2i2p

k

� �

i3 ¼ 2kðv3 � vTHÞ2 ¼ i0 þ i2 þ 2ffiffiffiffiffiffiffii0i2

p

i3 ¼ 2i0 þ i2 þ iIN

i2 ¼i0 þ iINð Þ2

4i0

iOUT ¼ i2 þi0

4¼ i0

2þ iIN

2þ i2

IN

4i0

iOUT ¼i0

21þ iIN

i0

� �þ 1

2

iIN

i0

� �2" #

� i0

2e

iINi0

ð7Þ

where iIN is the control current and a resistor converts the

current to the voltage.

Using the restricted terms of the Taylor series will lead

to error. more terms in series expansion will lead to better

approximation with less error. As a result, for better

approximation, more transistors and more complex circuits

are needed. This will entail more power consumption and

more complexity which will increase the error while

decreasing performance.

Figure 8 illustrates the comparison between the pro-

posed function and functions in [4, 6, 8], [3] and [14]. As

shown in this figure the resultant error is between the range

of that of [4, 6, 8] and [14]. Because of high gain range in

this work, simulation result shows, the error is kept less

than 2 dB. As a result, using the first three terms of the

Taylor series is enough for obtaining this error value.

Consequently, this restriction also decreases power con-

sumption. Figure 9 compares the output voltage of the

exponential voltage converter with the ideal state.

Fig. 6 Simulated gain versus VControl of the proposed VGA core

shown in Fig. 4

K

K K

K

K

K K

K

K K4

KK2K

4K

OIOI

OI

OI2I2 OI 2I

2I

4OI

1V 2V3V

INI

OI

OUTI3I

Fig. 7 Exponential converter circuit [15]

Fig. 8 The consequent error of approximation for the functions in [4,

6, 8], [3] and [14] and proposed function with the exponential

function

Fig. 9 Simulated output voltage versus control current IIN of the

exponential converter circuit shown in Fig. 7

Analog Integr Circ Sig Process

123

4 Simulation results

The circuit is designed and simulated in 0.18 lm and from

0.5 to 1 GHz. In the linear-in-decibel VGA, in order to

decrease error, the gain range variation is limited from -68

to 18 dB at 0.5 GHz and from -60 to 20 dB at 1 GHz. The

circuit structure is proper for the higher frequencies, while

Fig. 10 Simulated gain versus input power at different gain settings

at 1 GHz

Fig. 11 Simulated gain versus input power at different gain settings

at 0.5 GHz

Fig. 12 Simulated gain versus control current IIN of the Simulated

proposed VGA at 0.5 GHz frequency

Fig. 13 Simulated gain versus control current IIN of the Simulated

proposed VGA at 1 GHz frequency

Fig. 14 Input P1dB at frequency of 1 GHz

Fig. 15 Input P1dB at frequency of 0.5 GHz

Fig. 16 Power consumption versus control current IIN

Analog Integr Circ Sig Process

123

the range variation is restricted for the linear-in-decibel

range.

Besides the error of the approximation for the Taylor series,

there are two more factors which affect extra error. First and

foremost, exiting the input transistor from the triode region or

the entering of the cascode transistor from the subthreshold

region into the saturation region. But the timing order is

dependent on the input transistor bias. They happen when the

cascode transistor gate has high voltage. In this case, the drain

voltage of the input transistor is not a linear function of the

cascode gate voltage. The second, as shown in Fig. 5 which

poses, the error to increase in the low gate voltage of cascode

transistor because of Eq. 5. The reason this even is that, gm

would become uncorrelated with VDS and therefore the gain is

approximately fixed. Figures 10 and 11 show gain versus input

power at different gain settings at 1 and 0.5 GHz. In Figs. 12

and 13, VGA gain versus control current at the mentioned

frequencies is simulated. To reduce the error, the VGA maxi-

mum gain is restricted to 18 dB at 0.5 GHz. In Figs. 12 and 13,

the circuit gain in terms of the control current and the error in

terms of the ideal state can also be seen. The induced error is

due to the input transistor approaching the saturation region for

high VGA gain. The P1dB of the proposed VGA is illustrated in

Figs. 14 and 15. According to the figures, P1dB, at 1 GHz and

the 20 dB gain, is 2.2 dBm and P1dB, at 0.5 GHz and the 18 dB

gain, is -3.4 dBm. The power consumption of the proposed

VGA is declared in Fig. 16, the minimum power consumption

is 1.43 lW and the maximum is 13.5 mW.

Performance of the proposed VGA compared with the

other seven state-of-the-art VGA is summarized in Table 1.

5 Conclusions

In many communication systems, a broad dynamic gain

range even more than 80 dB is required. Therefore many

VGAs utilize led to high power consumption and low

linearity. In this paper, an 80 dB 0.18 lm CMOS single-

stage VGA from 0.5 to 1 GHz is presented. In order to

obtain linear-in-decibel gain control, two transistors in

triode and sub-threshold region are utilized. The VGA

enjoys -68 to 18 dB gain and -3.4 dBm P1dB at 0.5 GHz

and -60 to 20 dB gain and 2.2 dBm P1dB at 1 GHz. The

power consumption is 13.5 mW form a 1.8 V supply.

Acknowledgments Authors would like to acknowledge the finan-

cial support of University of Tehran for this research under grant

number 8101013/rp/02.

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Masoud Ayat completed his

master’s degree in electrical

engineering at University of

Tehran, Iran, in 2013. He cur-

rently is a research assistant in

the advanced RF and system

design Laboratory at school of

electrical and computer engi-

neering of University of Tehran,

Iran. he has been involved in

several research projects

including transistor level mod-

eling of high frequency trans-

ceivers using bsim3 and bsim4

models. His research interests

include analog, mixed mode integrated circuits and high quality on-

chip inductor and transformer.

Behjat Forouzandeh received

M.S. degree in the field of

Electrical Engineering from

University of Tehran, Tehran,

Iran in 1980 and her Ph.D. in the

field of Electrical Engineering

from the University of Bir-

mingham, U.K. in 1997. She

joined the Department of Elec-

trical and Computer Engineer-

ing at University of Tehran,

Iran, where she is currently an

Associate Professor and

involved in various courses and

labs such as analog/digital

electronics, SOI and quantum computing and VLSI. Her current

research interests include analog and mixed signal circuits, SOI

devices, quantum computing design and implementation. She is also

Analog Integr Circ Sig Process

123

author or coauthor for plenty of journal and conferences papers in

various filed of electronics and hardware engineering.

Samad Sheikhaei received the

B.Sc. and M.Sc. degrees in

electrical engineering from

Sharif University of Technol-

ogy, Tehran, Iran, in 1996 and

1999, respectively, and the

Ph.D. degree from the Univer-

sity of British Columbia, Van-

couver, BC, Canada, in 2008.

He was engaged in research and

design engineering at Sharif

University of Technology. He

also worked in industry for a

couple of years. In September

2009, He joined the Department

of Electrical and Computer Engineering at University of Tehran, Iran,

where he is currently an Assistant Professor. His research interests are

analog, mixed-signal, and RF integrated circuits design, and his

current research projects include circuit design for wireless trans-

ceivers, high-speed serial links, high-speed analog-to-digital con-

verters, and on-chip dc-dc power converters.

Analog Integr Circ Sig Process

123