a 1.8 v low power 5 gbps pmos-based lvds output driver with good return loss performance

A 1.8 V low power 5 Gbps PMOS-based LVDS output driverwith good return loss performance

Hazem W. Marar • Khaldoon Abugharbieh •

Abdel-Karim Al-Tamimi

Received: 23 July 2013 / Revised: 25 October 2013 / Accepted: 3 November 2013 / Published online: 19 November 2013

� Springer Science+Business Media New York 2013

Abstract This paper presents a novel design topology of

a 5 Gbps PMOS-based low voltage differential signaling

(LVDS) voltage mode output driver. The topology is

designed to meet the requirements of low power con-

sumption and high data rates applications. The driver

consists of an output stage and a pre-driver stage where the

driver’s swing and common-mode output voltage are set.

The pre-driver and the output stage consume only

13.1 mW of power at 5 Gbps speed while operating from a

1.8 V voltage supply. Further, the design achieved -21 dB

return loss performance at DC. The driver was extracted

and simulated using Mentor Graphics CAD tools and

implemented in 180 nm CMOS technology. The output

signal is fully compliant with the LVDS standard output

swing and common-mode voltage specifications.

Keywords Low-voltage-differential-signaling

(LVDS) � Low power � Transmit driver � High speed

1 Introduction

With the recent rapid increase in high-speed applications

and the ever-increasing performance demands on commu-

nication systems, higher data rates and processing speeds

are required. In the past, high-speed transmission was

achieved by parallel processing and pipelining. However,

with the increasing challenges related to the complexity

and cost for the IC packaging and the printed circuit boards

fabrication, design engineers are required to focus on

enhancing the performance of serial signal transmission.

Nevertheless, as the speed of data transmission increases,

challenges related to signal integrity and power consump-

tion become more significant. When transmitting data at

high speed along a communication channel, the signal will

suffer from attenuation and reflection. Therefore, the bit

error rate of the system may increase to un-acceptable

levels. To overcome this problem, most of the present high-

speed data transmission topologies consume a significant

amount of power to meet the minimum signal integrity

requirements.

One popular high-speed and low power standard used

for point-to-point short-range data transmission is low

voltage differential signaling (LVDS) [1–4]. It is defined in

two separate industry standards: the generic electrical layer

standard ANSI/TIA/EIA-644-1995 created by the tele-

communication industry association—electronic industry

association [1] and the IEEE 1596.3-1996 specific standard

that is based on the physical layer defined for the scalable

coherent interface (SCI) [2]. As in most point-to-point data

communication systems, an LVDS data transfer system

consists of a transmitter, a receiver, and a transmission

media. Per the standard, the transmitter’s output signal

should have a common-mode voltage between 1.125 and

1.375 V, and an amplitude swing between 250 and 450 mV

[1–5]. These relatively low voltage swing requirements

enable LVDS to consume less power compared to other

signaling standards. Since data is sent differentially, the

LVDS standard combines the ability to deliver high data

rates while consuming low power with high noise immu-

nity and low electromagnetic interference (EMI) [3–5].

Further, the standard increases the interface’s tolerance to

H. W. Marar (&) � K. Abugharbieh

Electrical Engineering Department, Princess Sumaya University

for Technology, Amman, Jordan

e-mail: [email protected]

H. W. Marar � A.-K. Al-Tamimi

Computer Engineering Department, Yarmouk University, Irbid,

Jordan

123

Analog Integr Circ Sig Process (2014) 79:1–13

DOI 10.1007/s10470-013-0224-6

ground mismatch between the transmitter and the receiver

[4, 5]. Therefore, these properties enable LVDS based ICs

to deliver data in high frequencies while offering accept-

able signal-to-noise ratios.

To maintain the integrity of the transmitter’s output

signal and to minimize its return loss throughout the media

channel, the transmit driver needs to provide an internal

differential impedance (ZTx) that matches the transmission

line differential impedance (2 9 Zo). The single-ended line

impedance (Zo) is typically designed to be 50 X [5].

Equation 1 describes the differential return loss throughout

the media channel in dB. The return loss is a measure of the

signal that is reflected back to the source, when a signal is

incident at the beginning of the channel.

Return loss ðdBÞ ¼ 20 log2� Zo � ZTxj j2� Zo þ ZTx

� �ð1Þ

If a transmit driver impedance, ZTx, is matched to 100 X,

the return loss defined in Eq. (1) should be (-?). This

means that no portion of the signal is reflected back to the

transmitter. However, practically, having a return loss

performance below -15 dB is considered acceptable in

most wire-line integrated circuits [6].

Since NMOS devices are faster [7], most current LVDS

transmit drivers use them to improve the transmission

speed. NMOS and PMOS FETs differ in the voltages that

turn on the device and the elements used to dope the sili-

con. Mainly, semiconductor materials such as silicon are

not good conductors. Therefore, to improve conductivity,

they should be doped with other elements that contain extra

electrons like Phosphorous (n-type) or elements missing

electrons (holes) like Boron (p-type). Having an n-type

source and drain, NMOS devices need a positive voltage at

the gate to repel the holes from the body and form a

channel. On the other hand, PMOS devices need a low

voltage at the gate to repel the electrons from the body and

form a p-type channel between the source and the drain [7].

Having the mobility of the electrons twice the holes, a

PMOS device should be designed to have twice the size of

an NMOS device to get the same current. Despite that, the

proposed driver uses a PMOS-based architecture. As sim-

ulation results will show, a PMOS-based topology will

address supply voltage headroom issues. This paper intro-

duces a novel topology of a low power PMOS-based

voltage mode LVDS output driver. The driver can operate

from a 1.8 V supply while supporting switching speeds up

to 5 Gbps. The driver can be used for high-speed serial data

transmission while consuming low power.

This paper is organized as follows: section II illustrates

the basic method of operation of common LVDS transmit

drivers. Section III describes the operation and signal flow

of the proposed design and its methodology. Simulation

results of the driver are demonstrated in section IV. Section

V concludes the paper and compares the proposed design

performance to other published work.

2 LVDS transmit drivers

LVDS is considered a popular differential signaling standard

and is widely used in low-power high-speed industrial

applications [1–4]. The standard was created to address data

communications, and server and computer peripherals. For

example, LVDS is extensively used in multimedia applica-

tions for transmitting video data from graphical processing

units to the flat panel displays in laptops and digital cameras

[8]. Further, LVDS is widely used in high performance

analog-to-digital converters (ADCs) where very high sam-

pling rate is required [9]. In general, LVDS transmit drivers

are either current mode drivers or voltage mode drivers [5].

Figure 1 illustrates the simplified schematic of each type.

2.1 Current mode drivers

In general, current mode drivers consume relatively high

power [5, 11]. However, they are simple to design and

often result in good performance in terms of speed and

signal reflection. This is due to the fact that current mode

drivers use linear resistors to match the driver impedance to

the channel impedance [5, 11]. Therefore, current mode

drivers are less prone to ringing and switching spikes. As

shown in Fig. 1a, NMOS and PMOS devices are used as

switches to switch the current from one leg to another. To

have an LVDS compliant output signal, the driver needs to

supply a current ILoad through the external load resistance,

RLoad. Equation 2 illustrates the output voltage swing of

current mode drivers.

Current mode output voltage swing ¼ RLoad � ILoad

¼ 100� ILoad ð2Þ

Further, the driver has an internal linear 100 X resistor

implemented in parallel with RLoad for transmission line

impedance matching. Therefore, the driver also needs to

provide another current, ILoad, through the 100 X internal

resistor. As a result, current mode drivers consume a

minimum of twice the load current. Since they need to

fully switch twice the load current, MOS devices need to

have large sizes. This will cause the pre-driver stage to

consume significant power, since it is driving a large output

stage gate capacitance [10].

2.2 Voltage mode drivers

Voltage mode drivers consume less power [5]. However,

due to the fact that field effect transistors (FETs) are used

2 Analog Integr Circ Sig Process (2014) 79:1–13

123

as matching devices, the system suffers from non-linear

behavior during signal switching. This might affect the

system’s performance and speed. As seen in Fig. 1b,

NMOS and PMOS devices operate in the linear region and

switch current from one leg to another. For transmission

line impedance matching, each MOS device must be sized

to have an internal 50 X resistance to provide a 100 Xdifferential internal termination impedance. Due to having

a series combination of resistors, the output voltage swing

of voltage mode drivers can be calculated as shown in Eq.

(3).

Voltage mode output voltage swing

¼ ðVHigh � VLowÞ � RLoad

50þ RLoad þ 50¼ ðVHigh � VLowÞ

2ð3Þ

Ideally, consuming only ILoad, voltage mode drivers

consume half the power of current mode drivers. However,

voltage mode drivers are harder to design since the

impedance of the MOS devices is affected by several

factors like temperature and process variations. In addition,

the FET impedance will exhibit non-linear behavior as the

signal amplitude changes. This will likely cause signal

reflection and result in sub-optimal signal integrity. During

the last decade, several designs and topologies were

presented to address high-speed data transfer while

consuming low power. In [12–14], a pre-emphasis circuit

is introduced to improve the matching properties of the

driver and to compensate for high frequencies. In [12], a

current mode transmit driver is presented. The driver

includes a pre-emphasis circuit used to compensate for the

attenuation of limited bandwidth of the media channel.

Further, a closed-loop negative feedback circuit is

proposed to provide means of stability for the common

mode voltage. Figure 2 illustrates a simplified schematic of

the LVDS driver and the pre-emphasis circuit presented in

[12].

As seen in Fig. 2, the signal flow due to the input signals

(Vin?, Vin-) and the delayed signals (Vind?, Vind-) are

controlled by an enable signal (Pre_EN). Further, a pre-

emphasis circuit is added to the normal current mode

LVDS driver to enable high-speed transmission. At run-

time, the original and the delayed signals become the same

logic state for a short period during which the pre-emphasis

circuit supplies additional current to the main driver circuit.

This excess current contributes in generating the needed

voltage swing and thus improves the driver’s speed per-

formance. As a result, the driver was able to provide

2 Gbps speed while running from a 3.3 V supply.

Having two pairs of MOS devices with a PMOS current

source, a typical LVDS driver is considered a bridged-

switched current sources driver that works well for supply

voltages above 2.5 V. However, due to the finite on-resis-

tance of the MOS devices, the driver might run into supply

headroom issues if operated from lower power supplies.

Therefore, in [15], a new double current source (DCS)

LVDS topology is presented to address headroom issues.

The DCS design replaced the upper PMOS current

source in the normal LVDS driver with two PMOS current

sources. Therefore, the driver is able to run using a 1.8 V

supply. However, to maintain the same voltage swing, the

current sources are doubled and the size of the transistors

must be increased.

Fig. 1 Common topologies for

LVDS transmit drivers.

a Current mode driver.

b Voltage mode driver

Analog Integr Circ Sig Process (2014) 79:1–13 3

123

In [16], a current mode LVDS driver, with built-in self-

detection functions, is presented. The functions include

frequency and duty-cycle detection units to monitor and

maintain the transmitter’s output signal to be within the

standard specifications. However, adding these units

requires more power. The driver uses a 3.3 V supply

voltage while supporting data rates up to 1.3 Gbps.

As the transmission speed increases, the effect of the

driver parasitics becomes more significant and hence the

signal might suffer from spikes and glitches. To overcome

this problem, a charge/discharge circuit that consists of a

combination of capacitors is presented in [17]. This solu-

tion helped in suppressing the switching noise and stabi-

lizing the driver’s output signal. Therefore, the driver is

able to support switching speeds up to 2.2 Gbps while

operating from a 1.8 V supply.

To maintain the LVDS standard common mode voltage

regardless environment variations, the previous designs

included a common mode feedback circuit that controls the

amount of current passing through the driver, hence con-

trolling the output signal specifications. This is achieved by

comparing the output common mode voltage to a 1.25 V

reference voltage. However, this reference voltage might

be also affected by the environment variations. In [18], a

band-gap reference source is introduced to generate a

temperature independent reference voltage.

All these topologies helped in improving the driver’s

ability to deliver high data rates while using a single

transmitter. However, in [19], a multi-channel architecture

is presented. The design included several LVDS transmit-

ters with a pre-emphasis circuit controlled via a multiplexer

to improve transmit driver’s speed and throughput. How-

ever, adding the multiplexer and the controlling circuits

caused the driver to consume more power. Therefore, the

driver is able to provide 3.125 Gbps while consuming

48 mW. Other designs presented different interfacing cir-

cuits and topologies to allow LVDS to communicate over a

variety of media channels. In [20, 21] two current mode

LVDS transmit drivers are interfaced with optical fiber

channels to allow high-speed communication.

This proposed design is a low power and high-speed

voltage mode transmit driver. As simulation results will

show, the driver achieves good signal integrity perfor-

mance and low power operation while supporting high

switching speeds. The implementation and design meth-

odology of the driver is discussed in the next section.

3 Proposed driver

To minimize power consumption, voltage mode driver

architecture is used. Figure 3 shows a simplified schematic

of the proposed driver and the signal flow through it. As

illustrated in the figure, the new design consists of a pre-

driver stage and an output stage. The pre-driver stage con-

trols the output signal characteristics like the common-mode

Fig. 2 LVDS driver with pre-

emphasis circuit in [12]


123

voltage and the amplitude swing, while the output stage

ensures the integrity of the output signal. RLoad is an

external resistor through which the current ILoad passes

creating the differential output swing. LPackage, CPad, and

CBoard represent the parasitic inductance and capacitance of

the chip and the board.

3.1 Generating the pre-driver output swing

and common-mode voltage

The pre-driver stage, to which the input signals are applied,

consists of a P-type MOSFET differential pair with a

resistive load. At high frequencies, having low capacitance

at the pre-driver is important to minimize power con-

sumption [10]. Therefore, the differential pair PMOS

devices (Q1, Q2) were designed with a relatively small

channel width. Depending on the input signal, Q1 and Q2

are switched passing the current IPre through one leg only.

This current will create a voltage drop across one of the

pre-driver resistors, RPre. Equation 4 describes the output

voltage swing of the pre-driver stage.

VOut�Pre ¼ IPre � RPre ð4Þ

Source followers at the output stage (Q3, Q4) have high

input impedance Zin(Q3,Q4). Therefore, the pre-driver’s load

is equal to RPre in parallel with Zin(Q3,Q4) and is dominated

by RPre. This will minimize the amount of power consumed

by the pre-driver, since it is not driving highly capacitive

switches at the output stage. This is a significant advantage

over current mode drivers where pre-drivers drive large

gate capacitance of the output stage. Further, to help

achieve a good margin for the common-mode voltage over

operating environment variations, the pre-driver has a

variable programmable resistor, RCOM. The resistor is used

to help set the common-mode voltage of the pre-driver

stage and the output stage to be within the LVDS standard

specifications. To make it programmable, the resistor,

RCOM, is implemented using a group of parallel NMOS

devices controlled by an external signal as shown in Fig. 4.

Depending on the value of RCOM, the common-mode

voltage of the entire driver is shifted by IPre � RCOM .

Fig. 3 Proposed LVDS driver

Fig. 4 Common-mode voltage variable resistor, RCOM

Fig. 5 Small signal half-circuit model for output voltage


123

Equation 5 describes the common-mode voltage of the pre-

driver stage.

VCM�Pre ¼ IPre � RCOM þIPre

2� RPre ð5Þ

3.2 Generating the output voltage swing

The output stage shown in Fig. 3 consists of two PMOS

devices (Q5, Q6), two internal termination resistors Rterm,

and two PMOS source follower (Q3, Q4). The output dri-

ver employs a positive feedback technique that minimizes

power consumption. In this technique, the pre-driver con-

trols the switching of the output stage source followers

(Q3, Q4). This eliminates the need for any additional

switching circuitry. Therefore, Q3 and Q4 will consume a

maximum current of ILoad when fully switched. Further, the

output signals from the source followers (VZ, VY) control

the switching of the PMOS devices (Q5, Q6). These PMOS

devices will be in saturation and switch the load current

ILoad from one leg to the other. The current will create a

voltage drop across the load resistance, RLoad.

Figure 5 shows the small signal half-circuit model of the

proposed driver as seen from the load resistance, RLoad. The

pre-deriver output swing, described in Eq. (4), is modeled

as a pulse voltage source connected to the output imped-

ance of the source follower (Q3, Q4). Since Q5 and Q6 are

in saturation, their output resistance is high and should not

affect the circuit. However, since the source-follower out-

put impedance, 1/gm3,4, is not much smaller than Rterm and

RLoad, it should be taken into account.

For the output signal to be LVDS compliant, the single

ended voltage swing should be between 125 and 225 mV

[1–4]. Equation 6 describes the half circuit output voltage,

VOUT, across the half circuit load resistance, RLoad/2.

VOUT ¼RLoad

2� ðIPre � RPreÞ

RLoad

2þ Rterm þ 1

gm3;4

¼ RLoad

2� ILoad ð6Þ

Since the load current, ILoad, is used to achieve the

needed output voltage swing, it cannot be reduced much.

However, to minimize the power consumption, the pre-

driver current, IPre, may be optimized. Equation 7

illustrates the pre-driver current with common-mode

input signals. The equation shows that IPre can be a

fraction of the load current. Therefore, by making RPre

Fig. 6 Single-ended internal impedance

Fig. 7 Pre-driver output signals


123

Fig. 8 Output stage signals


123

large, the system can be designed to consume very low

power at the pre-driver stage compared to other driver

topologies.

IPre¼WQ1;Q2

L

lpCox

2

� �VDD� IPre�RSpre�

VDD

2� Vtp

�� 2

¼ILoad� RLoad

2þRtermþ 1

gm3;4

� �RPre

ð7Þ

3.3 Generating the output common-mode voltage

For the output signal to be LVDS compliant, the common-

mode voltage should be between 1.125 V and 1.375 V [1–

5]. The output signal common-mode voltage for the pro-

posed driver, shown in Fig. 3, is determined by the sum of

voltage drops along the path from RLoad to the pre-driver

common-mode resistor, RCOM. Equation 8 describes the

common-mode voltage of the output stage.

VCOM ¼ IPre

RPre

2þ RCOM

� �þ VSGðQ3;Q4Þ þ VRterm þ

RLoad

2

� ILoad

ð8Þ

As noted in equation 8, the output common-mode

voltage does not significantly rely on the possibly

varying supply source VDD. Using a PMOS-based

topology that uses the ground, 0 V, as a reference, allows

the system to utilize the full voltage range. This is a major

advantage over other topologies where the common-mode

voltage is limited by the headroom of the supply source

voltage. This allows using a 1.8 V supply and still

maintaining LVDS common mode characteristics.

Moreover, as illustrated in the simulation results, the

design is able to withstand a 3 % variation in the supply

voltage while having the output signal compliant with the

LVDS standard.

3.4 Proposed design immunity to external factors

To increase the design robustness and to decrease its

dependency on process, voltage, and temperature (PVT)

variations, two programmable resistors (RSpre, RSout) are

used to control the amount of current passing through the pre-

driver and the output stage, respectively. Using resistors to

control the current flow throughout the driver minimizes the

supply voltage headroom issues. This is because the resistors

will exhibit less voltage drop than the traditional current

sources. Since it has the ability to control the amount of

current, the driver is capable of sustaining the output dif-

ferential voltage swing within the standard specifications

(250–450 mV) [1–5]. RSpre and RSout, are constructed using

a group of parallel PMOS devices. Using an external signal,

the PMOS devices are controlled to provide the proper

impedance which will adjust the amount of current passing

through the pre-driver and the output stage, if needed.

3.5 Achieving 50 X single-ended internal impedance

To minimize signal reflection and maximize its integrity,

the driver’s differential output impedance should be mat-

ched to the transmission line differential impedance,

100 X. The internal single-ended output impedance of the

proposed driver is illustrated in Fig. 6. Since most of the

current will flow though one leg only, the other branch will

have high-impedance devices that have minor effect on the

driver’s impedance.

Equation 9 describes the single-ended internal imped-

ance of the driver.

ZChip ¼ SLPackage þ1

SCPad

==Rterm þ 1

gm3;4

1� gm5;6

gm3;4

==ro5;6

!ð9Þ

The single-ended output stage internal impedance

described in Eq. (9) should be matched to 50 X. This

means that the signal at the end of the channel will exhibit

Fig. 9 Output signal common-mode voltage


123

a minimal amount of reflection. If the driver internal

impedance is properly matched, the output stage swing

described in Eq. (6) would be half the pre-driver swing

described in Eq. (4). The following section illustrates the

simulations results that verify the compliancy of the

proposed driver with the LVDS standard specifications.

4 Simulations results

The new driver was designed and extracted using Mentor

Graphics CAD tools and was implemented in 180 nm

CMOS technology. Using a supply voltage of 1.8 V, the

driver was simulated using a 5 Gbps PBRS7 input source

Fig. 10 Extracted single-ended (OUT, OUTB) eye-diagram. a TT Corner at 50 �C, 1.8 V supply. b SS corner at 125 �C, 1.75 V supply. c FF

corner at -40�, 1.85 V supply. d Slow MOSFET, fast R, 125 �C, 1.75 V. e Fast MOSFET, slow R, -40 �C, 1.85 V


123

to verify the output differential voltage swing, common-

mode voltage, and the pre-driver’s signals.

The PMOS devices used have a channel length of 0.18 lm

and a channel width of 35 and 100 lm for the pre-driver

stage and the output stage source followers, respectively.

Figure 7 shows the pre-driver output swing along with the

pre-driver’s current consumption. The pre-driver circuit

consumes only 1.8 mA, therefore burning only 3.2 mW.

Simulated at 50 �C with a typical process, the differential

output swing of the pre-driver stage is about 700 mV.

Figure 8 shows the output stage signals at 50 �C with a

typical process corner. The differential output signal swing

Table 1 Simulation results summary

Simulation setup Output voltage

swing (mV)

Common-mode

voltage (V)

Typical corner at 50 �C,

1.8 V supply

350 1.17

Slow corner at 125 �C,

1.75 V supply

300 1.14

Fast corner at -40�,

1.85 V supply

450 1.23

Table 2 Simulation results on different packages

Package parameters Eye opening

amplitude (mV)

Eye width

(psec)

LPackage = 0 nH, CBoard = 500 fF 300 200








LPackage = 3 nH, CBoard = 1 pF 320 180

Fig. 11 Extracted single-ended (OUT, OUTB) with different loading

configurations. a Typical corner, LPackage = 3 nH, CBoard = 100 fF.

b Typical corner, LPackage = 3 nH, CBoard = 1 pF. c Typical corner,

LPackage = 1 nH, CBoard = 500 fF. d Typical corner, LPackage =

5 nH, CBoard = 500 fF


123

across the load resistance, RLoad, is about 350 mV, which is

fully compliant with the LVDS standard. Comparing the

voltage swings of Figs. 7 and 8, the output stage voltage

swing is almost 50 % of the pre-driver swing. This indi-

cates the output stage is properly matched to 50 X which is

equal to RLoad/2. As a result, signal reflection is minimized.

Further, the current flowing through Q5 is about 5 mA

which is comparable to the load current, ILoad. This means

that most of the current is used to generate the needed

output voltage swing, which minimizes the output stage

power consumption. It should be noted that Q3 and Q4

never reach a zero current state. This is necessary to

maintain proper impedance termination. As a result, the

output stage consumes only 9.9 mW. This is a significant

power saving compared to current mode topologies where

the output stage current is at least twice the load current.

As mentioned earlier, to be LVDS compliant, the com-

mon-mode voltage should be between 1.125 and 1.375 V [1–

5]. Figure 9 shows the output signal common-mode voltage.

The signal is clearly within the LVDS standard. Further, the

common-mode voltage ripple is less than 50 mV. This

reduces the EMI and crosstalk during data transmission.

Figure 10 shows the eye diagram of the differential

output of the driver running at different process corners and

operating environments at 5 Gbps date rate. As the figure

illustrates, the eye width is about 200 ps and the differ-

ential eye height is greater than 500 mVppd in all cases.

Therefore, the system is able to sustain the LVDS

requirements under different conditions with a 3 % varia-

tion in the supply voltage. Simulations take into account

the package inductance (3 nH), the pads capacitance

(100 fF), the chip-to-board capacitance (150 fF), and the

extracted layout metal parasitic elements.

Table 1 lists the design output signal specifications based

on the previous eye measurements. The results show that

the driver is fully compliant with the LVDS standard and is

able to operate under all operating environment conditions.

To further demonstrate the robustness of the design, the

driver was simulated with multiple package and board loading

configurations. Figure 11 plots the output signal with selected

LPackage and CBoard values. Table 2 lists the eye opening

amplitude and eye width for nine different package and board

loading configurations. While the slope and shape of the signal

changes, the eye opening and width are acceptable.

Figure 12 shows the differential return loss performance

of the system. The figure shows that the driver is well

terminated and achieves -21 dB differential return loss at

DC. The return loss performance of the system degrades as

the frequency increases since the effect of the parasitic

capacitance and inductance, shown in Fig. 3, becomes

Table 3 Simulation results summary

Design attribute Value

Speed 5 Gbps

Supply voltage 1.75–1.85 V

Technology 180 nm CMOS

Total current (pre-driver?output stage) 7.3 mA

Output swing amplitude 300–400 mV

Common-mode voltage 1.14–1.23 V

Return loss at DC -21 dB

Fig. 12 Differential return loss performance

Fig. 13 Proposed driver layout


123

more significant at higher frequencies. Although using an

NMOS based topology will not work due to running into

supply headroom issues, Fig. 12 shows the return loss

performance if an NMOS based topology is used. Com-

paring the results, it is shown that using an NMOS based

topology will not affect the return loss performance sig-

nificantly. It should be noted that the Rterm resistors in

Fig. 3 will shield the capacitance effect of devices in the

output stage source followers like Q3 and Q4.

Figure 13 shows the layout of the new design topology

using 180 nm technology. Applying compact layout design

techniques and having a symmetrical design allowed

reducing the circuit total area and minimizing the metal

parasitic resistance and capacitance.

Table 3 provides a summary of the new design topology

simulation results. The results show the total current con-

sumption of the driver along with the driver’s output signal

specifications.

5 Conclusions

In this paper, a PMOS-based low power 5 Gbps voltage

mode LVDS driver with a positive feedback mechanism in

the output stage is presented. The minimum amplitude

swing is 300 mV with a common-mode voltage of 1.14 V

which are compliant with the LVDS standard. Both the

output swing and the common-mode voltage are set in the

pre-driver. Power consumption is reduced by using a PMOS

based topology that does not require a high supply voltage.

Moreover, implementing a pre-driver along with source

followers that utilize the driver load current in the output

stage eliminates the need for any extra current to switch the

source followers which saves power. Further, the design

achieves a -21 dB differential return loss performance at

DC and is implemented using 180 nm CMOS technology.

Previous designs that includes designing a DCS topology

[13], adding a control unit to monitor the frequency and

duty cycle of the output signal [14], and designing a multi-

channel transmitter [18] intended to achieve high speed data

transmission while consuming low power. Simulation

results, using Mentor Graphics CAD tools, show that the

proposed design consumes only 13.1 mW of at-speed

power from a 1.8 V supply. Table 4 lists a comparison with

other published work that demonstrates the power and

speed efficiency of the newly proposed design topology.

References

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characteristics of low voltage differential signaling (LVDS)

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Table 4 Performance

comparison with published

work

Work Technology Supply

(V)

Speed

(Gbps)

Power

consumption

(mW)

Year of

publication

[13] CMOS 0.18 lm 1.9 2.5 14.4 2009

[14] CMOS 0.13 lm 3.3/1.5 1.5 80 2011

[15] CMOS 0.35 lm 1.8 1.4 23 2005

[15] CMOS 0.35 lm 1.8 1.2 12.8 2005

[16] CMOS 0.35 lm 3.3 1.3 29.4 2012

[17] CMOS 0.35 lm 1.8 2.2 23 mW for

output stage

2010

[18] CMOS 0.18 lm 1.8 1.8 11.6 2010

[19] CMOS 0.18 lm 3.3/1.8 3.125 48 2010

[20] CMOS 0.18 lm 3.3 2 21 2011

[22] CMOS 0.18 lm 3.3 5 17.8 2012

This work

(simulation results)

CMOS 0.18 lm 1.8 5 13.1 2013


123

11. National semi conductors. (2002). LVDS owner’s manual. A

general design guide for national’s low voltage differential sig-

naling (LVDS) and bus LVDS products (2nd ed.).

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(2011). LVDS driver design for high speed serial link in 0.13 lm

CMOS technology. In Computational Problem-Solving (ICCP),

2011 International Conference on (pp. 145–148, 21–23).

13. Tajalli, A., & Leblebici, Y. (2009). A slew controlled LVDS

output driver circuit in 0.18 m CMOS technology. IEEE Journal

of Solid-State Circuits, 44(2), 538–548.

14. Wei, X., Li, P., & Wang, Y. (2011). Regular paper A LVDS

transmitter with low-jitter PLL and pre-emphasis for serial link.

Journal of Electrical Systems, 7(3), 373–381.

15. Chen, M., Silva-Martinez, J., Nix, M., & Robinson, M. E. (2005).

Low-voltage low-power LVDS drivers. IEEE journal of solid-

state circuits, 40(2), 472–479.

16. Hsu, H. S., & Lu, G. Y. (2012). High-speed driver with built-in self

detection functions for off-chip transmission. Journal of Analog

Integrated Circuits and Signal Processing, 73(1), 397–408.

17. Hua, C., & Ping, L. (2010). A novel 2.2 Gbps LVDS driver

circuit design based on 0.35 lm CMOS. Journal of Semicon-

ductors, 31(10), 105007.

18. Kleczek, R. (2010). The design of low power 11.6 mW high speed

1.8 Gb/s stand-alone LVDS driver in 0.18-lm CMOS. In Mixed

Design of Integrated Circuits and Systems (MIXDES), 2010 Pro-

ceedings of the 17th International Conference. (pp. 337–342).

19. Park, W., & Lee, S. C. (2010). Design of LVDS driver based

CMOS transmitter for a high speed serial link. IEEE Interna-

tional Conference on Electronics and Information Engineering

(ICEIE), 1, 2010.

20. Hui, H., Jia, L., Lingling, S., & Keming, C. (2011). Design of 2 Gb/

s LVDS transmitter and 3 Gb/s LVDS receiver for optical com-

munication in 0.18 lm CMOS technology. In Microwave Con-

ference Proceedings (CJMW), 2011 China–Japan Joint. (pp. 1–3).

21. Park, K. Y., Oh, W. S., Choi, J. C., & Choi, W. Y. (2011). Design

of 250-Mb/s low-power fiber optic transmitter and receiver ICs

for POF applications. Journal of Semiconductor Technology and

Science, 11(3), 221–228.

22. Rao, P. V. S., Desai, N., & Mandal, P. (2012). A low-power

5-Gb/s current-mode LVDS output driver and receiver with

active termination. Circuits, Systems, and Signal Processing,

31(1), 31–49.

Hazem W. Marar is a Lab

Instructor and teaching assistant

at Princess Sumaya University

for Technology, Jordan. He

received his M.Sc. degree in

Embedded Systems Design from

Yarmouk University, Jordan, the

B.Sc. degree in Computer/Elec-

trical Engineering from Princess

Sumaya University for Technol-

ogy, Jordan. His research inter-

ests are in the area of system IC

design, microprocessors, and on-

chip-communication.

Khaldoon Abugharbieh received

a B.S.E.E. degree from Arizona

State University in 1994 and an

M.S.E.E. degree from Stanford

University in 1996. He received a

Ph.D. degree in electrical engi-

neering from Santa Clara Uni-

versity in 2009. From 1995 to

1999, he worked on programma-

ble logic devices and data com-

munication products with Cypress

Semiconductor. In1999,he joined

the RF Group in DataPath Sys-

tems, which was later acquired by

LSI Logic Corporation, where he

worked on consumer-product mixed-signal system-on-chips. In 2006, he

joined National Semiconductor Corporation High Speed Signal Division.

Dr. Abugharbieh also worked at Xilinx Corporation SerDes Technology

Group as senior design manager. He worked on RF-class voltage-

controlled oscillators, phase lock loops, data converters, and high-speed

and low-power I/Os. He is presently a faculty member in Princess Sumaya

University for Technology electrical engineering department in Amman,

Jordan. His research interests include high-performance analog- and

mixed-signal ICs. Dr. Abugharbieh holds eight issued US patents and has

authored and co-authored twelve technical refereed journal and confer-

ence publications.

Abdel-Karim Al-Tamimi is an

Assistant Professor in the Com-

puter Engineering Department at

Yarmouk University, Jordan. He

received his Master and Ph.D.

degrees in Computer Engineer-

ing from Washington University

in St. Louis in 2007 and 2010,

respectively. His research inter-

ests include computer networks,

multimedia networks and appli-

cations, modeling and simula-

tion, and computer security.


123

a 1.8 v low power 5 gbps pmos-based lvds output driver with good return loss performance

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