a 25gb/s low noise 65nm cmos receiver tailored to 100gbase … · a 25gb/s low noise 65nm cmos...
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A 25Gb/s Low Noise 65nm CMOS Receiver tailored to 100GBASE-LR4
Dan Li, Gabriele Minoia*, Matteo Repossi*, Daniele Baldi*, Enrico Temporiti*, Andrea Mazzanti, Francesco Svelto
Università degli Studi di Pavia, Pavia, Italy
* Studio di Microelettronica, STMicroelectronics, Pavia, Italy
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Motivation
• Intensive utilization of high-speed optical communication calls for low cost solution (electronics part) CMOS
IEEE 802.3ba Physical layer 40GBSE 100GBASE
Electrical 1m Backplane KR4 7m Copper cable CR4 CR10
Optical 100 m OM3 MMF SR4 SR10 150 m OM4 MMF
10 km SMF LR4 LR4 40 km SMF ER4
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Core network
Server I/O
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Outline • Existing approaches to high-speed receiver front-end • Proposed two-stage front-end • Receiver design • Experiments • Conclusions
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100 GBASE-LR4 architecture
TIA Requirement Note Noise Iin,rms < 4.2μArms BER < 10-12
Bandwidth ~17GHz 2/3 * 25Gb/s Transimpedance gain 74dBΩ 300 mVpp@RX output
• Target: low noise, wide bandwidth, significant gain 3
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Low noise front-end: Common Gate TIA?
• Wide bandwidth needs large bias current, which degrades noise
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(Transimpedance gain)
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Low noise front-end: shunt-feedback TIA?
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• In low-speed shunt-feedback TIA, low noise achieved by large RF
(Transimpedance gain)
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Shunt-feedback TIA: transimpedance limit
• A*f0: constant in a given technology node • From transimpedance limit: RF ~ 1/BW2 • Wide bandwidth results quite small RF , degrading noise
significantly
“Transimpedance limit” Mohan, JSSC, 2000
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Two-stage front-end: BW scaling
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Two-stage front-end: noise reduction
• Noise of RF: 1/n2
• Low frequency noise of Amp & EQ: 1/n4 • High frequency noise of Amp & EQ: not impacted 8
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Input referred noise (n=2): RF
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Input referred noise (n=2): amplifier
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Input referred noise (n=2): equalizer
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Input referred noise (n=2): all
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0
1
2
3
4
5
6
7
8
145 550 1500
pA^2
RF (Ohm)
Integrated input referred noise EQ noiseAmp noiseRF noise
Comparison: noise (simulation)
• Optimal performance with RF of ~ 500 Ohm (noise vs. frequency response)
Conventional
Two-stage front-end
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Receiver architecture
• 5-stage LA and 3-stage buffer provide sufficient gain Simulation* Front-end LA Buffer RX
Gain (dB) 57.2 23.2 2.9 83.3 BW (GHz) 15.6 21.5 50 14.8
Power (mW) 13.4 25.7 49.4 88.5
* Without photodiode 14
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Low noise front-end
• Dummy mirror TIA: suppress common mode supply noise • Push-pull amplifier: boosts open loop gain to 6.4, RF = 510Ω • RF and BW can be tuned independently for optimal performance
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LA & Buffer gain stage
• Additional current load to boost Gm, formed by thick oxide transistor powered by higher Vdd (1.8V)
LA gain stage Buffer stage
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Chip summary
Technology ST 65nm Bulk CMOS
Core area 0.42 mm2
(0.66 x 0.64)
Power consuption 93 mW
Voltage supply 1 / 1.8 V
1650 μm
1850
μm
660 μ
m
640 μm
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Frequency response
Single-ended in, differential out
Item Nominal Tuning RT (dBΩ) 83 78 ~ 87.1
Bandwidth (GHz) 13.6* 10.6 ~ 18.2 * Pure electrical, which becomes 17 GHz at 80fF PD cap + 0.5nH bondwire (sim.) 18
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Input referred noise current spectral density
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• In,rms = 2.44μArms, In,ispectrum,avg = 20.9pA√Hz
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Electrical eye diagram plot
• Electrical eye diagram with ~14mVpp input voltage (after attenuation) • Eye amplitude: 662mVpp, Jitter_rms = 2.5ps (PRBS31)
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Comparison Ref. This Work CICC10 JSSC08 JSSC12
CMOS Tech. (nm) 65 65 90 45 (SOI)
Bit Rate (Gb/s) 25 25 40 40
Bandwidth (GHz) 13.6 22.8* 22 30
Transimpedance (dBΩ) 83 69.8* 66 55
Supply (V) 1 / 1.8 1 / 1.8 1.2 1
Power (mW) 93 74 75 9
Noise (pA/√Hz) 20.9*** - 22** 20.5
FOM (GHz∙Ω/mW) 2066 952 585 1874 *: simulated, **: differential, ***: including dummy mirror TIA
• Highest FOM obtained 21
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Conclusions • A 25 Gb/s optical receiver in 65nm CMOS presented,
meeting 100GBASE-LR4 with margin • A new low noise technique proposed: noise and BW trade-off
broken by two-stage front-end architecture • Low noise achieved with state-of-the-art FOM
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