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1SSCC96 I SESSION24 / ANALOG TECHNIQUES / PAPER SP 24.5SP 24.5: A 900MHz Frequency SynthesizerwithIntegrated LC Voltage-Controlled OscillatorAkbar Ali, Joo LeongThamRockwell International, NewportBeach,CAIntegration of general-purpose frequency synthesizers usuaUyrequires a BiCMOS process and necessitates a compromise be-tween the level of integration and performance. Frequency syn-thesizers with extensive channel programming flexibility and lowphase noise typically require exte rnal voltage-controlled oscilla-tors (VCOs) while highly-integrated synthes izers utilizing on-chip VCOs tend to exhibit degraded phase-noise performance.The frequency synthesizer presented here featur es low referencespurs and low phase-noise and is fully-integrated with the excep-tion of an external crystal and anRC loop-filter. It uses a 25GHzfT silicon bipolar process an di s for 9OOMHzISMband applicationsand operates over a supply voltage range of 2. W to 5.0V. Theintegration level is achieved by simplified architecture thatprovides 41 channels with a 60OkHz spacing and requires a 6bprogramming word.The block diagram of the frequency synthesizer is shown inFigure 1. The pulse-swallow architecture consists of a crystaloscillator, a reference divider, a phase-frequency detector andcharge-pump, an LC voltage-controlled oscillator WCO),RF out-put buffers, a prescaler, a 6b swallow counter, a b e d 6b counter,and control logic. The output of the VCO, divided in frequency bythe chain formed by the prescaler, b e d counter and swallowcounter, is phase-locked t o the reference frequency. The outputfrequency is given by

FOut=FmP(M*N+A)where N>4 (1)By using a 32/33 prescaler (M), in Cl), a fixed N of 47 covers th eISM band with the first channel at 903MHz and the last at927MHz with channels spaced 600kHz apart (A = 1to 41). Areference frequency of 9.6MHz is chosen, giving R of 16. A serialthree-wire control input, which is TTUCMOS compatible, is usedfor channel programming. The RF output bufTers provide twoseparate pairs of differential outputs with selectable outputpower levels.Differential current-mode logic (CML) circuits are employedthroughout the logic section because they are less noisy th an the irCMOS counterparts due to smaller voltage swings. The crystaloscillator output and the reference frequency input are madeaccessible on two pins and are TTUCMOS compatible. Thecrystal oscillator and CMOS-to-CML converters ar e placed as fa rfrom the VCO as possible to minimize coupling through thesubstrate.The charge-pump has matched top and bottom switching outputcurrent sources tha t eliminate the dead-band problem and result sin improved spurious performance. The technique is illustrated inFigure 2. A capacitor is added on the np n transistor to match theeffects of the parasit ic capacitances on the pnp transis tor to resultin symmetrical pulse shapes of the two output currents. Whenthere is little or no phase difference at the phase-detector inp uts,the charge-pump output curre nt pulses a re of short duration andcancel each other, minimizing the spurs. On-chip capacitors of20pF each are used at the charge-pump output to ground andpositive supply to localize high-frequency energy containedin th epulses. The charge-pump output has a voltage compliance ofabout 200mV from either rail to minimize the required VCO

tuning sensitivity. The phase-locked loop uses a typeI third-orderlow-pass filter with 4kHz bandwidth. This gives optimum phase-noise performance and reasonably fast settling.A fully-differential RF LC voltage-controlled oscillator using on-chip spiral inductors and varactors and low distortion differentialbuffering stages that ultimately drive 50Q off-chip are shown inFigure 3. A monolithic varactor-less LC VCO using 2 separateresonating tanks in silicon bipolar is previously reported [l].Low-harmonic content in th e RF outputs of the buffering stages isdesirable since it minimizes the phase inaccuracy in passivephase shiRerswhen they are used for generating quadrat ure localoscillator signals. The active circuit for th e oscillator i s formed bythe emitter-coupled pair , Q1 and Q2. The fdly-differential archi-tecture of the VCO provides more power supply rejection as wellas more common mode radiation immunity compared to single-ended designs. Better radiation immunity of the resonatorsminimizes the possibility of pulling of the center frequency of theVCO due to the presence of a large signal near the centerfrequency 121. The differential a rchitec ture, in addition, reducesthe effects of parasitic lead inductance and substrate coupling.The VCO is followed by a low distortion stage (Q3-Q6). Filt eringis provided by the low-pass network R1 , R2 and C1.The outputstage has two degenerated emitter coupled pairs (Q7-Q8, Q9-410) connected in parallel. This allows the harmonic distortion ofthe stage to be independent of the output power level. The loweroutput power levelis selectable by shutt ing I6 off. The output ac-coupling capacitors C5 and C6 are also part of a differential L-section match to 50Q off-chip.Figure 4 shows the RF output spectrum of the synthesizer for a-6dBm output level for one of the differential outputs. Theharmonics of the output are less t han -34dBc. A close-in spectralplot of th e carrier is shown in Figure 5. The spurs a re less than -1lOdBc. Figure 6 shows a plot of the output phase-noise. Thephase-noise is -1OldBJHz at a 1OOkHz offset from the carrier.The measured results ar e summarized in Table 1.The four most critical inputs/outputs (charge-pump output, VCOcontrol input, VCO outputs, and crystal oscillator output) areplaced at close to 90 " from each other to minimize inductivecoupling. The logic section of the synthesizer (including thecrystal oscillator) dissipates 25mW at 3V, the VCO lOmW, andeach output stage 25mW for a -6dBm output and 15mW fo r-1ldBm. The IC die is about 5.5mm2and is tested in a 32-pin th inquad flat package.Acknowledgments:The authors thank C. Hull, F. Carr, and L. Jansson for sugges-tions and support.References:[U Nguyen, N. M. , R. G. Meyer, "A 1.8GHz Monolithic LC Voltage-Controlled Oscillator,"ISSCC Digest of Technical Papers, pp. 158-159,Feb., 1992.[21 Kurokawa,K, "Injection Locking of Microwave Solid-state OsciUa-tors,"Proceedingsof the IEEE,Vol. 61,No.10,pp. 1386-1410,Oct., 1973.

390 1996 IEEE InternationalSolid-stateCircuits Conference 0-7803-3136-2I 96 I$5.00 IO IEEE

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ISSCC96I February 10,1996 / Sunset A - D I315 PM-

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Technology 25GHz f, bipolarReference frequency 9.6MHz.............................................................................................................. ~ Channel spacing 600kHz

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Figure 6: NCPC chip micrograph. Figure 7: SC filter chip micrograph.

SP 24.5: A SOOMHz Frequency Synthesizer with Integrated LC Voltage-Controlled Oscillator(Continued from page 391)

Figure 3: LC VCO and buffers.

DIGESTOF TECHNlCaLPAPERS 479