A CMOS Fully Differential OperationalTransconductance Amplifier

Nuntachai Poobuapheun Xiaoyan Lu nuntachp@eecs.berkeley.edu clu123@culink.berkeley.edu

EE240 Term Project, Spring 2003Department of Electrical Engineering and Computer Sciences

University of California, Berkeley

Design Approach

Topology SelectionTopology selection is one of the most important steps in designing a circuit to

meet the given specifications. Making a right decision in this step will make the required specifications easier to be achieved. Since the detailed design and verification processes consume a lot of time, we have to be extremely careful at the starting point in order to avoid any “re-designs”. Our primarily results from hand calculations show that the amplifier needs a DC gain of around 400k, which is in the order of at least ( )3ogmr . The one stage and folded triple-cascode designs, although might be able to meet the gain requirements, are not suitable because they tend to have to low output swings (~1.4-1.6 V). Therefore, our choices have been narrowed down to either two-stage design or gain-boosted one stage design. The main advantage of the gain-boosted topology is that it requires only two main current legs, which is very power efficient. However, designing a one stage gain-boosted amplifier to have a high output swing, low noise, and high gain at the same time is obviously not an easy task. Although two-stage design seems to be less power efficient (four main current legs), it gives us more degrees of freedom in the design. Our basic calculations indicates that by combining the high-output swing and relatively low noise properties, two-stages amplifier tends to consume less power than the gain-boosted one stage amplifier for reaching the given specifications. So we select the two-stage topology for our design.

Two-Stage Design ConsiderationsTo ensure a high gain over the output range, we deiced to use the triple-cascode

topology in the first stage and use a common source topology in the second stage. Sincewe want to keep the sizes of the input pair to be small, a minimum channel length ofNMOS input pair is employed. We deiced to connect the output of the first stage directlyto the gate of the PMOS in the second stage. This helps increasing headroom for the Vdsof NMOS devices and thus circuits can operate in the high-gain region. In addition, theV* of the second stage devices have been set to around 150mV (we target 2.7V outputswing). The V* of the input pair devices have been set to 100mV in order to achieve lowcurrents for required gm. The V* of the top PMOS current source loads in the first stagehas been designed to be very high (~400mV) in order to minimize the total noise as muchas possible.

We choose cascode compensation techinque in our design particularly because itgives us more degree of freedom (with long equations) to optimize the second polelocations and then Phase Margin [1]. Which will significantly decrease the powerconsumption of our circuit.

Amplifier Schematics

Main Amplifier

M1bM1a

M2bM2a

M3bM3a

M4bM4a

M5bM 5 a

M6bM6a

Mcmf

M8b

M7bM7a

M8a

Vdd

Vss

Vin-Vin+

Vo-Vo+

CcCc

C2C2

Vb6

Vb5

Vb4

Vb3

Vb2

Vb7 Vcmf Vb7

V1

External Feedback Connection CMFB Circuit

Cf

Cf

Cs

Cs

Vin+

Vin-

Vo-

Vo+

Vss

Vo-

Vo+

Cmf

Cmf

Vb6

Vref

Vcmf

Vdd

Mm1

Mmc1

Mmc3

Mmc2

Mmc4

Biasing Network

Mb112

Mb111

Mb1

Mb2

Mb103

Mb104

Mb101

Mb102

Mb110

Mb109

Mb108

Mb107

Mb105

Mb106

Vb6

Vb5 Vb4

Mb117

Mb116Vb2 Vb3

V1

Mb113

Mb114

Mb115

Mb118

Mb119

Mb120

Mb121

Mb122

Mb123

Mb124

Mb125

Mb126

Mb201

Mb202Vb7

First Stage PMOS Biasing First Stage NMOS Biasing Second Stage Biasing

50uA

Devices Parameter

Main Amplifier

W(µm) L(µm) Id(µA) gm(mS) gm/Id(V-1)M1a, b 800 0.35 970 19.3 19.8M2a, b 500 0.5 970 15.9 16.4M3a, b 500 0.5 970 16.2 16.8

M4a, b 2000 1 970 11.3 11.7

M5a, b 2000 1 970 11.5 11.8M6a, b 240 1 970 4.5 4.66M7a, b 600 1 1060 13.7 12.9M8a, b 4000 1 1060 15.4 14.5Mcmf 240 0.35 1940 20.41 10.5

CMFB Circuit

W(µm) L(µm) Id(µA) gm(mS) gm/Id(V-1)Mm1 20 1 66 0.24 3.63Mmc1 100 0.35 23 0.43 18.7Mmc2 100 0.35 43 0.75 17.4Mmc3 2.5 0.35 23 0.23 10Mmc4 2.5 0.35 43 0.31 7.21

Biasing Network

W(µm) L(µm) Id(µA) gm(mS) gm/Id(V-1)Mb1 20 1 50 0.57 11.4Mb2 20 1 50 0.55 11

Mb101 160 1 400 4.53 11.3Mb102 160 1 400 4.42 11.1Mb103 160 1 400 4.53 11.3Mb104 160 1 400 4.42 11.1Mb105 500 1 1250 14.3 11.5

Mb106 500 1 1250 14.03 11.2Mb107 100 1 1250 3.34 2.67Mb108* 400 1 1250 1.56 1.25Mb109 176 1 400 2.63 6.58Mb110* 64 1 400 0.91 2.28Mb111 176 1 400 2.62 6.55Mb112 112 1 400 1.63 4.08Mb113 10 1 25 0.16 6.4Mb114 10 1 25 0.16 6.4Mb115 10 1 25 0.28 11.2Mb116 10 1 25 0.23 9.2Mb117 10 1 25 0.28 11.2Mb118 10 1 25 0.16 6.4Mb119 10 1 25 0.16 6.4Mb120 40 1 100 0.64 6.4Mb121 40 1 100 0.62 6.2Mb122 80 1 200 1.28 6.4Mb123 80 1 200 0.75 3.75Mb124 3 0.5 100 0.38 3.8Mb125 2 0.5 200 0.36 1.8Mb126 120 1 300 3.22 10.7Mb201 100 1 250 1.60 6.4Mb202 29.5 1 250 1.52 6.08

*Devices are in triode regionCapacitor Values

Cf 2.5pFCs 40pFC2 15.5pFCc 13.2pF

Cmf 15fF

Design Process

Initial Considerations

Specifications Settling Accuracy 0.01%Settling Time 100nsDynamic Range 85dBClosed-Loop Gain 16

Feed back FactorThe feedback factor in the circuit is:

Csf

f

CCCC

F++

=

We get Cs = 16Cf from the gain requirement. Assuming that Ci = Cf for the initial design, we get:

18/1=F

Output SwingIn order to lessen the noise requirement as much as possible, we target the peak

output differential voltage at 2.7 V.aldifferentiV peakod V 7.2, =

We set V* of the M7a,b and M8a,b to be around 150mV

Static Accuracy and Open Loop GainWe allocate 50% of the settling error to be static:

%005.05.0 == εε s

As a result, the required open loop gain become:

kF

Adcs

400%005.0

181≈==

εIn the design, we target the open loop DC gain as follow:

( ) angeV output r.over kdBAdc 72 400 112 ±≥

Dynamic Range

Since our peak output signal swing is 2.7 volt, the peak signal power is:

22 V 645.3)7.2(21

==signalP

The minimum required dynamic range is 85dB; therefore, the maximum output noise power that can be tolerated is:

) 6.107(nV 53.1110

645.3 2

1085

2

max, VrmsVPnoise µ==

Ignoring the flicker noise as well as noise from the cascode devices and the second stage, our amplifier has a total output noise given by:

+=

161

34

gmgm

FCTKP

C

Bnoise

By chosen gm6/gm1=1/4 (we set *2,1V =100mV), and from F=18, we get

pF 4.10411

)V 53.11(18

34

2 =

+×

×=

TKC BC

In reality, noises from the cascode and the second stage devices as well as flicker noise isnot negligible. So the value of CC has to be increased:

pF 2.13=CC (Final Design)

Settling

We have chosen %005.0=sε in the previous section, then:%005.0=−= sd εεε

Slewing

Since CL =0 in our design, the total load capacitance become:

( )FCC feffL −= 1, (Ignoring parasitics)

We estimate that the value of Cf should be around 2.5pF (this is set by CI). In addition, Cgd of M8a,b is around 2pF (we have large output devices); therefore, the required current in the second stages from the slewing requirement perspective has to be slightly higher than that of the first stage. The total capacitance at the output node is approximately 18pF.

From our calculations, we allocate 15% of the settling time for the slewing and the other 85% to the linear settling.

In our design, M1a,b have been biased to have a large gm/Id ratio (~20). This makes their Vdsat significantly lower than V* for short channel devices. From SPICE, we get Vdast around 70mV

The maximum input step is 2.7/16=1.6875V; therefore, the current required for the settling time is:

SV

nS

VVTFVV

SRslew

dsatstepi µ12015

181

07.016875.01,, =×

−=

×

−=

The required current in the second stage will be:

mApFSVI d 07.1181205.08 =×

×= µ

Then we have:

%0107.01,

max, =×

=dast

outdlinear V

FVεε

Then we estimate the required ωu as follow:

( ) Mrad/Sec 2230ln175.0 πεω ×== linearlinear

u FT

The factor 0.75 comes from the fact that our circuit is designed to have a phasemargin around 75 Degree, so it has a faster settling time than a one-pole circuit with thesame unity-gain bandwidth by approximately 25% (see appendix 1 on how to set thephase margin)

Then we have:

( ) mSSMradpFgm 1.19/ 22302.131 =××= π

Finally, we get:

mA 55.92

I*

2,1d1 =

×=

Vgm

As expected, the current in the first stage is slightly lower than that in the secondstage

Common-Mode feedback

The common-mode feedback circuit is shown on the previous section. There aretwo design considerations in the design: Unity-Gain bandwidth and Phase Margin. Giventhe value of gmcmf = gm1≈20mS, and Cg,mc1 = 175fF . Then we get

fFCFC

gmCC

Cmfu

C

cmf

mcgmf

mf 55.022

2

1,

≥⇒=≥+

ω

In the final design, we can increase Cmf up to 15fF while maintaining theacceptable common-mode loop phase margin of 50°

Biasing Network

Biasing Network have been carefully designed in order to make all devices in themain amplifier, especially devices in the first stage, operate in the high-gain region. Weuse high-swing biasing schemes in the first stage and use a simple current mirror in thesecond stage. Please note that we connect the gates of Mb124 and Mb125 in bias circuitsto the gate of M1 in the main amplifier in order to track the voltage variation at that node.

Since M4 and M5 are relatively large, we need high current values for the biasdevices connected to their gates in order to ensure proper operations of the circuit duringa fast transient.

Verifications

Performance Summary

Simulation ResultsParametersNominal Fast Slow Specs.

Settling Accuracy (Vod=2.7V) at 100nS 0.0007% 0.0056% 0.0078% 0.01%Settling Accuracy (Vod=0) at 100nS 0.0056% 0.0070% 0.0037% 0.01%Dynamic Range (Vod=0V) 85.1 dB 85.2 dB 85.0 dB 85 dBDynamic Range (vod=2.7V) 85.3 dB 85.1 dB 85.1 dB 85 dBMain Amplifier Power Dissipation 12.3 mW 12.4 mW 12.3 mW Min.Biasing Network Power Dissipation 8.3 mW 8.3 mW 8.2 mW Min.Openloop Gain (Vod=2.7) 115 dB 113 dB 117 dB -Differential Closed Loop Unity-Gain bandwidth (Vod=0) 10.8 MHz 11.5 MHz 10.6 MHz -Differential Loop Phase Margin (Vod=0) 76.8° 76.0° 77.4° -Differential Closed Loop Unity-Gain bandwidth (Vod=2.7V) 10.1 MHz 10.9 MHz 9.8 MHz -Differential Loop Phase Margin (Vod=2.7V) 77.7° 77.1° 78.2° -Common-Mode Loop Unity Gain Bandwidth 17 MHz 16.2 MHz 17.8 MHz -Common-Mode Loop Phase Margin 51.6° 54.1° 50.7° -

Symbol

Wave

D0:A1:NominalGain

D0:A3:FastGain

D0:A5:SlowGain

Type

Expression

Expression

Expression

Design

D0: CASCODEOPEN

D0: CASCODEOPEN

D0: CASCODEOPEN

Result (lin)

90

95

100

105

110

115

120

125

130

135

140

145

Voltages (lin) (vod)

-3

-2

-1

01

23

Gain (dB)=1.131e+002

Output Swing=-2.700e+000

nominal

01:01:11 AM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:GainNominal

D0:A1:GainFast

D0:A2:GainSlow

Type

Expression

Expression

Expression

Design

D0: CASCODELOOP

D0: CASCODELOOP

D0: CASCODELOOP

Result (log)

1m

10m

100m

1

10

100

1k

10k

100k

1x

Frequency (log) (HERTZ)1

10 100 1k 10k 100k 1x 10x 100x1g

Gain=1.00e+000

Frequency=1.08e+007

Gain=6.71e-002

Frequency=1.18e+008

08:30:36 PM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:PhaseNominal

D0:A1:PhaseFast

D0:A2:PhaseSlow

Type

Expression

Expression

Expression

Design

D0: CASCODELOOP

D0: CASCODELOOP

D0: CASCODELOOP

Result (lin)

-100

0

100

Frequency (log) (HERTZ)1

10 100 1k 10k 100k 1x 10x 100x1g

Phase=-1.04e+002

Frequency=1.08e+007

Phase=1.80e+002

Frequency=1.05e+008

08:30:36 PM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:GainNominal

D0:A1:GainFast

D0:A2:GainSlow

Type

Expression

Expression

Expression

Design

D0: CASCODELOOP

D0: CASCODELOOP

D0: CASCODELOOP

Result (log)

1m

10m

100m

1

10

100

1k

10k

Frequency (log) (HERTZ)1

10 100 1k 10k 100k 1x 10x 100x1g

Gain=1.00e+000

Frequency=9.80e+006

Gain=6.76e-002

Frequency=1.07e+008

nominal

08:46:15 PM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:PhaseNominal

D0:A1:PhaseFast

D0:A2:PhaseSlow

Type

Expression

Expression

Expression

Design

D0: CASCODELOOP

D0: CASCODELOOP

D0: CASCODELOOP

Result (lin)

-100

0

100

Frequency (log) (HERTZ)1

10 100 1k 10k 100k 1x 10x 100x1g

Phase=-1.02e+002

Frequency=9.84e+006

Phase=1.79e+002

Frequency=1.07e+008

nominal

08:46:15 PM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:Nominal

D0:A2:Fast

D0:A3:Slow

Type

Expression

Expression

Expression

Design

D0: CMM

D0: CMM

D0: CMM

Result (log)

1m

10m

100m

1

10

100

1k

10k

100k

1x

Frequency (log) (HERTZ)1

10 100 1k 10k 100k 1x 10x 100x1g

Gain=1.00e+000

Frequency=1.78e+00

Gain=1.00e+000

Frequency=1.62e+007

nominal

06:13:58 PM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:Nominal1

D0:A2:Fast1

D0:A3:Slow1

Type

Expression

Expression

Expression

Design

D0: CMM

D0: CMM

D0: CMM

Result (lin)

-100

0

100

Frequency (log) (HERTZ)1

10 100 1k 10k 100k 1x 10x 100x1g

Phase=5.41e+001

Frequency=1.62e+007

Phase=5.07e+001

Frequency=1.78e+007

nominal

06:13:58 PM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:Nominal

D0:A1:Fast

D0:A2:SlowResult (lin)

0

500m

1

1.5

2

2.5

Time (lin) (TIME)

0 100n 200n 300n 400n 500n

nominal

02:16:43 AM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:Nominal

D0:A1:Fast

D0:A2:Slow

Result (lin)

2 699

2.6992

2.6994

2.6996

2.6998

2.7

2.7002

2.7004

2.7006

2.7008

2.701

Time (lin) (TIME)

100n 200n

nominal

02:16:43 AM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:Nominal

D0:A1:Fast

D0:A2:Slow

Result (lin)

-1m

-800u

-600u

-400u

-200u

0

200u

400u

Time (lin) (TIME)

400n

nominal

02:16:43 AM Pacific Daylight Time, 05/13/2003

Wave

D0:A0:Nominal

D0:A1:Fast

D0:A2:Slow

Type

Expression

Expression

Expression

Design

D0: CASCODECLOSED

D0: CASCODECLOSED

D0: CASCODECLOSED

Result (lin)

0

500m

1

1.5

2

2.5

Time (lin) (TIME)

0 200n 400n

nominal

02:47:46 AM Pacific Daylight Time, 05/13/2003

Wave

D0:A0:AmpPowerNominal

D0:A1:AmpPowrerFast

D0:A2:AmpPowerSlow

Type

Expression

Expression

Expression

Design

D0: CASCODECLOSED

D0: CASCODECLOSED

D0: CASCODECLOSED

Result (lin)

11.5m

12m

12.5m

13m

13.5m

Time (lin) (TIME)

0 200n 400n

nominal

02:47:46 AM Pacific Daylight Time, 05/13/2003

Symbol

Symbol

Symbol Wave

D0:A0:Nominal

D0:A1:Fast

D0:A2:Slow

Type

Expression

Expression

Expression

Design

D0: CASCODECLOSED

D0: CASCODECLOSED

D0: CASCODECLOSED

Result (lin)

0

500m

1

1.5

2

2.5

Time (lin) (TIME)

0 200n 400n

nominal

02:55:46 AM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A0:BiasPowerNominal

D0:A1:BiasPowerFast

D0:A2:BiasPowerSlow

Type

Expression

Expression

Expression

Design

D0: CASCODECLOSED

D0: CASCODECLOSED

D0: CASCODECLOSED

Result (lin)

8 2m

8.22m

8.24m

8.26m

8.28m

8.3m

Time (lin) (TIME)

0 200n 400n

nominal

02:55:46 AM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A3:VonNominal

D0:A5:VonFast

D0:A7:VonSlow

Result (lin)

0

20u

40u

60u

80u

100u

Frequency (log) (HERTZ)1u

10u 100u 1m 10m 100m 1 10 100 1k 10k 100k 1x 10x 100x 1g 10g

nominal

03:10:49 AM Pacific Daylight Time, 05/13/2003

Symbol Wave

D0:A4:VonNominal2

D0:A6:VonFast2

D0:A8:VonSlow2

Result (lin)

0

20u

40u

60u

80u

100u

Frequency (log) (HERTZ)1u

10u 100u 1m 10m 100m 1 10 100 1k 10k 100k 1x 10x 100x 1g 10g100g

nom2

03:10:49 AM Pacific Daylight Time, 05/13/2003

Comments And Conclusions

A fully differential CMOS OTA has been designed and simulated. The circuitmeets all requirements at all process corners and consumes 12.4mW form the mainamplifier, 8.3mW from the biasing network. Output swing of +/-2.7V and 85dB dynamicrange have been achieved.

All calculated parameters matched well with the simulation results although weneeded SPICE to adjust our final designs. The noise requires have been significantlyrelaxed by having a high out put swing. Cascode compensation scheme has beensuccessfully employed in the circuits in order to get an optimum phase margin. Althoughthe equations involved in the design are complex, they are seems to be accurate up to acertain level. However, there is no load capacitance in our design and this situation willnever happen in reality. If there were big load capacitance at the out put, the gain-boostedtopology might a better choice since second-stage slewing can be a severe problem thethis case.

The slewing period in the second stage is longer than expected for the maximumoutput voltage swing. From the simulation, the output slew for around 35nS beforeentering the linear settling mode. We guess that this happens because we bias manydevices (especially the input pairs) in low V* region and then they need some extra timeto recover from the “nonlinear node” during the slew period. This is an interesting issuethat might worth investigation in the future.

We use a short-channel non-cascode current source device in our design in orderto lower the required power consumption as much as possible. This badly affects thePSRR and CMRR of our circuits. If they were crucial parts in the design, we muchemploy either cascoded or long-channel device tail current sources. This would decreasethe headroom of the circuit as well as create more body effects to the input pair devices.

References

[1] EE240 Notes on “2-Stage OTA with Cascode Compensation”.

[2] D.B. Ribner and Copeland, “Design Techniques for Cascoded CMOS Op Amps withImproved PSRR and Common-Mode Input Range,” IEEE Journal of Solid-State Circuits,Vol. Sc-19, No.6, pp. 919-925, December 1984

[3] EE240 Lecture Notes, Spring2003

Appendix

Phase Margin and Second Pole Optimization

We use the cascode compensation (Ribner’s style) in our circuit. One advantage of using this method is that we can control the second pole location by adjusting the value of C2.

From [1], locations of non-dominant poles in a cascode compensated circuit are:

( )DP n ±−= 13,2 ω

Where

−−

=

fTo

CCn

FCCCC

gm

1

12

3ω

−−

−−=

fTo

C

fTxTo

TxC

eff

C

FCCC

CCCCC

CC

gmgm

D 141 2,23

7

CTx and CTo are total capacitance at the input and output nodes, respectively.

We select *3V to be around 120mV (We choose relatively low *

3V low to makesure that our devices are always in the high-gain region). From the previous calculations,we have F=18, Cc=13.2pF, CTo=18pF, Id3=0.955mA. Then we get:

Mrad/S

pFpFpFpF

mAn 2368

18/2.13182.131

12.1312.022955.0 πω ×=

−

−××

×=

Since the targeted phase margin is 75°, then we get:

SecMradFP u / 250)75tan(2 πω ×=×= o

As a result, the required value of D is 0.746 (from the equation above). Pleasenote that P3 has been put the very high frequency, approximately at 2ωn.

The value of CTx is Cf/F= 45pF, and from the data about M7 obtained from theprevious calculations, we get:

( )

−

−−×

×××

−=18/5.218

2.1315.21845

452.132.13955.015.007.112.041746.0 2

,2 pFpFpF

pFpFpFpFpF

CpF

mAmA

eff

pFC eff 36,2 =In our circuits, Cgs7=14.1pF, Cgd4=1pF, then we need C2=36-15.1=20.9pF

However, from our simulations, using a high value of C2 increases the total outputnoise. Moreover, the calculations above use only the estimated initial design values. Thenin the final design we have:

C2 = 15.5pF.

The obtained phase margin is around 77°