A Comparative Study on a SOI-CMOS Capacitive Feedback Op-Amp Using different Bias Circuits for High Temperature Application

Jeongwook Koh�, Muthukumaraswamy Annamalai Arasu and Minkyu Je

Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research) kohj@ime.a-star.edu.sg

Abstract. In this paper, we present comparative study on implementation of 1.0 um SOI-CMOS capacitive feedback op-amps using two different bias circuits, constant-gm bias and constant-current bias circuits for down-hole drilling application among high temperature electronics from 0 °C to 225 °C. Temperature dependence of leakage current and output resistance are investigated for high temperature operation of the op-amp and bias circuits. And the temperature dependence of open-loop ac characteristics of op-amps with two different bias circuits and the temperature dependence of closed-loop ac characteristics of capacitive feedback op-amp using these bias circuits are analyzed in this paper.

Keywords: SOI-CMOS, Op-amp, capacitive feedback, high temperature electronics, constant-gm bias, constant current bias

1. Introduction High temperature electronics finds many applications like automotive, aerospace, nuclear and down-hole

drilling. Those applications require a reliable operation at elevated temperature. Electronics used in down-hole-drilling application is to explore modern oil/gas wells through collecting, logging and/or processing data such as heading and inclination, temperature and pressure of the strata. The biggest obstacle for electronic data acquisition systems in deep wells is the high temperature (>170°C) encountered at great depth. Reliable high-temperature performance (up to 225°C, ambient) is a requirement due to the extreme temperatures encountered in deep wells typically over 2 km depth below the surface of the earth/sea bed [1].

Conventional integrated circuit (IC) technology like a bulk-CMOS technology is not capable of operating at these high temperatures. As temperature increases, several phenomena arise in bulk-CMOS technology - mobility degradation, threshold voltage down-shift and anomalous increase of leakage current with increasing temperature. Among them, anomalous increase of leakage current is the most serious problem limiting analog circuit performance and more seriously destroy the chip due to latch-up. SOI-CMOS technology is more attractive than bulk-CMOS technology thanks to reduction of this “excess” leakage current at high temperature regime [2].

In addition to technology consideration, analog circuit design consideration need to be considered for high temperature electronics. An important concept for an operational amplifier is to maintain a stable dc gain, speed and stability over operating temperature ranges. Generally those parameters have a direct dependency on a dc bias circuit. Literature study shows two popular techniques for high temperature operation, a constant-gm bias circuit and constant-current bias circuit [3] [4].

In this paper we make a comparative study on a 5V1.0 um SOI-CMOS (XI10 by X-FAB Semiconductor Foundry AG) capacitive feedback op-amp using these two bias schemes for high temperature operation. A � Corresponding author. Tel.: + 65 6770 5591 fax: +65 6774 5754. E-mail address: kohj@ime.a-star.edu.sg

2012 International Conference on Solid-State and Integrated Circuit (ICSIC 2012) IPCSIT vol. 32 (2012) © (2012) IACSIT Press, Singapore

temperature range in the study is chosen from 0 °C to 225 °C for down-hole drilling application among high temperature electronics.

2. Considerations for High Temperature Op-Amp 2.1. Junction Leakage Current

The junction leakage current is remarkably smaller (3 order) in SOI transistor than in bulk transistors due to the reduced junction area and the absence of diffusion leakage towards the substrate [5]. Fig. 1 shows the junction leakage current with increasing temperature in 1.0 um SOI-CMOS transistors. With increasing temperature the junction leakage current increases for both of nMOS and pMOS transistors. The nMOS transistor junction leakage current decreases with the reduction of gate length and no gate-length dependency of the junction leakage current of pMOS transistor is found. We observe no further increase of the pMOS transistor junction leakage current beyond 175 °C. It is also found that pMOS transistor has 4 times less leakage current in the gate length from 4 to 5 um.

2.2. Output Resistance The output resistance is a parameter determining gain of an op-amp. The output resistor of a MOS

transistor is expressed using drain-source current IDS and channel length modulation parameter λ as (1)

The channel length modulation parameter is inversely proportional to gate length of MOS transistors. Fig. 2 shows the temperature dependence of channel length modulation parameter for nMOS and pMOS

Fig. 1 Junction leakage current of SOI transistor over temperature 0 °C to 225 °C

Fig. 2 Channel length modulation parameter of SOI transistor over temperature from 0 °C to 225 °C

transistor with different gate length from 4 to 5 um. Fig. 2 indicates pMOS transistor has 2.5 times more channel length modulation parameter. As temperature increases, channel length modulation parameter decreases for both of nMOS and pMOS transistor. With consideration of channel temperature behavior of junction leakage current and channel length modulation parameter (Fig. 1 and Fig. 2) gate lengths from 4 to 5 um are used for the design in this study.

3. Design of Bias Circuits High temperature effects of MOS transistors including mobility degradation, threshold voltage down-

shift, increase of leakage current cause degradation of op-amp design parameters which are gain and unity-gain-bandwidth. These parameters can be maintained stable by using constant-gm current bias circuit and constant-current bias circuits [3] [4].

3.1. Constant Gm Bias Current Circuit Transconductance (gm) is a critical parameter in many analog circuits. Transconductance determines a

dc gain, speed (bandwidth) and stability of an operational amplifier. The transconductance of a MOS in saturation region is given by

(2) where W and L are the channel width and length of the transistor. To reduce temperature variation of transconductance gm, a bias circuit is used to generate a bias current

IB with a temperature dependence inversely proportional to that of mobility [6]. IB is given by (3)

where K is the gate width ratio of MN2 and MN1 and sets to 4 in the design (Fig. 3).Transconductance of a transistor biased by this circuit is

(4) When RS has a zero-temperature coefficient, transconductance will be stable over temperature. Fig. 3 shows the schematic of const-gm current bias circuit and design result, the transconductance of

MN1 over 0 °C to 225 °C for nominal corner (NN) and two worst corners (FS, SF). The transconductance is designed to have 50 uS with ±3 % accuracy for all corners from 0 °C to 225 °C.

Fig. 3 Const-Gm bias circuits and the transconductance of MN1 over temperature from 0 °C to 225 °C

3.2. Constant Current Bias Current Circuit Fig. 4 shows the schematic of constant-current bias circuit and the reference current over 0 °C to 225 °C

for nominal corner (NN) and two worst corners (FS, SF). The reference current is designed to 10 uA with ±1 % accuracy for all corners from 0 °C to 225 °C.

4. Design of Op-Amp Fig. 5 (a) shows the schematic of the op-amp core and a capacitive feedback op-amp in the design. The

op-amp core is a two stage miller amplifier which has a folded cascode pMOS input stage for high dc gain. A pMOS input stage is selected since pMOS has less 1/f noise & DC offset characteristics in the XI10 1.0 um SOI-CMOS technology. And, in addition, pMOS has a less substrate leakage current with temperature rising (Fig. 1). An inverting amplifier is selected in the second stage and is designed to drive high capacitance for measurement environment. In the inverting amplifier, nMOS cascode current source is used for op-amp to have lower output resistance since pMOS transistor output resistance is at least three times less (Fig. 2).

This op-amp is used for a capacitive feedback op-amp in Fig. 5 (b). If C2 in Fig. 5 (b) is variable capacitance as in a capacitive MEMS accelerometer, Fig. 5 (b) is called capacitance-voltage converter (CVC), a widely used MEMS accelerometer analog interface circuit [7]. The capacitive feedback op-amp is designed to have an amplification of 20 dB in the frequency range from 200 Hz to 200 kHz from 0 °C to 225 °C. The capacitive feedback will be used in receiver analog frontend in a MEMS accelerometer acoustic telemetry IC for down-hole drilling application.

Fig. 5. (a) Op Amp Core (b) Capacitive Feedback Op-Amp

Fig. 4 Const Current bias circuits and reference current over temperature from 0 °C to 225 °C

5. Design Results Fig. 6 shows the open-loop ac characteristics of two different op-amps which have two different bias

circuits, constant-gm bias circuit and constant current bias circuit. Gain of constant-gm op-amp stays stable (112 dB) up to 200 °C and reduces to 110 dB at 225 °C. Gain of constant-current op-amp increases from 112 dB at 0 °C to 116 dB at 225 °C. Unity-gain-bandwidth of constant-gm op-amp increases from 3.4 MHz at 0 °C to 3.8 MHz at 225 °C, while that of constant-current op-amp decreases from 3.4 MHz at 0 °C to 2.4 MHz at 225 °C.

Fig. 7 shows the closed-loop ac characteristics of two different capacitive feedback amplifiers, constant-gm capacitive feedback op-amp and constant-current capacitive feedback op-amp. The closed-loop gains of two capacitive feedback amplifiers are same (20 dB) and the closed-loop gain stays stable over the temperature from 0 °C to 225 °C. The low cut-off frequencies of them are also same (162 Hz) and this does not change with temperature. The high cut-off frequency of constant-gm capacitive feedback op-amp increases from 308 kHz at 0 °C to 359 kHz at 225 °C while that of constant-current capacitive feedback op-amp decreases from 346 kHz at 0 °C to 257 kHz at 225 °C. This is because bias current of constant-current capacitive feedback op-amp is kept constant over temperature and thus temperature dependant mobility degradation causes 1st stage transconductance degradation which determines high cut-off frequency. Otherwise the 1st stage transconducance of constant-gm capacitive feedback op-amp increases because it has nMOS constant-gm bias circuit and pMOS input transistors in the op-amp. As temperature increases, 1st stage transconductance increases in this configuration.

Fig. 7 Closed-loop ac characteristics of two different capacitive feedback op-amps

Fig. 6 Open-loop ac characteristics of two different op-amps

Fig. 8 Current consumption of two different op-amps

Fig. 8 shows the current consumption of two different op-amps. As expected from bias schemes in op-

amps, constant-current op-amp consumes stable current consumption of 1.03 mA from 0 °C to 225 °C and constant-gm op-amp has increasing current consumption from 0.91 mA at 0 °C to 2.51 mA at 225 °C.

6. Conclusion This paper presented comparative study on implementation of 1.0 um SOI-CMOS capacitive feedback

op-amps using two different bias circuits, constant-gm bias and constant-current bias circuits for high temperature application from 0 °C to 225 °C. Temperature dependence of leakage current and output resistance were considered for high temperature operation of the op-amp and bias circuits. We investigated the temperature dependence of open-loop ac characteristics of op-amps with two different bias circuits and also investigated the temperature dependence of closed-loop ac characteristics of capacitive feedback op-amp using these bias circuits. The closed-loop gains of two capacitive feedback amplifiers are same (20 dB) and the closed-loop gain stays stable over the temperature from 0 °C to 225 °C. The low cut-off frequencies of them are also same and this does not change with temperature. The high cut-off frequency of constant-gm capacitive feedback op-amp increases from 308 kHz at 0 °C to 359 kHz at 225 °C while that of constant-current capacitive feedback op-amp decreases from 346 kHz at 0 °C to 257 kHz at 225 °C.

7. References [1] S. P. Rountree et al, “High Temperature Measurement While Drilling Systems and Applications”, 5th International

HiTEC Conference, 2000

[2] Eggermont et al, “Design of SOI CMOS operational amplifiers for applications up to 300 °C”, IEEE J. Solid-State Circuits, vol. 31, no.2, pp. 179-186, 1996

[3] Cu, A High -Temperature, High-Voltage, Fast Response Time Linear Regulator in 0.8um BCD-on-SOI, University of Tennessee, Knoxville, 2010

[4] Yu, High-Temperature Bulk-CMOS Integrated Circuits for Data Acquisition, Ph. D Dissertation, Case Western Reserve University, 2006

[5] M. Willander and H. L. Hartnagel, eds., High Temperature Electronics, London: Chapman & Hall, 1999

[6] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001

[7] N. Yazdi, H. Kulah and K. Najafi, “Precision readout circuits for capacitive microaccelerometers”, in IEEE sensors proceedings, vol.1, pp. 28-31, 2004