a complete reliability solution: reliability modeling ... · • tmi aging model offered three...
TRANSCRIPT
Confidential
A Complete Reliability Solution: Reliability Modeling, Applications, and Integration in Analog Design Environment Tianlei Guo, Jushan Xie Cadence Design Systems, Inc. June 19, 2018
2 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Project Vision
• Make reliability analysis relevant by providing – Predictive aging models – Aging analysis accelerated by temperature, process variation, … – Support mission profiles
Design for Reliability
Failure is NOT an Option
3 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Simulating Device Aging
4 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Terminology for Device Reliability Analysis
• Age – Device age is a parameter that represents the device degradation physical
phenomena • Age (or lifetime or degradation) model
– Predicts the degradation in device characteristics due to a physical phenomena, such as HCI, NBTI, PBTI, TDDB, …
• Aged (or degraded) model – is a device SPICE model that represents the effects of all kind of
degradations at particular future time value • Fresh Simulation
– Is a simulation without degradation or a simulation at time = 0 • Stress Simulation
– Is a simulation that represents the stress condition • Aging (or EOL) simulation
– is a simulation with worst case device degradation due to electrical stress, a simulation at the end of life
5 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
HCI (Hot Carrier Injection)
Ben Kaczer, 2016 IEDM tutorial
6 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
BTI (Bias Temperature Instability)
NBTI: NMOS BTI PBTI: PMOS BTI strong
7 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
TDDB (Time-Dependent Dielectric Breakdown)
Ben Kaczer, 2016 IEDM tutorial
8 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Cadence Aging Reliability Support
9 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Aging Analysis in Spectre
10 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Aging Reliability Analysis HCI and NBTI/PBTI Analysis Flow
Fresh
Aging/EOL
Stress
Circuit Netlist + Reliability Model
Fresh Simulation
Device Degradation, Lifetime
Degraded model/netlist Generation
Aging Simulation
Waveform Compare Circuit degradation Check
Stressing
Aging
11 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• Reliability effects supported: – Built-in HCI, NBTI and PBTI – other mechanisms possible via URI (eg. TDDB, GOI)
• SPICE Models supported for degradation: – BSIM3, BSIM3V3, BSIM4, BSIMSOI, MOS9, MOS11, PSP 102, PSP 103,
HVMOS, HISIM2 and HISIM_HV. – BSIMCMG, BSIMIMG, UTSOI, UTSOI2 – BJT: VBIC, HiCUM and MEXTRAM – Resistor: native and R3 – Diode – Verilog-A
• Reliability models: – ageMOS: Cadence proprietary reliability model for HCI, NBTI and PBTI (with
recovery) and degraded model generation (for legacy nodes). – ageMOS2: Cadence proprietary reliability model for advance nodes. – URI: API to allow customer implement own reliability models. – TMI-aging, TMI self-heating models, TMI TDDB
Reliability Models supported
12 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• The Virtuoso Unified Reliability Interface (URI) allows you to add your own (custom/proprietary) reliability equations/models and supports user-defined degradation models
Virtuoso Unified Reliability Interface (URI) Using Custom Reliability Models
RelXpert Spectre APS/XPS
C code Custom/Proprietary reliability equations
URI
Reliability Simulation Results
Netlist with your own reliability model
13 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
TMI Simulation flow • TMI Aging model offered three simulation flows with .option tmiAge=1
– Aging only simulation flow. (tmishe=0) – Aging stress w/o self-heating effect ( calculate degradation rates under TempE ) – Measurement simulation w/o self-heating effect.
– Self-Heating only simulation flow. (tmishe=1) – w/o aging stress. – Measurement simulation w/i self-heating effect.
– Aging simulation with self-heating effect. (tmishe=2) – Aging stress w/i self-heating effect ( calculate degradation rates under
TempE+dtemperature ). – Measurement simulation either w/i or w/o self-heating effect.
tmiShe Self-heating aging 0 - Yes default 1 Yes - 2 Yes Yes
14 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Spectre/TMI interface in ADE
15 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
RelXpert Spectre Native ageMOS HCI, NBTI, PBTI, TDDB* X X ageMOS2 HCI, NBTI, PBTI, TDDB* X X
Extraction X (verification) TMI HCI, BTI, TDDB X X URI Running X X
Model development, 3rd party spice X Self-heating Built-in (bsimcmg, bsimimg) X X
Spectre-SHE X X TMI-SHE X X
MC-aging ageMOS, ageMOS2 X TMI X
Reliability models support matrix
TDDB*: prototype
16 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
New Aging Model
17 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Model HCI Degradation Saturation Effect
1.E-13
1.E-11
1.E-09
1.E-07
1.E-05
1.E-03
1.E-01
1.E-08 1.E-06 1.E-04 1.E-02 1.E+00 1.E+02 1.E+04 1.E+06 1.E+08
HCI(Vgs=1V)
Vds=0.8V 1.2V 1.6V
Degradationsaturation
V. Huard, IEDM, 2007
“New Generation Reliability Model”, S.-Y. Liao, C. Huang, T. Guo, A. Chen, Jushan Xie, Cadence Design Systems, Inc. S. Guo, R. Wang, Z. Yu, P. Hao, P. Ren, Y. Wang, R. Huang, Peking University, MOS-AK December 2016
http://www.mos-ak.org/berkeley_2016/publications/T11_Xie_MOS-AK_Berkeley_2016.pdf
18 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
1E-71E-51E-3 0.1 10 1000 1E-71E-51E-3 0.1 10 1000(a)
FinFET silicon dataNBTI stress
ΔVT
H(a.
u.)
Time(s)
FinFET silicon dataNBTI stress
Conventional model A (Power law) (b)
Conventional model B (Log law)
ΔVT
H(a.
u.)
Time(s)
1E-7 1E-5 1E-3 0.1 10 1000 1E-7 1E-5 1E-3 0.1 10 1000(c)
FinFET silicon data NBTI recvoery
Convertional model A (Power law)
Norm
aliz
ed Δ
VTH
(a.u
.)
Time(s)
FinFET silicon data NBTI recovery
Convertional model B(Log law) (d)
Norm
aliz
ed Δ
VTH
(a.u
.)
Time(s)1E-7 1E-5 1E-3 0.1 10 1000 1E-7 1E-5 1E-3 0.1 10 1000
(c)
FinFET silicon data NBTI recvoery
Convertional model A (Power law)
Norm
aliz
ed Δ
VTH
(a.u
.)
Time(s)
FinFET silicon data NBTI recovery
Convertional model B(Log law) (d)
Norm
aliz
ed Δ
VTH
(a.u
.)
Time(s)
Model limitation in FinFET BTI effect (log-log nonlinear)
TD model RD model
RD model TD model
19 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Model result demonstration – New BTI models New model equations for FinFET: DC verification
• Curve slope changed against time (in log-log, or log-lin scale) • Gate bias dependency changed
1E-5 1E-3 0.1 10 1000 1E-5 1E-3 0.1 10 1000
(d)(c)
(a) Stage 2
Stage 1
Stage 2 Stage 2Stage 1
Stage 2
Stage 1
Vg=0V, -0.2V, -0.4V, -0.6V
Vg=-1.3V, -1.4V, -1.5V, -1.6V
NBTI stress
NBTI stress
Stage 1
(b)
T=50°C, 75°C,
100°C, 125°C
T=50°C, 75°C, 100°C, 125°C
NBTI recoveryNBTI Recovery
ΔVT
H (a
.u.)
ΔVT
H (a
.u.)
Time (s)
lines: new modelsymbols: FinFET silicon data
lines: new modelsymbols: FinFET silicon data
lines: new modelsymbols: FinFET silicon data
Time (s)
lines: new modelsymbols: FinFET silicon data
1E-5 1E-3 0.1 10 1000 1E-5 1E-3 0.1 10 1000
(d)(c)
(a) Stage 2
Stage 1
Stage 2 Stage 2Stage 1
Stage 2
Stage 1
Vg=0V, -0.2V, -0.4V, -0.6V
Vg=-1.3V, -1.4V, -1.5V, -1.6V
NBTI stress
NBTI stress
Stage 1
(b)
T=50°C, 75°C,
100°C, 125°C
T=50°C, 75°C, 100°C, 125°C
NBTI recoveryNBTI Recovery
ΔVT
H (a
.u.)
ΔVT
H (a
.u.)
Time (s)
lines: new modelsymbols: FinFET silicon data
lines: new modelsymbols: FinFET silicon data
lines: new modelsymbols: FinFET silicon data
Time (s)
lines: new modelsymbols: FinFET silicon data
1E-5 1E-3 0.1 10 1000 1E-5 1E-3 0.1 10 1000
(d)(c)
(a) Stage 2
Stage 1
Stage 2 Stage 2Stage 1
Stage 2
Stage 1
Vg=0V, -0.2V, -0.4V, -0.6V
Vg=-1.3V, -1.4V, -1.5V, -1.6V
NBTI stress
NBTI stress
Stage 1
(b)
T=50°C, 75°C,
100°C, 125°C
T=50°C, 75°C, 100°C, 125°C
NBTI recoveryNBTI Recovery
ΔVT
H (a
.u.)
ΔVT
H (a
.u.)
Time (s)
lines: new modelsymbols: FinFET silicon data
lines: new modelsymbols: FinFET silicon data
lines: new modelsymbols: FinFET silicon data
Time (s)
lines: new modelsymbols: FinFET silicon data
Slope1
Vgsdependence1
Slope2
Vgsdep.2
Slope1
Vgsdep.1Slope2
Vgsdep.2
Stress phase Recovery phase
20 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Model result demonstration – New BTI models History effect: sequential simulation step
Time
Time
ΔDeg
0
Vgsstress
t1
Vgs1
Stressphase
t2
Vgs2
Recoveryphase
t3
Vgs3
Stressphase
21 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
BTI model with recovery effect -New Model
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Degrad
ation[a.u
.)
Time[s]
Vgs
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Degrad
ation[a.u
.)
Time[s]
Stressonly
Simu.Result
-1V
-1.2V
-1.4V
-1.6V
0V
22 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
BTI model prediction with recovery effect
103 104 105 106 107
Degradation results@3years
Type B
ΔV
TH (a
.u.)
Frequency(Hz)
Type A
(b)10-3 100 103 106 109
ΔV
TH (a
.u.)
Time(s)
w/ recovery wo/ recovery
Iterated resultsIteration step:N=10 (a)
Over-estimationin3years
Vgs
Time
Duty=50%
Aperiodicsquarewaveformisappliedonaninvertorduringafewmilliseconds.Thenpredictionfor3years.
23 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Comparison of AgeMOS and AgeMOS2
AgeMOS
§ Developed around 1995 § Based on Lucky-Electron model § Degradation log-log linear § Many enhancements § Using skew parameters
− Vth, U0, Ua, Ub, Nfactor, Vsat, … § Simple recovery model
− linear extrapolation
§ Current CMC Approach
AgeMOS2
§ Developed around 2015 § Based on trapping/de-trapping
model § Degradation log-log nonlinear § Degradation saturation/history
effect § Using degradation directly
− Vth and Ids degradation
§ Recovery with step-wise model − More accurate − Frequency dependency
24 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
AgeMos2 Model Extraction (Standalone tool)
Grouped reliability characteristics, such as degradation vs. time curves with varying Vds for a
fixed temperature.
Loading the data, and treating it for
extraction preparation, such as sorting, regrouping, data checking, etc.
Specified reliability model parameter
extraction
Data complete
Output EDA readable reliability modelcard
Fitting error report compared to the
input data, simulation results in text files,
graphically, etc.
No
Yes
25 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Reliability Monte Carlo
26 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Reliability Variation Components
Variation Aging variation
(AV)
Process Variation
(PV)
Correlation
27 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Simulation Diagram for Flow I (1+N flow) (Aged model + Process Variation))
Mean Aging calculations
Aged spice model generations
Mean reliability model
Mean spice model Mean transistor-level simulation
Fresh
PV transistor-level simulation
Stress
MC Aging
Mean fresh
Degradation variation
MC RUNs: 1+N
N
• Can perform Aging MC with current foundry aging + MC model • Not expensive
28 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Simulation Diagram for Flow II (N+N flow) (Age Variation + Process Variation)
AV aging calculations
Aged spice model generations
AV reliability model
PV spice model PV transistor-
level simulation
MC Fresh
PV transistor-level simulation
MC Stress
MC Aging
Fresh variation
Degradation variation
MC RUNs: N+N
N
N
N
29 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
VTH Comparison between Flow Zero, I and II
0
20
40
60
80
100
-0.52 -0.5 -0.48 -0.46 -0.44 -0.42
Flow I
Flow II
Flow Zero
VTH (V)
Flow Zero & Flow I
Fresh Aged
µ=-0.487 σ=0.0120
µ=-0.487 σ=0.0044
µ=-0.437 σ=0.0045
Ø Variation distribution (Y-axis) Ø Variation of aged VTH of flow I (only PV) is smaller than flow II (PV + AV)
30 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Process Variation and Aging Variation Correlation
Ø Aged VTH and IDS variation become smaller after considering correlation between PV/AV
Spectre syntax for correlation analysis
31 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Scatter Points for Operation Outputs
Ø The scatter points between aged VTH and aged IDS, GM, GDS, ROUT, IGS, and VDSAT Ø The correlation between PV/AV makes the outputs correlation more complicated
32 © 2017 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
13-Stage Ring Oscillator Waveform Variation
Ø Flow II shows the fresh and aged RO waveform variation. The voltage degradation variation includes the PV-aware age calculations