POWER OPTIMIZATION OF CMOS PROGRAMMABLE GAIN AMPLIFIERS WITH HIGH DYNAMIC RANGE AND COMMON-MODE FEED-FORWARD CIRCUIT

A. J. Ginés*, R. Doldán, A. Rueda and E. Peralías

Instituto de Microelectrónica de Sevilla (CNM-CSIC)University of Seville (Spain)

IEEE ICECS 2010

Motivations

State-of-the-Art in Low Voltage PGAs

Close-loop vs. Open-loop Architectures

Proposed PGA Architecture

Design Methodology

Common-Mode Feed-forward Circuit (CMFFC)

Verification:

Post-layout Simulation Results (3-stage PGA)

Experimental Results (stage core)

Conclusions

Contents

IMSE-CNM ICECS 2010, Athens (Greece)

Low-IF ZigBee Receiver

Motivations

1

ZigBee should operate with power levels at the antenna from -85dBm to -20dBm (DR > 64dB).

Adjustable gain through the chain is need to optimize the sensitivity and signal-to-noise ratio (SNR).

Power consumption is one of the most critical design constraints in ZigBee standard.

RF Filter

LNA

FrequencySynthesizer

I

Q Cha

nne

lF

ilter90º

ADC

PLL

Mixers

ADC

PGA

PGA

IMSE-CNM ICECS 2010, Athens (Greece)

Low-IF ZigBee Receiver

Motivations

1

This Work

RF Filter

LNA

FrequencySynthesizer

I

Q Cha

nne

lF

ilter90º

ADC

PLL

Mixers

ADC

PGA

PGA

ZigBee should operate with power levels at the antenna from -85dBm to -20dBm (DR > 64dB).

Adjustable gain through the chain is need to optimize the sensitivity and signal-to-noise ratio (SNR).

Power consumption is one of the most critical design constraints in ZigBee standard.

Motivations

State-of-the-Art in Low Voltage PGAs

Close-loop vs. Open-loop Architectures

Proposed PGA Architecture

Design Methodology

Common-Mode Feed-forward Circuit (CMFFC)

Verification:

Post-layout Simulation Results (3-stage PGA)

Experimental Results (stage core)

Conclusions

Contents

IMSE-CNM ICECS 2010, Athens (Greece)

Close-loop Architectures

State-of-the-Art in Low Voltage PGAs

2

-

+

+

-

Rf

Rf

Rin

RinVinp

Vinn Voutp

Voutn

G = Rf / Rin

IMSE-CNM ICECS 2010, Athens (Greece)

Close-loop Architectures

State-of-the-Art in Low Voltage PGAs

2

-

+

+

-

Rf

Rf

Rin

RinVinp

Vinn Voutp

Voutn

Take advantage of resistive feedback to achieve:High Linearity

Low Noise

G = Rf / Rin

IMSE-CNM ICECS 2010, Athens (Greece)

Close-loop Architectures

State-of-the-Art in Low Voltage PGAs

2

-

+

+

-

Rf

Rf

Rin

RinVinp

Vinn Voutp

Voutn

Take advantage of resistive feedback to achieve:High Linearity

Low Noise

Drawbacks of the classical approach:Gain programmability introduces stability issues.

Low voltage limitations due to equal common modes (cmi = cmo).

Buffers are required to deal with low input impedance.

G = Rf / Rin

IMSE-CNM ICECS 2010, Athens (Greece)

Close-loop Architectures

State-of-the-Art in Low Voltage PGAs

2

-

+

+

-

Rf

Rf

Rin

RinVinp

Vinn Voutp

Voutn

Take advantage of resistive feedback to achieve:High Linearity

Low Noise

Drawbacks of the classical approach:Gain programmability introduces stability issues.

Low voltage limitations due to equal common modes (cmi = cmo).

Buffers are required to deal with low input impedance.

-

+

+

-

Rin

Rin

-

+

+

-

Rf

Rf

Voutp

Voutn

CDN

CDN

IS

IS D

(1-D)IS

Vinp

Vinn

Reference: [3]

Current Division Network (CDN)

G = Rf / Rin

IMSE-CNM ICECS 2010, Athens (Greece)

Close-loop Architectures

State-of-the-Art in Low Voltage PGAs

2

-

+

+

-

Rf

Rf

Rin

RinVinp

Vinn Voutp

Voutn

Take advantage of resistive feedback to achieve:High Linearity

Low Noise

Drawbacks of the classical approach:Gain programmability introduces stability issues.

Low voltage limitations due to equal common modes (cmi = cmo).

Buffers are required to deal with low input impedance.-

+

+

-

Rf

Rf

Rin

RinVinp

Vinn Voutp

Voutn

VREFin -+

VREFout-+

Decoupling common mode (cmi ≠ cmo)

Reference: [4]

G = Rf / Rin

IMSE-CNM ICECS 2010, Athens (Greece)

Close-loop Architectures

State-of-the-Art in Low Voltage PGAs

2

-

+

+

-

Rf

Rf

Rin

RinVinp

Vinn Voutp

Voutn

Take advantage of resistive feedback to achieve:High Linearity

Low Noise

Drawbacks of the classical approach:Gain programmability introduces stability issues.

Low voltage limitations due to equal common modes (cmi = cmo).

Buffers are required to deal with low input impedance.

Reference: [6]

Transimpedance amplifier

G = Rf / Rin

IMSE-CNM ICECS 2010, Athens (Greece)

Close-loop Architectures

State-of-the-Art in Low Voltage PGAs

2

-

+

+

-

Rf

Rf

Rin

RinVinp

Vinn Voutp

Voutn

Take advantage of resistive feedback to achieve:High Linearity

Low Noise

Main drawback for ZigBee:High power consumption is required for driving resistive load.

It does not take advantage of the standard linearity relaxation.

Solution: Open-loop topologies !!!

G = Rf / Rin

IMSE-CNM ICECS 2010, Athens (Greece)

Open-loop Architectures

State-of-the-Art in Low Voltage PGAs

3

-

+

+

-

Ro

Vinp

VinnVoutp

Voutn

gm

Ro

G = gmRo

IMSE-CNM ICECS 2010, Athens (Greece)

Open-loop Architectures

State-of-the-Art in Low Voltage PGAs

3

-

+

+

-

Ro

Vinp

VinnVoutp

Voutn

gm

Ro

M1 M2

Vc

Vinn Vinp

Voutp VoutnRo Ro

+

-

Advantages:High-speed and high-stability

Low-Power

References: [8-10]

Gilbert’s Cell

G = gmRo

IMSE-CNM ICECS 2010, Athens (Greece)

Open-loop Architectures

State-of-the-Art in Low Voltage PGAs

3

-

+

+

-

Ro

Vinp

VinnVoutp

Voutn

gm

Ro

M1 M2

Vc

Vinn Vinp

Voutp VoutnRo Ro

+

-

Advantages:High-speed and high-stability

Low-Power

Drawbacks:Gain is not accurately defined.

Low-voltage operation.

Non-linearity

References: [8-10]

Gilbert’s Cell

G = gmRo

IMSE-CNM ICECS 2010, Athens (Greece)

Open-loop Architectures

State-of-the-Art in Low Voltage PGAs

3

M2M1 M4

M3

Voutp

Voutn

Vinn Vinp

-

+

+

-

Ro

Vinp

VinnVoutp

Voutn

gm

Ro

M1 M2

Vc

Vinn Vinp

Voutp VoutnRo Ro

+

-

Advantages:High-speed and high-stability

Low-Power

Drawbacks:Gain is not accurately defined.

Low-voltage operation.

Non-linearity

References: [8-10]

Gilbert’s Cell

G = gmRo

IMSE-CNM ICECS 2010, Athens (Greece)

Open-loop Architectures

State-of-the-Art in Low Voltage PGAs

3

M2M1 M4

M3

Voutp

Voutn

Vinn Vinp

-

+

+

-

Ro

Vinp

VinnVoutp

Voutn

gm

Ro

M1 M2

Vc

Vinn Vinp

Voutp VoutnRo Ro

+

-

Advantages:High-speed and high-stability

Low-Power

Drawbacks:Gain is not accurately defined.

Low-voltage operation.

Non-linearity

References: [8-10]

Gilbert’s Cell

G = gmRo

IMSE-CNM ICECS 2010, Athens (Greece)

Open-loop Architectures with Feed-back

State-of-the-Art in Low Voltage PGAs

4

M2M1

Vinn

Ioutp Ioutn

2RSResistive degeneration enhances linearity

IMSE-CNM ICECS 2010, Athens (Greece)

Super-Source Follower (SSF) [18,19]

Open-loop Architectures with Feed-back

State-of-the-Art in Low Voltage PGAs

4

M2M1

Vinn

Ioutp Ioutn

2RS

Mfb2M1fb1

Vinn

Ioutp Ioutn

2RS

-+ Vinp

-+(CS)

OTA

Vinn

2RS

Mfb2M1fb1

- +

Vinp

-+

Ioutp Ioutn

Resistive degeneration enhances linearity

Further ImprovementReferences: [18-22]

This Work

Gain Boosting

Servo-loop [20,21]

Motivations

State-of-the-Art in Low Voltage PGAs

Close-loop vs. Open-loop Architectures

Proposed PGA Architecture

Design Methodology

Common-Mode Feed-forward Circuit (CMFFC)

Verification:

Post-layout Simulation Results (3-stage PGA)

Experimental Results (stage core)

Conclusions

Contents

IMSE-CNM ICECS 2010, Athens (Greece)

A 1.2V 72dB 3-stage PGA in 90nm CMOS process

Proposed Low Power PGA Architecture

5

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

IMSE-CNM ICECS 2010, Athens (Greece)

A 1.2V 72dB 3-stage PGA in 90nm CMOS process

Proposed Low Power PGA Architecture

5

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

2RS

BiasN

M5 M3

M1+

-

M4

M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

IMSE-CNM ICECS 2010, Athens (Greece)

A 1.2V 72dB 3-stage PGA in 90nm CMOS process

Proposed Low Power PGA Architecture

5

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

How much currents in 90nm CMOS?

Stress due to trench isolation barriers!!!

2RS

BiasN

M5 M3

M1+

-

M4

M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

IMSE-CNM ICECS 2010, Athens (Greece)

A 1.2V 72dB 3-stage PGA in 90nm CMOS process

Proposed Low Power PGA Architecture

5

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

All the transistors havethe same width, lengthand number of fingers.

The only difference is the multiplicity.

How much currents in 90nm CMOS?

Stress due to trench isolation barriers!!!

2RS

BiasN

M5 M3

M1+

-

M4

M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

IMSE-CNM ICECS 2010, Athens (Greece)

A 1.2V 72dB 3-stage PGA in 90nm CMOS process

Proposed Low Power PGA Architecture

5

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

5 5 5

3 3 3

o m oS

S m S

R g F R FG F

R g F R F

1

1

o oR C

12

3 11

1

1

m ds dsg r r C

1z

Z ZR C

Poles

Zero

Gain

2RS

BiasN

M5 M3

M1+

-

M4

M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

IMSE-CNM ICECS 2010, Athens (Greece)

Design Methodology

Proposed Low Power PGA Architecture

6

Specifications

G BW Power

THD OS Noise

VDD Ib C0 ω2

2RS

BiasN

M5 M3

M1+

-

M4M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

Vin

IMSE-CNM ICECS 2010, Athens (Greece)

Design Methodology

Proposed Low Power PGA Architecture

6

cmo, cmi

Initialguess

Specifications

G BW Power

THD OS Noise

VDD Ib C0 ω2

2RS

BiasN

M5 M3

M1+

-

M4M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

Vin

IMSE-CNM ICECS 2010, Athens (Greece)

Design Methodology

Proposed Low Power PGA Architecture

6

cmo, cmi

Initialguess

cmo, R0 F5

BW, C0 R0

Specifications

Formulae

G BW Power

THD OS Noise

VDD Ib C0 ω2

2RS

BiasN

M5 M3

M1+

-

M4M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

Vin

IMSE-CNM ICECS 2010, Athens (Greece)

Design Methodology

Proposed Low Power PGA Architecture

6

cmo, cmi

Initialguess

cmo, R0 F5

BW, C0 R0 G, ω2 F3

Specifications

Fs=R0/RS

FN

Pick ValuesFormulae

BW, Noise ?

OP-ACSimulation

Formulae

G BW Power

THD OS Noise

VDD Ib C0 ω2

2RS

BiasN

M5 M3

M1+

-

M4M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

Vin

W1, W5, W4, WBP, WBN

NO

IMSE-CNM ICECS 2010, Athens (Greece)

Design Methodology

Proposed Low Power PGA Architecture

6

cmo, cmi

Initialguess

cmo, R0 F5

BW, C0 R0 G, ω2 F3

Specifications

Fs=R0/RS

FN

Pick ValuesFormulae

BW, Noise ?NO

PSSSimulation

OP-ACSimulation

Formulae

G BW Power

THD OS Noise

VDD Ib C0 ω2

YESTHD, Power ?

NO

END

YES

2RS

BiasN

M5 M3

M1+

-

M4M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

Vin

W1, W5, W4, WBP, WBN

IMSE-CNM ICECS 2010, Athens (Greece)

Key Aspects in the Design

Proposed Low Power PGA Architecture

7

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

IMSE-CNM ICECS 2010, Athens (Greece)

Key Aspects in the Design

Proposed Low Power PGA Architecture

7

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

1.- AC-coupling

2.- CMFF Circuit

IMSE-CNM ICECS 2010, Athens (Greece)

Key Aspects in the Design

Proposed Low Power PGA Architecture

7

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

AC-coupling1.- AC-coupling

2.- CMFF Circuit

IMSE-CNM ICECS 2010, Athens (Greece)

AC-coupling

Key Aspects in the Design

Proposed Low Power PGA Architecture

7

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

DC-coupledDC-coupled

S = 2 (Vinpmax - Voutp

min) ≈ 0.28Vpp

0.2

0.4

S = 2 (Vinp,outpmax - Vinp,outp

min) > 0.90Vpp

-0.2

AC-coupledAC-coupled0.2

0.4

-0.2

Traditional assumptions for PGAs, such as the convenience of DC-coupling [1], must be revised in a low-voltage high-dynamic range scenario

1.- AC-coupling

2.- CMFF Circuit

VDD/2

Voltage Range (V) Voltage Range (V)

IMSE-CNM ICECS 2010, Athens (Greece)

AC-coupling

Key Aspects in the Design

Proposed Low Power PGA Architecture

7

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

Traditional assumptions for PGAs, such as the convenience of DC-coupling [1], must be revised in a low-voltage high-dynamic range scenario

1.- AC-coupling

2.- CMFF Circuit

Advantages:Different cmi and cmoGreater dynamic rangeHigh linearity without resistive feedbackLow-power consumption

DC-coupledDC-coupled

S = 2 (Vinpmax - Voutp

min) ≈ 0.28Vpp

0.2

0.4

S = 2 (Vinp,outpmax - Vinp,outp

min) > 0.90Vpp

-0.2

AC-coupledAC-coupled0.2

0.4

-0.2

VDD/2

Voltage Range (V) Voltage Range (V)

IMSE-CNM ICECS 2010, Athens (Greece)

Key Aspects in the Design

Proposed Low Power PGA Architecture

8

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

1.- AC-coupling

2.- CMFF Circuit

2RS

BiasN

M5 M3

M1+

-

M4

M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

IMSE-CNM ICECS 2010, Athens (Greece)

CMFFC

VREFcmi

(Vbp,Vbn)

2cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

Key Aspects in the Design

Proposed Low Power PGA Architecture

8

Common-Mode Feed-forward Circuit (CMFF)

2RS

BiasN

M5 M3

M1+

-

M4

M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

IMSE-CNM ICECS 2010, Athens (Greece)

Key Aspects in the Design

Proposed Low Power PGA Architecture

8

Vbn

Vbp

Ib

VREF

cmi

-

+

IbRREF

Common-Mode Feed-forward Circuit (CMFF)

( common for all stage)

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

CMFFC

VREFcmi

(Vbp,Vbn)

2

5/ /b REF REF dd o REF REFI V R cmo V R R FV

2RS

BiasN

M5 M3

M1+

-

M4

M2

M6

VoutnVoutp

Ro Ro

BiasP

v1

C1

Co Co

(FN+F3)IbF5Ib

Vbn

Vbp

FNIb

Ib

Vbn

IMSE-CNM ICECS 2010, Athens (Greece)

Key Aspects in the Design

Proposed Low Power PGA Architecture

8

Common-Mode Feed-forward Circuit (CMFF)

( common for all stage)

Advantages:Common-mode feedback circuit can be suppressed since relatively low impedance is found at the output (Ro is usually in the order of k).

Low-cost low-power solution.

Accurately definition of the output common-mode (cmo).

Functionality guaranteed with Corners and Monte-Carlo simulations.

5/ /b REF REF dd o REF REFI V R cmo V R R FV

cmi

Vinp

VinnCZ

RZ

Voutp

Voutn

+

- -+ +

- -+ +

- -+

STG1 STG2 STG3Vinp,2

Vinn,2

CMFFC

VREFcmi

(Vbp,Vbn)

2

Vbn

Vbp

Ib

VREF

cmi

-

+

IbRREF

Motivations

State-of-the-Art in Low Voltage PGAs

Close-loop vs. Open-loop Architectures

Proposed PGA Architecture

Design Methodology

Common-Mode Feed-forward Circuit (CMFFC)

Verification:

Post-layout Simulation Results (3-stage PGA)

Experimental Results (stage core)

Conclusions

Contents

IMSE-CNM ICECS 2010, Athens (Greece)

Target Specifications

• Gain = 0 to 72dB in 6-dB steps

• Bandwidth > 15MHz

• ω 2 >> BW

• Power < 2.5mW

• Input referred noise (Gmax) < 15nVrms /Hz

• THD (Gmax) < -36dB

• Vdd = 1.2V 5%

Verification: 3-stage PGA

9

IMSE-CNM ICECS 2010, Athens (Greece)

103 104 105 106 109Frequency(Hz)

-60-40-20

0204060

Gain(dB)

107 108

G = 1G = 23

G = 43

G = 83

G = 163

Post-layout Simulation Results (90nm CMOS)

Verification: 3-stage PGA

9

Active Section

Decoupling Network

110µm

165µ

m

65µ

m

0.2 0.4 0.6 0.8 1 1.2 1.4Voutpp (V)

HD3 (dB)

-80

-70

-60

-50

-40

-30

G = 1

G = 2

G = 4G = 8

G = 16

STG Layout

3-stg PGA

Stage-core

IMSE-CNM ICECS 2010, Athens (Greece)

Corners and Monte-Carlo Specifications (Post-layout)

Verification: 3-stage PGA

10

TABLE I. PGA STATIC AND DYNAMIC SPECIFICATIONS AFTER LAYOUT PARASITIC EXTRACTION: TT (27ºC, 1.2V), SS(75ºC, 1.08V), FF(0ºC, 1.26V).

AC (Small Signal) @ Co = 2pF DC Large Signal @ 2.5MHz with maximum output range

Gain Corner G(dB) f3dB down

(kHz) f3dB up (MHz)

Input Noise (nVrms /Hz)

Power ( mW )

Aout

(Vpp) G(dB)

HD2 (dB)

HD3 (dB)

THD (dB)

G=1x1x1 tt 0.0 31.40 49.1 128.7 1.95 0.610 0.15 -44.67 -39.53 -39.23 G=16x16x16 tt 72.0 28.48 20.5 10.2 1.95 1.165 71.92 -83.32 -42.05 -42.03

G=1x1x1 ff -0.3 46.91 59.5 121.9 2.58 0.602 -0.31 -51.96 -47.94 -47.75 G=16x16x16 ff 73.0 43.05 25.2 9.4 2.58 1.171 72.31 -81.04 -43.78 -43.76

G=1x1x1 ss -0.5 21.58 39.4 131.8 1.53 0.604 0.55 -36.66 -32.77 -32.56 G=16x16x16 ss 71 19.48 16.7 11.4 1.53 1.134 70.20 -85.71 -36.82 -36.81

TABLE II. MONTE-CARLO RESULTS OF THE PGA STAGE FOR THE WORST CASE GAINS IN TERMS OF OUTPUT REFERRED OFFSET: #200, TT (27ºC, 1.2V).

G G(dB) f3dB down (Hz) f3dB up (Hz) Noise (Vrms /Hz) Output Offset (V) Power( W)

Gain mean std mean std mean std mean std mean std mean std mean std G=8 7.99 0.034 18.05 0.037 15.08K 6.74 26.28M 123K 13.92n 46.83p 22.70μ 12.90m 648.8μ 19.03μ G=16 15.98 0.055 24.07 0.030 14.66K 11.69 24.33M 128K 10.11n 22.13p 264.5μ 18.15m 648.8μ 19.03μ

IMSE-CNM ICECS 2010, Athens (Greece)

Corners and Monte-Carlo Specifications (Post-layout)

Verification: 3-stage PGA

TABLE I. PGA STATIC AND DYNAMIC SPECIFICATIONS AFTER LAYOUT PARASITIC EXTRACTION: TT (27ºC, 1.2V), SS(75ºC, 1.08V), FF(0ºC, 1.26V).

AC (Small Signal) @ Co = 2pF DC Large Signal @ 2.5MHz with maximum output range

Gain Corner G(dB) f3dB down

(kHz) f3dB up (MHz)

Input Noise (nVrms /Hz)

Power ( mW )

Aout

(Vpp) G(dB)

HD2 (dB)

HD3 (dB)

THD (dB)

G=1x1x1 tt 0.0 31.40 49.1 128.7 1.95 0.610 0.15 -44.67 -39.53 -39.23 G=16x16x16 tt 72.0 28.48 20.5 10.2 1.95 1.165 71.92 -83.32 -42.05 -42.03

G=1x1x1 ff -0.3 46.91 59.5 121.9 2.58 0.602 -0.31 -51.96 -47.94 -47.75 G=16x16x16 ff 73.0 43.05 25.2 9.4 2.58 1.171 72.31 -81.04 -43.78 -43.76

G=1x1x1 ss -0.5 21.58 39.4 131.8 1.53 0.604 0.55 -36.66 -32.77 -32.56 G=16x16x16 ss 71 19.48 16.7 11.4 1.53 1.134 70.20 -85.71 -36.82 -36.81

TABLE II. MONTE-CARLO RESULTS OF THE PGA STAGE FOR THE WORST CASE GAINS IN TERMS OF OUTPUT REFERRED OFFSET: #200, TT (27ºC, 1.2V).

G G(dB) f3dB down (Hz) f3dB up (Hz) Noise (Vrms /Hz) Output Offset (V) Power( W)

Gain mean std mean std mean std mean std mean std mean std mean std G=8 7.99 0.034 18.05 0.037 15.08K 6.74 26.28M 123K 13.92n 46.83p 22.70μ 12.90m 648.8μ 19.03μ G=16 15.98 0.055 24.07 0.030 14.66K 11.69 24.33M 128K 10.11n 22.13p 264.5μ 18.15m 648.8μ 19.03μ

f3dB @ 2pF

(MHz)

Input Noise

(nVrms /Hz)Power( mW )

Aout

(Vpp)

THD(dB)

20.5 10.2 1.95 1.165 -42.03

10

IMSE-CNM ICECS 2010, Athens (Greece)

Corners and Monte-Carlo Specifications (Post-layout)

Verification: 3-stage PGA

10

TABLE I. PGA STATIC AND DYNAMIC SPECIFICATIONS AFTER LAYOUT PARASITIC EXTRACTION: TT (27ºC, 1.2V), SS(75ºC, 1.08V), FF(0ºC, 1.26V).

AC (Small Signal) @ Co = 2pF DC Large Signal @ 2.5MHz with maximum output range

Gain Corner G(dB) f3dB down

(kHz) f3dB up (MHz)

Input Noise (nVrms /Hz)

Power ( mW )

Aout

(Vpp) G(dB)

HD2 (dB)

HD3 (dB)

THD (dB)

G=1x1x1 tt 0.0 31.40 49.1 128.7 1.95 0.610 0.15 -44.67 -39.53 -39.23 G=16x16x16 tt 72.0 28.48 20.5 10.2 1.95 1.165 71.92 -83.32 -42.05 -42.03

G=1x1x1 ff -0.3 46.91 59.5 121.9 2.58 0.602 -0.31 -51.96 -47.94 -47.75 G=16x16x16 ff 73.0 43.05 25.2 9.4 2.58 1.171 72.31 -81.04 -43.78 -43.76

G=1x1x1 ss -0.5 21.58 39.4 131.8 1.53 0.604 0.55 -36.66 -32.77 -32.56 G=16x16x16 ss 71 19.48 16.7 11.4 1.53 1.134 70.20 -85.71 -36.82 -36.81

TABLE II. MONTE-CARLO RESULTS OF THE PGA STAGE FOR THE WORST CASE GAINS IN TERMS OF OUTPUT REFERRED OFFSET: #200, TT (27ºC, 1.2V).

G G(dB) f3dB down (Hz) f3dB up (Hz) Noise (Vrms /Hz) Output Offset (V) Power( W)

Gain mean std mean std mean std mean std mean std mean std mean std G=8 7.99 0.034 18.05 0.037 15.08K 6.74 26.28M 123K 13.92n 46.83p 22.70μ 12.90m 648.8μ 19.03μ G=16 15.98 0.055 24.07 0.030 14.66K 11.69 24.33M 128K 10.11n 22.13p 264.5μ 18.15m 648.8μ 19.03μ

IMSE-CNM ICECS 2010, Athens (Greece)

Experimental Results (single stage)

Verification (not included in the paper)

11

PCB Test Setup +HP3589A Analyzer

Single-to-Differential Input Buffers& Diff.-to-Single Output Buffers

This work has been partially supported by the Spanish projects TEC2007-68072 and P09-TIC-5386, and by the Catrene European project SR2 2A105 (all co-founded by FEDER).

103

104

105

106

107

-20

-15

-10

-5

0

5

10

15

20

25Magnitude Bode (dB)

Frequency (MHz)

Simulated: - -Measured: ―

Gain ↑

IMSE-CNM ICECS 2010, Athens (Greece)

Experimental Results (single stage)

Verification (not included in the paper)

11

PCB Test Setup +HP3589A Analyzer

Single-to-Differential Input Buffers& Diff.-to-Single Output Buffers

This work has been partially supported by the Spanish projects TEC2007-68072 and P09-TIC-5386, and by the Catrene European project SR2 2A105 (all co-founded by FEDER).

0 2 4 6 8 10

x 106

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Frequency (MHz)

Output Spectrum (dBm @ 50 Ohms)

THD = -45.0dB

fin

= 1MHz; Aout

= 1.05Vpp

; G = 4

Motivations

State-of-the-Art in Low Voltage PGAs

Close-loop vs. Open-loop Architectures

Proposed PGA Architecture

Design Methodology

Common-Mode Feed-forward Circuit (CMFFC)

Verification:

Post-layout Simulation Results (3-stage PGA)

Experimental Results (stage core)

Conclusions

Contents

IMSE-CNM ICECS 2010, Athens (Greece)

In this paper, we have shown that open-loop topologies with gain boosting present an optimum trade-off between power consumption and linearity for ZigBee applications.

We have proposed a design methodology for low-voltage PGAs with resistive degeneration.

The developed design flow is shown with a 1.2V 72dB 1.95mW PGA implementation in a TSMC 90nm CMOS process.

Power optimization is improved thanks to the use of a front-end capacitive decoupling network and a common-mode feed-forward circuit shared between all stages.

The front-end capacitive decoupling network also improves the PGA dynamic range. Actually, a THD < -42dB is achieved for a 1.2Vpp output excursion, G = {4,8,16}.

Conclusions

12

POWER OPTIMIZATION OF CMOS PROGRAMMABLE GAIN AMPLIFIERS WITH HIGH DYNAMIC RANGE AND COMMON-MODE FEED-FORWARD CIRCUIT

A. J. Ginés, Email: gines@imse-cnm.csic.es

Instituto de Microelectrónica de Sevilla (CNM-CSIC)University of Seville (Spain)

Thank you very much for your attendanceQuestions?