236 IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 5, MAY 2000

A Novel Flash EEPROM Cell Based on TrenchTechnology for Integration Within Power

Integrated CircuitsD. M. Garner, Member, IEEE, Y. Chen, Member, IEEE, L. Sabesan, G. A. J. Amaratunga, Member, IEEE,

A. Blackburn, J. Clark, S. S. Sekiariapuram, and A. G. R. Evans, Member, IEEE

Abstract—A flash EEPROM suitable for integration withinpower integrated circuits (PIC’s) is presented. The EEPROM celluses a trench floating gate to give a large gate charge while usingno more silicon area than a conventional flash EEPROM cell.The cell shows good immunity against the induced disturbancevoltages which are present in a PIC, and the storage lifetime isgreater than ten years at a reading voltage of = 2 2 V circuits.

Index Terms—CMOS memory integrated circuits, EPROM,power integrated circuits.

I. INTRODUCTION

T HE INTEREST in power integrated circuits, whereCMOS circuitry and power switching devices are inte-

grated side-by-side on the same silicon substrate, has recentlygrown rapidly due to improved integration techniques [1]–[3].The applications of such circuits range from plasma displaypanel driver IC’s which switch voltages of 200 V [4] to 600 Vsingle-chip power converters [1]. Within this context, a familyof generic power integrated circuits which can be programmedfor use in a variety of applications is an attractive proposition.

A novel submicron flash EEPROM cell suitable for integra-tion within power integrated circuits is presented in this letter.The stored charge on the floating gate of the EEPROM needs tobe as large as possible in order to give good immunity againstinduced disturbances associated with the switching of adjacenthigh-voltage devices on the same silicon substrate. A largestored charge can be achieved by employing a large storagecapacitance beneath the floating gate, but in the conventionalplanar flash EEPROM memory cell structure this uses a largesilicon area.

To address this problem, we propose a flash EEPROM cellthat uses a trench gate capacitor as the floating gate, shown inthe inset of Fig. 1, which gives an increased floating gate chargewhile using a silicon area no greater than that used by an ordi-

Manuscript received October 13, 1999; revised November 30, 1999. Thiswork was supported by the United Kingdom’s Engineering and Physical Sci-ences Research Council under Grant GR/K35471. The review of this letter wasarranged by Editor C. Wann.

D. M. Garner, L. Sabesan, G. A. J. Amaratunga, and S. S. Sekiariapuram arewith the Department of Engineering, University of Cambridge, Cambridge CB21PZ, U.K.

Y. Chen is with Cypress Semiconductor, San Jose, CA USA.A. Blackburn, J. Clark, and A. G. R. Evans are with the Department of Elec-

tronics and Computer Science, University of Southampton, Southampton, U.K.Publisher Item Identifier S 0741-3106(00)02110-8.

Fig. 1. A cross-sectional SEM picture of a completed cell with a trench widthof 800 nm. The structure of the trench EEPROM cell is shown diagramaticallyin the inset.

nary EEPROM cell. The source and drain are on either side ofthe trench, and the conduction channel lines the silicon/oxideinterface along the trench wall. Because the control gate alsolies within the trench, the voltage coupling ratio (floating gatevoltage over control gate voltage) would be only slightly re-duced compared to a normal planar EEPROM cell. However,in order to counteract this and to ensure that the voltage cou-pling ratio, and hence stored charge, is as large as possible, weused silicon nitride as the interpoly dielectric which has a higherdielectric constant than conventional oxynitride. Therefore, noincrease in gate voltage over a conventional planar EEPROM isrequired for programming and erasing.

II. DEVICE FABRICATION

The devices were fabricated on 17–33cm p-type siliconsubstrates. Isolation trenches of width ranging from 500 to800 nm were first etched to a depth of 1.5-m and wereoxidized and refilled with polysilicon. An arsenic implant ofdose cm and energy 80 keV formed the nsourceand drain. Then 1.5 m deep trenches of width ranging from500 to 800 nm were etched through the nimplanted regionsusing an HBr

0741–3106/00$10.00 © 2000 IEEE

GARNERet al.: NOVEL FLASH EEPROM CELL BASED ON TRENCH TECHNOLOGY 237

Fig. 2. Gate transfer characteristics before and after programming. Terminalvoltages other than those shown were held at 0 V.

process chemistry, thus separating the source and drain and en-suring the source and drain were self-aligned to the edges ofthe trench. A 15-nm thick oxide was then grown thermally andimmediately removed with buffered HF in order to smooth thesidewalls of the trench, and to remove any damage at the sur-face created by the reactive ion etch. A tunneling gate oxideof thickness 10 nm was then grown, and 300 nm of polysil-icon was deposited to form the floating gate. A 20-nm layerof LPCVD silicon nitride formed the interpoly dielectric, afterwhich another 200 nm of polysilicon was deposited to form thecontrol gate electrode. The polysilicon/nitride/polysilicon stackwas then etched to leave only a small overhang around the trenchedges. The processing was completed with BPSG planarization,contact window etching and metal deposition and patterning.The processing required to form the trench is compatible withthat required for the fabrication of trench-based power devices[5], thereby minimizing process complexity and cost.

III. RESULTS AND DISCUSSION

A cross-sectional SEM picture of the completed structure foran 800-nm trench width is shown in Fig. 1. One can see how thecontrol gate electrode as well as the floating gate electrode lieswithin the trench, and so the area between the control gate andthe floating gate is comparable to the area between the floatinggate and the substrate.

The devices are programmed with a gate voltage of 8 V and adrain voltage of 6 V, which causes the injection of hot electronsinto the floating gate near the drain side of the trench. Erasing isachieved by applying a negative bias of15 V to the gate whilegrounding the drain and source which causes the Fowler–Nord-heim tunneling of electrons from the floating gate. The gatetransfer characteristics in the erased state and programmed stateare shown in Fig. 2. A threshold voltage shift of about 2.5 V isobtained and the threshold voltages obtained are relatively highat about 4 V in the erased state and 6.5 V in the programmedstate. High threshold voltages are required in power integratedcircuits to avoid the possibility of accidental device operationthrough induced voltages from the switching of high-voltage

Fig. 3. Threshold voltage as a function of programming and erasing time. Theprogramming condition wasV = 6 V, V = 8 V and the erasing condition isV = �15 V; all other potentials were held at 0 V.

Fig. 4. Drain and gate program disturb characteristics. Drain disturbance wasunder the conditionV = 0 V, V = 8 V, and gate disturbance was under thecondition ofV = 6 V, V = 0 V.

devices which are integrated on the same silicon substrate. Thepunch-through voltage is 8.8 V at 10 nA drain current. The readcurrent is relatively low at 10 A (although this is comparableto a recently published novel EEPROM technology [6]). This adrawback of using a large floating gate area, achieved using thetrench structure, which gives an increased channel length, hencereducing the device current. However, by scaling up the channelwidth accordingly a larger read current could be obtained. Note,however, that the read current is not a major concern in this ap-plication: it is the achievement of a large stored charge that isimportant for immunity of the stored data against noisy environ-ments resulting from operation of the EEPROM cell in a powerintegrated circuit.

Fig. 3 shows that programming can be achieved within 1 msand that the erase time is 1 s. Although these are relativelylong programming and erasing times compared with some re-cent high-density flash EEPROM technologies [7], [8], the largeamount of charge that needs to be stored on the large floatinggate accounts for this, and is what gives this structure resilience

238 IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 5, MAY 2000

Fig. 5. Read disturb characteristics, showing a greater than ten year lifetimeat V = 2 V.

against induced disturbances that are likely to arise when it isintegrated within a power integrated circuit.

Drain and gate program disturb characteristics are shown inFig. 4. No significant change in threshold voltage was foundin 1000 s of drain disturbance, suggesting excellent resilienceof this EEPROM cell against drain disturbance. The gate dis-turb characteristic shows good immunity. The drain disturbancecharacteristics of our device are superior to many recently pub-lished EEPROM technologies [9]–[12]. While the gate disturbcharacteristic does not show such a good improvement overother published technologies, it should be noted that this charac-teristic is remarkably good considering that the floating gate isa trench gate, and one would expect the enhanced electric fieldat the trench corner to reduce the resilience of the device to gatedisturbance somewhat. We believe that the careful developmentof the trench etch process and the use of a sidewall smoothingoxide to give the rounded trench corners seen in Fig. 1 are re-sponsible for enhancing the gate disturbance.

Fig. 5 shows that the lifetime due to soft writing duringreading of the device is greater than ten years at a readingvoltage of V. The gate voltage for reading was5 V. These high reading voltages give the EEPROM excellentimmunity to induced disturbances arising from the switchingof adjacent high-voltage devices.

IV. CONCLUSION

A flash EEPROM cell structure compatible with power inte-grated circuit operation has been presented. The EEPROM em-

ploys a trench gate technology to elicit a large floating gate ca-pacitance while using no more silicon area than a conventionalflash EEPROM technology. The device was programmed anderased in the same way as a conventional flash EEPROM togive a threshold voltage shift of 2.5 V. The EEPROM showedexcellent immunity to drain disturbance and good immunity togate disturbance, and a reading lifetime of ten yrs. was obtainedat a drain reading voltage of 2.2 V, and a gate voltage of 5 V.The immunity of the device to disturbances, and the relativelyhigh reading voltages, make the device suitable for integrationalongside high-voltage switching devices in a power integratedcircuit.

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