A Radiation-Hard Non-linear DAC for DDFS

Zhihe Zhou and George S. La Rue

School of Electrical Engineering and Computer Science

Washington State University

Pullman, Washington, U.S.A.

Abstract— A radiation-hardened 12-bit non-linear DAC was

designed and fabricated on Honeywell’s 0.35 µµµµm MOI5 SOI

CMOS process. The non-linear DAC allows a significant

reduction in complexity and power dissipation when used within

direct digital frequency synthesizers (DDFSs). The non-linear

DAC implements a 32-segement piecewise linear approximation

to sine function reducing the ROM look-up table size from 11K

bits to 544 bits. Test results show that an SFDR of 72 dBc is

achieved at low output frequency and 54 dBc at high frequency.

Radiation test shows that the non-linear DAC can sustain a total

ionizing dose up to 200 Krad Si.

Keywords- DDFS; non-linear DAC; piecewise-linear

approximation; radiation hardness

1. INTRODUCTION

Direct digital frequency synthesizer (DDFSs) can produce sinusoidal waveforms over a wide range of frequencies. Fast frequency hopping, high spectral purity and low power dissipation are the desired performance measures, which are required for many modern wireless communication systems. In addition, DDFS also can have higher frequency resolution and lower phase noise than phase-lock look (PLL) based frequency synthesizers [1].

In DDFSs, a fixed input frequency is directly converted to other output frequencies using a phase accumulator, ROM look-up table and a digital-to-analog converter (DAC). The phase accumulator generates the digital phase, which is input into a sinusoidal look-up table to generate digital amplitudes of a sine function. The DAC converts the digital sine wave to analog which is then filtered to provide the synthesized frequency.

The standard approach of implementing a DDFS using a 12-bit binary-weighted DAC requires a ROM look-up table of 11K bits. The ROM only needs to store the first quarter of a cycle due to symmetry of the sine function. Reducing ROM size is especially important for obtaining low power dissipation in high-speed DDFSs. A number of approaches have been developed to reduce ROM size, including using non-linear DACs, sine-phase difference, and double-trigonometric approximations [2-3].

This paper presents an implementation of a non-linear DAC that allows the ROM look-up table to be reduced to 544 bits. The reduction in ROM size requires no digital adders or multipliers, which increase complexity and power dissipation, as in some previous approaches. It also requires relatively few switches increasing its potential for high-speed operation. The

non-linear DAC architecture in [3] requires 2N switches, where

N is the resolution in bits, and limits high speed operation at higher resolution.

2. NON-LINEAR DAC

The non-linear DAC implements a 32-segment piecewise linear approximation (PLA) to a sine function. The piecewise linear approximation can be described as

)1( )()sin( Nixxbax iii K=−+= (1)

where x is the phase of the sine wave, N is the number of segments and ai and bi are the offset and gain of the ith segment. Figure 1 illustrates the concept with a 4-segment approximation of a 12-bit DAC.

Figure 1. 4-segment piecewise linear approximation

A block diagram of the DAC and its associated control logic are shown in Figure 2. Advantage is taken of the symmetry properties of the sine function to reduce ROM size using the sign of the phase and the conditional complementor, as is common in many DDFSs. The ROM look-up table stores the segment offsets and gains.

Figure 2. Non-linear DAC with control logic

This material is based on research sponsored by the Air Force Research Laboratory under agreement number F29601-02-2-0299 in conjunction with

the NSF Center for the Design of Analog-Digital Integrated Circuits

(CDADIC).

ROM 11

5

32x 17

10

6

Gain

Offset

5 LSBs

Offset

DAC MSB

Filter Output 12 bit resolution

Conditio

nal

Complementor

10

MSB - 1

From Phase

Accumulator -

Non-linear DAC

Phase

Amplitude

12th NASA Symposium on VLSI Design, Coeur d’Alene, Idaho, USA, Oct. 4-5, 2005

The non-linear DAC consists of two DACs; an offset DAC and a vernier DAC. Each DAC implements one term in (1). Since the DACs are designed using current steering architecture, the addition of the terms is performed by summing the current at the output node. The multiplication is performed by summing currents from partial products instead of using a digital multiplier.

2.1 OFFSET DAC

The offset DAC is implemented as a 12-bit hybrid current-steering DAC. The top 5 MSBs are implemented using unary current sources and the 7 LSBs consists of 7 binary-weighted current sources. This hybrid architecture reduces the amplitude of glitches at the output [4].

To compensate for the current source matching error during the fabrication process, digital calibration and trimming is used. All unary current sources and the largest of the binary-weighted current sources are digitally trimmed. Figure 3 shows a unary current source with digital trimming circuit. Each unary current source is implemented with a current source that is 4 LSB lower than the ideal value of 128 LSBs. A current mirror adds in an extra current of up to 8 LSBs with a resolution of 0.125 LSBs from 6 binary-weighted trimming current sources. The 6-bit control word (TB1~TB6) is stored in RAM.

Figure 3. A current source with trimming circuit

The largest binary current source must be first calibrated to the sum of all lower LSBs plus 1 LSB (64 LSBs). Then an additional trimmable reference current source, identical to the unary current sources, is trimmed to a value that equals the sum of all binary current sources plus 1 LSB (128 LSBs). The reference current source is then used to calibrate the 32 unary current sources.

2.2 VERNIER DAC

The vernier DAC is also a current steering DAC but with variable gain. It consists 6 sets of binary-weighted current sources with values shown in Table 1. The multiplication in the linear term DAC is performed by summing partial products instead of using a digital multiplier. The partial products can be obtained using AND gates. Xi (i=1 to 5) in Table 1 denotes the ith bit of the phase offset within a segment and Gk (k=1 to 6) the kth bit of the gain for a segment. Xs is the sign bit. These bits control 26 current sources with relative sizes given in the table.

Current is switched to the output when both row and column control bits are high. Otherwise the current is switched to the complementary output. The total current switched to an output node is the product of the segment gain and the phase offset. The minimum current is 1 LSB and all bits less than 1 LSB in the product are rounded off. The non-linear DAC approach requires only 26 current switches in addition to the 39 current switches in the offset DAC. Having few switches enables the DAC to operate at high speed.

TABLE I. MULTIPLICATION BY SUMMING PARTIAL PRODUCTS (VALUES ARE IN LSBS)

Xs X5 X4 X3 X2 X1

G6 32 16 8 4 2 1

G5 16 8 4 2 1 1

G4 8 4 2 1 1

G3 4 2 1 1

G2 2 1 1

G1 1 1

2.3 ROM TABLE AND CONTROL LOGIC

The ROM lookup table stores the digital sine wave. For a 12-bit DAC, the standard approach of implementing a DDFS requires 11K bits of ROM. When using the non-linear DAC, the ROM only stores the offset and gain of each segment instead of each point of the sine function. The size of ROM can be significantly reduced, depending on the number of segments and the number of bits assigned to the segment gain.

Choosing an optimum number of segments N requires a compromise between look-up table size and output SFDR [5]. A smaller N results in fewer segments and a smaller look-up table but has a larger approximation error leading to lower SFDR. More segments results in higher SFDR at the cost of a larger look-up table. After investigation, an N of 32 was found to provide sufficient implementation margin to achieve 60 dB SFDR with a 12-bit DAC resolution. The look-up table is 544 bits with 11 bits for offset and 6 bits for gain in each segment.

3. MEASURMENT RESULTS

The chip was packaged in a 128 pin leaded quad flat pack.

Figure 4 shows a photograph of the die. The non-linear DAC

was characterized for DC and AC performance along with total

ionizing dose radiation testing.

3.1 DC CHARACTERIZATION

The differential non-linearity (DNL) and integral non-

linearity (INL) of the offset DAC were measured after

performing digital calibration. Figure 5 shows the measured

DNL and INL with both being less than 0.5 LSB, showing that

12-bit accuracy was obtained for the offset DAC. Before

calibration, the DNL and INL were about ±2 LSBs. The digital

trimming approach is effective in compensating for process

induced matching errors.

12th NASA Symposium on VLSI Design, Coeur d’Alene, Idaho, USA, Oct. 4-5, 2005

Figure 4. Die photograph of the non-linear DAC

Figure 5. The Measured DAC INL/DNL

Operation of the vernier DAC was tested by providing external gain bits and segment offset bits. Figure 6 shows 16 of the 64 possible gains. The figure was obtained by sweeping the segment offset from -31 to +31 for each of the 16 gains.

Figure 6. Variable gains

The non-linear DAC can generate a piecewise linear function and is not limited to just generating a sine wave. As an illustration, the combined output of the offset DAC and vernier DAC is shown in figure 7 with various offsets and gains to form a continuous waveform. Each segment consists of 32 points. The offset and gain words for each segment are shown in the table below the graph.

Offset 2048 2172 2234 2234 2234 2134 2103 2041 2041

Gain 63 31 4 -4 12 -63 -15 -31 3

Figure 7. Output wave with different offsets and gains

3.2 HIGH SPEED MEASUREMENTS

Testing showed the non-linear DAC can be clocked up to 600 MHz. The SFDR ranges from 54 dBc to 72 dBc for different frequency outputs and clock rates. Figure 8 shows the output sine wave at 630 KHz with the non-linear DAC operating at 10 Mbps clock rate. Figure 9 shows the spectra of this signal, which has a dominant third harmonic. The SFDR is 72 dBc. Figure 10 shows the spectra for a 37.5 MHz output at 600 Mbps. The fundamental signal is at +2.5 dBm and the second harmonic is -51.5 dBm, giving an SFDR of 54 dBc.

Figure 8. Sine wave output at 630 KHz

PHASE OFFSET

OUTPUT (V)

INPUT

DNL (LSB)

INL (LSB)

PHASE

OUTPUT (V)

TIME (0.5 uS/grid)

OUTPUT (0.5 Vpp)

12th NASA Symposium on VLSI Design, Coeur d’Alene, Idaho, USA, Oct. 4-5, 2005

Figure 9. Spectrum of 630 KHz output at 10 MSps

Figure 10. Spectrum of 37.5 MHz output at 600 MSps

3.3 RADIATION TESTING

Total ionizing dose radiation testing was performed at Boeing Radiation Effects Laboratory. Figure 11 shows the INL and DNL measurements on the lower 6 bits of the DAC before and after a dose of 200 Krad Si. The unary current sources showed no significant changes up to 200Krad Si but both the unary and binary current sources showed significant leakage after a dose of 250 Krad Si.

4. CONCLUSION AND FUTURE WORK

A 12-bit non-linear DAC was designed, fabricated and tested. Results show the DAC has true 12 bit accuracy and can substantially reduce the required ROM look up table size and hence the power dissipation when used in DDFS applications. The non-linear DAC can be used to implement a piecewise linear approximation to a sine function. The DAC operates up to 600 Mbps and has high SFDR. The non-linear DAC was

fabricated on Honeywell’s 0.35 µm MOI5 SOI process and can withstand radiation up to a total ionizing dose of 200 Krad Si.

A piecewise quadratic approximation (PQA) is being investigated to reduce the ROM size further for DDFSs with higher resolution DACs, which are capable of obtaining higher SFDR. For the same approximation error, the number of segments can be reduced using the piecewise quadratic approximation compared to the piecewise linear approximation. Due to the additional complexity required to

implement the PQA, only for DAC resolutions higher than 12 bits will the PQA be capable of reducing overall complexity compared to the piecewise linear approximation. Simulation results show that an SFDR above 80 dBc is achievable with a 14-bit non-linear DAC using a 16-segment quadratic approximation.

Figure 11. INL and DNL measurements before (top) and after (bottom)

radiation showing hardness of current sources up to 200 Krad Si.

REFERENCES

[1] J. Tierney, C.M. Rader, and B. Gold, “A digital frequency synthesizer,” IEEE Trans. on Audio and Electroacoustics, vol. 19, no. 1, pp. 48-57, January 1971.

[2] J.M.P. Langlois, and D. Al-Khalili, “ROM size reduction with low processing cost for direct digital frequency synthesis,” Proc. PACRIM’01, Victoria, Canada, Aug. 2001, vol. 1, pp. 287–290.

[3] Mortezapour, S., and Lee, E.K.F., “Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter,” IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1350-1359, Oct. 1999.

[4] A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, “A 10-bit 1 GSample/s Nyquist Current-Steering CMOS D/A Converter”, IEEE J. Solid-State Circuits, 36(3), pp. 315–324, 2001.

[5] Z. Zhou, I. Horowitz, G. S. La Rue, “Non-linear DAC implementations in DDFS,” IEEE Workshop on Microelectronics and Electron Devices, pp 124-125, 2004.

12th NASA Symposium on VLSI Design, Coeur d’Alene, Idaho, USA, Oct. 4-5, 2005