A Reconfigurable FPGA Architecture for DSP Transforms

Subramanian Rama Vishnu Vijayaraghavan

OUTLINE Motivation Reconfigurable FPGA’s DSP Transforms, Breakdown &

Applications Communication Graphs& Proposed

Architecture Imaginary Radix Complex Multiplication Accomplished Work Conclusion

Motivation Dedicated VLSI Architectures for

Orthogonal Transforms – FFT, DCT, Convolution, Correlation

Dedicated VLSI Architectures for Non- Orthogonal Transforms – Gabor, Wavelet

Not many Architectures for Both – Current Day Applications like Handhelds, Mobile Phones, etc. require such DSP capabilities

Need for Reconfigurable Architecture Multiple Orthogonal & Non-Orthogonal

Transforms can be broken down to a basic set of Building blocks (DCT,DST, multipliers and Adders)

Handheld devices don’t require much Multiprocessing – No need to waste hardware

Increased Fault-Tolerance By Reconfiguration and Redundancy

AREA & POWER INCREASING PROMINENCE OF

PORTABLE SYSTEMS Cell Phones Personal Digital Assistants Tablet PC’s

Need for Low Power & Area Battery Technology not kept pace

with Semiconductor Technology

BATTERY(40+ lbs)

DISCRETE FOURIER TRANSFORM

APPLICATIONS:Image Processing Orthogonal Frequency Division Multiplexing

Traditional DFT

Breakdown of 2D DFT

Breakdown of 1D DFT

Discrete Gabor TransformGabor Transform and Coefficients

Breakdown

Applications Speech Processing / Voice Recognition Image Compression

Discrete Convolution

Applications Image Manipulation Sound Processing

2-D Fourier Transform

Convolution Operation

Convolution Operation (Contd.)

Computational complexity:2 DCT, 2 DST,4 real multiplications and 2 real additions

Imaginary Radix Representation A imaginary number system, Donald Knuth,

Communications of the ACM Concept:

a + ib = A – Interleave both real and Imaginary parts # of multiplications get reduced to one Preserve Interleaving even during

multiplication Requires slight modifications in multiplier

design (one reason for migrating to FPGA)

Convolution Operation (using Complex Representation)

Computational complexity:2 DCT, 2 DST,1 complex multiplication (same as real multiplication methodology)

Convolution using Complex Representation - Communication Graph

Gabor Transform Communication Graph

Reconfiguration

Work so far Design & Synthesis of Basic Building Blocks

DCT DST Parallel Array Multiplier Reconfiguration Unit Partial Integration

Work to be done: Complete Integration Functional Correctness Check

CONCLUSIONNeed for multiple transforms on same chip Mobile devices, Handhelds Not much multiprocessing requiredUse of Reconfigurable FPGA’s Reduces

AREA Increases

Functionality Fault Tolerance