Achieving Energy Efficiency by HW/SW Co-design

Shekhar Borkar, IntelAbstract: Compute performance increased by orders of magnitude in the last fewdecades, made possible by continued technology scaling, increasing frequency, pro-viding integration capacity to realize novel architectures, and reducing energy tokeep power dissipation within limit. The technology treadmill will continue, andone would expect to reach Exascale level performance this decade; however, it’s thesame Physics that helped you in the past will now pose some barriers—Business asusual will not be an option. The energy and power will pose as a major challenge.Memory and communication bandwidth with conventional technology would be pro-hibitive. Orders of magnitude increased parallelism, let alone extreme parallelism

Shekhar BorkarIntel

due to energy saving techniques, would increase un-reliability. And programming system will be posedwith even severe challenge of harnessing the performancewith concurrency. We will discuss potential solutionsin all disciplines, such as circuit design, system archi-tecture, system software, programming system, and re-siliency—in the true spirit of hardware-software- tech-nology co-design—where all levels in the system stackare harmonized to deliver the most energy efficient sys-tem.

Bio: Shekhar Borkar received M.Sc in Physics fromUniversity of Bombay in 1979, MSEE from University ofNotre Dame in 1981 and joined Intel Corp, where he workedon the 8051 family of microcontrollers, and Intel’s super-computers. Shekhar is an Intel Fellow, an IEEE Fellow,and Director of Extreme-scale Technologies.

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From Embedded Systems to Systems of Systems

Herman Kopetz, Vienna University of TechnologyAbstract: Most of today’s machines, e.g., automotive engines, production machineryor even consumer devices, such as a washing machine, are controlled by an embed-ded computer system. It is assumed that the widespread integration of these existingembedded computer systems and data bases into systems-of-systems will provide newsynergistic services, make better use of the available information, lead to new insights,improve current economic processes and thus create greater wealth. Fueled by thedramatic technological progress in the area of wire-bound and wire-less communica-tion, this integration is already happening on a wide scale in industry. From theviewpoint of computer science, the domain of Systems-of-Systems (SoS) is a relativelynew field that poses significant new research challenges. The table below characterizesa system of system by listing some distinguishing properties of a SoS compared tothose of a monolithic system. If we look at this table we see that the listed char-acteristics of a SoS violate many of the fundamental assumptions that are taken forgranted in the established monolithic system design process. For example, there isno central development authority, fixed specification, coordinated evolution, or finalacceptance test of a SoS. In our view, the most differentiating characteristics of aSoS compared to a monolithic system are the autonomy of the constituent systems(CS) and their means to represent information, emergent phenomena at the SoS leveland uncoordinated evolution of the CSs. From the perspective of a SoS the CSs thatform an SoS are independent, tightly integrated in their local environments and mustbe continually adapted to remain relevant to their ever-changing local environments.On October 1, 2013 the new European FP7 research project AMADEOS (Architec-ture for Multi-criticality Agile Dependable Evolutionary Open System-of- Systems)has started with the following objectives: It is the objective of this research proposalto bring time awareness and evolution into the design of System-of-Systems (SoS),to establish a sound conceptual model, a generic architectural framework and a de-sign methodology, supported by some prototype tools, for the modeling, developmentand evolution of time-sensitive SoSs with possible emergent behaviors. The proposedopen and agile architecture will focus on mixed-criticality Cyber- Physical Systems(CPS) with guaranteed responsiveness. This presentation will focus on the researchissues that are posed by the integration of embedded systems into systems of sys-tems and will present the research approach taken in the AMADEOS project. Theproject is supported by the European Commission under grant agreement 610535.

Herman KopetzVienna University ofTechnology

Bio: Hermann Kopetz is professor emeritus at the Tech-nical University of Vienna. He is the chief architect of thetime-triggered technology for dependable embedded Sys-tems and a co-founder of the company TTTech. The time-triggered technology is deployed in leading aerospace, auto-motive and industrial applications. Kopetz is a Life Fellowof the IEEE and a full member of the Austrian Academy ofScience. Kopetz served as the chairman of the IEEE Com-puter Society Technical Committee on Dependable Com-puting and Fault Tolerance and in program committees ofmany scientific conferences. He is a founding member anda former chairman of IFIPWG 10.4 and has been a memberof the ISTAG advisory group at the European Commissionin Brussels from 2008-2012. Kopetz has written a widelyused textbook on Real-Time Systems and published morethan 200 papers. In June 2007 he received the honorary de-gree of Dr. honoris causa from the University Paul Sabatier

in Toulouse, France.

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Future of Nano CMOS Technology

Hiroshi Iwai, Tokyo Institute of TechnologyAbstract: Although silicon-based CMOS devices have dominated the integrated cir-cuit applications over the past few decades, it is expected that the development ofCMOS would reach its limits after the next decade because of the difficulties in down-sizing and some fundamental limits of MOSFETs. However, there are no promisingcandidates which can replace CMOS with better performance with high-density inte-gration for the moment. Thus, we have to stick to the CMOS devices until its end.In order to pursue the downsizing of CMOS for another decade, the development ofnew technologies is becoming extremely important. Not all the companies can neces-sarily develop the most advanced technology timely and the competition between theleading semiconductor manufacturing companies becomes very severe for their sur-vive. The current status of the frontend of the technology is as follows: New devicestructures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventionalplanar MOSFETs. Continuous innovation of High-k/metal gate technologies has en-abled EOT scaling down to 0.9 – 0.7 nm in production, however, new materials arenecessary for further EOT scaling. Recent advances in new channel material such asIII-V/Ge shows promising device performances, however, it is still behind of the stateof the art Si-CMOS technologies. comparable to state of the art Si-based MOSFETs.Device demonstration on emerging technologies (such as Tunnel FET, JunctionlessFET, Carbon-based FET..) is increasing, But we cannot draw a successful story toreplace the Si-CMOS and much longer time is needed for implementation of thesetechnologies in future generation devices.

Hiroshi IwaiTokyo Institute ofTechnology

Bio: Hiroshi Iwai received the B.E. and Ph.D. degreesin electrical engineering from the University of Tokyo andworked in the research and development of integrated cir-cuit technology for more than 25 years in Toshiba. He isnow a professor of Frontier Research Center and Dept. ofElectronics and Applied Physics, Interdisciplinary Grad-uate School of Science and Engineering, Tokyo Instituteof Technology, Yokohama, Japan. Since joining Toshiba,he has developed several generations of high density staticRAM’s, dynamic RAM’s and logic LSI’s including CMOS,bipolar, and Bi-CMOS devices. He has also been en-gaged in research on device physics, process technologies,and T-CAD related to small-geometry MOSFETs and highspeed bipolar transistors. He has authored and coau-thored more than 1,000 international and 400 domesticjournal/conference papers. His current research interestsare Nano CMOS, Power and Photovoltaic Devices: Si

Nanowire and III-V MOSFETs, GaN and Diamond Power devices, Si-nanowire andsilicide photovoltaic devices, and High-k gate insulator and Metal/silicide S/D tech-nologies. Dr. Iwai is, a fellow of IEEE, a fellow of Institute of Electrical EngineersJapan, a fellow of the Japan Society Applied Physics, and a fellow of the Institute ofElectronics, Information and Communication Engineers of Japan. He is a recipient ofmany prize and awards such as J.J. Ebers Award, Prizes for Science and Technologyby the Minister of Japan.

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Testing and Debugging VLSI System

Masahiro Fujita, Tokyo UniversityAbstract: When testing circuits, advanced semiconductor technology needs widerranges of attention, i.e., not just stuck-at faults but many others. From the viewpointof logical functionality, functional faults are most general and can cover varieties offaults actually happening in the modern VLSI systems. As there are so many possibleways of faults in functional faults, their complete testing has been believed to be out ofpractice. Thanks to the recent advances in tools for Boolean reasoning, complete test-ing of such functional faults can be very practical, if we use implicit methods insteadof traditional explicit methods. The researches have shown that very small numbersof test vectors can actually guarantee complete checking of all possible fictional faults.Moreover, functional faults can also represent logical bugs, if the bugs are within thetarget faulty region. In this talk, we review the state-of-the-art techniques for testing,verifying, and diagnosing VLSI designs and implementations with emphasizing futureperspective.

Masahiro FujitaTokyo University

Bio: Masahiro Fujita received his Ph.D. in Informa-tion Engineering from the University of Tokyo in 1985 onhis work on model checking of hardware designs by usinglogic programming languages. In 1985, he joined Fujitsuas a researcher and started to work on hardware auto-matic synthesis as well as formal verification methods andtools, including enhancements of BDD/SAT-based tech-niques. From 1993 to 2000, he was director at FujitsuLaboratories of America and headed a hardware formalverification group developing a formal verifier for real-lifedesigns having more than several million gates. The devel-oped tool has been used in production internally at Fujitsuand externally as well. Since March 2000, he has been aprofessor at VLSI Design and Education Center of the Uni-versity of Tokyo. He has done innovative work in the areasof hardware verification, synthesis, testing, and softwareverification-mostly targeting embedded software and web-

based programs. He has been involved in a Japanese governmental research project fordependable system designs and has developed a formal verifier for C programs thatcould be used for both hardware and embedded software designs. The tool is nowunder evaluation jointly with industry under governmental support. He has authoredand co-authored 10 books, and has more than 250 publications. He has been involvedas program and steering committee member in many prestigious conferences on CAD,VLSI designs, software engineering, and more. His current research interests includesynthesis and verification in SoC (System on Chip), hardware/software co-designs tar-geting embedded systems, digital/analog co- designs, and formal analysis, verification,and synthesis of web-based programs and embedded programs.

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Brighter side of Dark Silicon

S K Nandy, IISc BangaloreAbstract: Desktop supercomputing is a felt need for a large class of challenging andcompelling applications spanning healthcare to climate modeling. In keeping withMoore’s Law, as technology nodes continue to shrink, we enter the era of ”Dark Sili-con”, where we are confronted with the Utilization Wall. General purpose processingon multi-cores is no more a panacea for the ILP, Memory, and Power wall. In thispresentation, we will seek answers to the question: Can (post silicon) runtime recon-figuration of hardware to compose custom datapaths and processing cores on demandserve as the brighter side of dark silicon for desktop supercomputing?

Bio: S. K. Nandy is a Professor at the Supercomputer Education and ResearchCentre, and the Department of Electronic Systems Engineering of the Indian Insti-tute of Science, Bangalore, India. He is the convener of the Computer Aided DesignLaboratory, a state-of-the-art laboratory for VLSI Systems Design set up in 1985 withthe assistance of the UNDP and the Department of Electronics, Government of India.

S K NandyIISc Bangalore

His current research interests include Dataflow and Flexi-ble Multi-core Processor Architectures, Micro-architecturaland Compiler optimizations for power and performance,Chip Multiprocessors (CMPs) and Runtime ReconfigurableMultiprocessor Systems on Chips (MP-SoCs), and CloudSystems. Prof. Nandy has over 130 research publica-tions in International Journals and Proceedings of Inter-national Conferences that highlight his research contri-butions. He is responsible for setting up Morphing Ma-chines (url: www.morphingmachins.com), a technology in-cubated start-up company from the Indian Institute of Sci-ence, engaged in the development of Reconfigurable SiliconCores, where he holds the position of Honorary Chief Sci-entist. Prof. Nandy obtained his B.Sc.(Hons.) degree in

Physics from the Indian Institute of Technology, Kharagpur in 1977. He obtained hisB.E.(Hons.) degree in Electrical Communications Engineering in 1980, M.Sc.(Engg.)degree in Computer Science and Engineering in 1987, and Ph.D degree in ComputerScience and Engineering in 1989 from the Indian Institute of Science, Bangalore.

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Net of Things to Internet of Things

Wei Zhao, Macau UniversityAbstract: Internet of Things (IoT) is a networking infrastructure for cyber-

physical systems. With IoT, physical objects should be seamlessly integrated intoan Internet- like system so that the physical objects and cyber-agents can interacteach other in order to achieve mission-critical objectives. Internet of Things (IoT)should have tremendous application potential and hence has become popular in recentyears, attracting great attentions from both academic research and industrial develop-ment. In this talk, we will first focus on fundamental issues related to IoT. We arugemost of R/D work has focused on ”Net of Things”. Efforts are needed to create ”In-ternet of Things”. We address principles that should guide research and developmentof IoT. We will then present several approaches that may lead to implementation ofIoT and analyze their advantages and disadvantages. Finally, we will discuss criticalissues that must be addressed in order to fully realize the objectives and potentials ofIoT.

Wei ZhaoMacau University

Bio: Wei Zhao is currently the Rector of the Universityof Macau (UM). Before joining the University of Macau,Professor Zhao served as the Dean of the School of Sci-ence at Rensselaer Polytechnic Institute, Director for theDivision of Computer and Network Systems in the U.S. Na-tional Science Foundation, and Senior Associate Vice Pres-ident for Research at Texas A&M University. As an IEEEFellow, Professor Zhao has made significant contributionsin distributed computing, real-time systems, computer net-works, and cyberspace security. His research group hasbeen well recognized and received numerous awards andprizes including the outstanding paper award (1992) fromthe IEEE International Conference on Distributed Com-puting Systems, the best paper award (1998) from theIEEE National Aerospace and Electronics Conference, anaward on technology transfer from the Defense Advanced

Research Program Agency in 2002, and the best paper award (2008) from the IEEEInternational Communication Conference. In 2007, he received the IEEE Transactionson Parallel and Distributed Systems Outstanding Achievement Award. Professor Zhaois the holder of two U.S. patents and has published over 300 papers in journals, con-ferences, and book chapters. In 2011, he was named by the Ministry of Science andTechnology as the Chief Scientist of the national 973 Internet of Things Project oncyber-physical networking systems. Recognizing his accomplishments in educationleadership and scientific research, Wei Zhao has been a recipient of 12 Honoral doc-toral degrees.

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Your Synthesis is Broken @ 14nm: Physical tothe Rescue

Sanjiv Taneja, CadenceAbstract: The small world of sub-20nm is already upon us and has brought a newset of challenges for RTL designers as the race for best PPA (performance, power, andarea) continues unabated. Challenges include giga-scale integration of new function-ality, new physics effects, new device structures such as FinFETs, interconnect stackswith vastly varying resistance characteristics from bottom to top layers in a non-linearfashion and process variation. These challenges are raising several questions. Can RTLsynthesis handle giga-scale, giga-hertz designs in a timeframe of market relevance? Canlogic synthesis perform accurate and predictive modeling of the interconnect stack, viasand other physical effects in RTL? How do new device structures affect dynamic andleakage power tradeoff and library choices? How do logic structuring, cell selection,clock gating, and DFT choices change to anticipate and handle routing congestion?

Sanjiv TanejaCadence

And how do we ensure strong correlation between logic syn-thesis and P&R/signoff? This talk will explore these chal-lenges and provide an overview of state-of-the-art technol-ogy to address them in a predictive and convergent designflow.

Bio: Sanjiv Taneja is VP of Product Engineering forthe Front End Design Group at Cadence Design Systems.Prior to assuming this role in 2010, he led Cadence’s En-counter Test R&D group for over five years. He joined Ca-dence from Bell Laboratories where he led the developmentof transistor-sizing based technology for low power design.Sanjiv holds a BS degree in EE from IIT New Delhi, MSin Computer Science from Ohio State University and MBAfrom NYU.

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Combining Advanced Fault Models and EfficientTest Methods

Janusz Rajski, Mentor GraphicsAbstract: Semiconductor manufacturing always had to balance the desired productquality with the impact on the design process (silicon area, design time) and the costof manufacturing test. Fault models are used to achieve the quality objectives. At 130nm the industry started using the transition fault model in addition to the stuck-atfault. Since then we have added multiple detection capabilities, timing information,layout, and transistor-level models of standard cell libraries. In 2001 test compressionwas introduced, on top of scan, to reduce the cost of manufacturing test. What othertechnologies will be needed to address the issue of growing design sizes, increasingvolume of test data, and longer test times? Will those be new breakthroughs in testcompression, logic BIST or hybrids?

Janusz RajskiMentor Graphics

Bio: Janusz Rajski received the M.S. degree in electri-cal engineering from the Technical Uni-versity of Gdansk,Gdansk, Poland, in 1973, and the Ph.D. degree in electri-cal engineering from the Poznan University of Technology,Poznan, Poland. He is a chief scientist and the director ofengineer-ing for the Silicon Test Solutions products groupat Mentor Graphics. He has published more than 200 re-search papers in these areas and is co-inventor of 80 USpatents. He is also the principal inventor of EmbeddedDeterministic Test (EDT(tm)) technology used in the firstcommercial test compression prod-uct TestKompress(R).He was co-recipient of the 1993 Best Paper Award forthe paper on logic synthesis published in the IEEE Trans-actions on Computer-Aided Design of Integrated Circuitsand Systems, co-recipient of the 1995 and 1998 Best PaperAwards at the IEEE VLSI Test Symposium, co-recipient

of the 1999 and 2003 Honorable Mention Awards and the 2012 Most Significant PaperAward at the IEEE International Test Conference, co-recipient of the 2010 Best PaperAward at the IEEE European Test Symposium, co-recipient of the 2008 Best PaperAward at the Asian Test Symposium, and 2009 Best Paper Award at the VLSI De-sign, as well as co-recipient of the 2006 IEEE Circuits and Systems Society Donald O.Pederson Outstanding Paper Award recognizing the paper on embedded determinis-tic test published in the IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems. He served as Program Chair of the IEEE International TestConference. In 2009 he received the Stephen Swerling Innovation Award from MentorGraphics ”for his breakthrough innovation, TestKompress, and his many contributionsto revitalizing Mentor’s DFT business to its current position as #1 test business inEDA””. In 2011 Janusz was elevated to the grade of IEEE Fellow for ”contributionsto VLSI circuit testing and test compression”. In 2013 he was awarded an honorarydoctorate from the Poznan University of Technology, Poznan, Poland.

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Design and Test Challenges for Cyber-PhysicalSystems

Zebo Peng, Linkoping UniversityAbstract: There is an exponentially increasing number of cyber-physical systemswhere the computational components interact with the physical world in a tightlymanner. Many of these systems are nowadays used for safety-critical applications,such as automotive electronics and medical equipment, with stringent reliability andreal-time requirements. At the same time, with silicon technology scaling, integratedcircuits used to implement the computational components of these systems are builtwith smaller transistors, operate at higher clock frequency, run at lower voltage lev-els, and operate very often at higher temperature. Consequently, they are subject tomore faults and interferences. We are therefore facing the challenge of how to buildreliable and predictable cyber-physical systems with unreliable and unpredictable com-ponents. This talk will discuss the design of cyber-physical systems for safety-criticalapplications by considering both fault-tolerance and real-time predictability at thesame time. It will describe several key challenges and some emerging solutions to thedesign and test of such systems. In particular, it will present time-redundancy basedfault-tolerance techniques to address transient faults which have become more andmore common in nano-scale technology. It will also present several technology trendsand research directions in the field of cyber-physical systems.

Zebo PengLinkoping University

Bio: Zebo Peng received his Ph.D. in Computer Sci-ence from Linkoping University in 1987. He has beenProfessor and Director of the Embedded Systems Labora-tory at Linkoping University since 1996, and served as thehead of the Swedish National Graduate School in Com-puter Science in 2006-2008. His current research interestsinclude design and test of embedded systems, electronic de-sign automation, SoC testing, fault tolerant design, hard-ware/software co-design, and real-time systems. He haspublished over 350 technical papers and four books in theseareas, and has received four best paper awards and a bestpresentation award in major international conferences. Heserves currently as Associate Editor of the IEEE Transac-tions on VLSI Systems, the VLSI Design Journal, and theEURASIP Journal on Embedded Systems. He has servedon the program committee of a dozen international confer-ences, including ATS, DATE, DDECS, DFT, ETS, IOLTS,

RTCSA, and VLSI-SOC, and was the Program Chair of DDECS’04, ETS’07, DATE’08,and ETS’13.

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Carbon Nanotube Computer: Transforming Sci-entific Discoveries into Working Systems

Subhasish Mitra, Stanford UniversityAbstract: Carbon Nanotube Field Effect Transistors (CNFETs) are excellent

candidates for building highly energy-efficient future electronic systems. Unfortu-nately, carbon nanotubes are subject to substantial inherent imperfections that posemajor obstacles to large-scale CNFET digital systems. A combination of design andprocessing techniques overcomes these challenges by creating robust CNFET digitalcircuits that are immune to these inherent imperfections. This imperfection-immunedesign paradigm enables the first experimental demonstration of the carbon nanotubecomputer, and, more generally, arbitrary CNFET digital systems. Monolithically-integrated three-dimensional CNFET circuits will also be discussed. This researchwas performed at Stanford University in collaboration with Prof. H.-S. Philip Wongand several graduate students.

Subhasish MitraStanford University

Bio: Prof. Subhasish Mitra directs the Robust Sys-tems Group in the EE and CS departments of Stanford,where he is the Chambers Faculty Scholar of Engineering.Before joining Stanford, he was a Principal Engineer at In-tel. His research interests include robust systems, VLSI de-sign, CAD, validation and test, and nanotechnologies. Hishonors include the Presidential Early Career Award fromthe White House, the highest US honor for early-career out-standing scientists and engineers, IEEE CAS/CEDA Ped-erson Award, and the Intel Achievement Award, Intel’shighest honor. Prof. Mitra and his students publishedaward-winning papers at major venues: Design Automa-tion Conference, International Solid-State Circuits Confer-ence, International Test Conference, IEEE Trans. CAD,VLSI Test Symposium, and Symp. VLSI Technology. Heis a Fellow of the IEEE.

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Art and Science of Benchmarking Ultra Low PowerMicro-controllers.

Mahesh Mehendale, Texas InstrumentsAbstract: There is an exponentially increasing number of cyber-physical systemswhere the computational components interact with the physical world in a tightlymanner. Many of these systems are nowadays used for safety-critical applications,such as automotive electronics and medical equipment, with stringent reliability andreal-time requirements. At the same time, with silicon technology scaling, integratedcircuits used to implement the computational components of these systems are builtwith smaller transistors, operate at higher clock frequency, run at lower voltage lev-els, and operate very often at higher temperature. Consequently, they are subject tomore faults and interferences. We are therefore facing the challenge of how to buildreliable and predictable cyber-physical systems with unreliable and unpredictable com-ponents. This talk will discuss the design of cyber-physical systems for safety-criticalapplications by considering both fault-tolerance and real-time predictability at thesame time. It will describe several key challenges and some emerging solutions to thedesign and test of such systems. In particular, it will present time-redundancy basedfault-tolerance techniques to address transient faults which have become more andmore common in nano-scale technology. It will also present several technology trendsand research directions in the field of cyber-physical systems.

Mahesh MehendaleTexas Instruments

Bio: Mahesh Mehendale leads the Kilby Labs at TexasInstruments India. His present areas of focus include ultra-low power MCUs. Prior to this, he worked on architec-tures for low power HD video compression. Since joiningTI in 1986, he has led the development of multiple indus-try leading digital and system-on-a- chip designs includingC27x/C28x DSPs (first commercial DSP designed in India)and DM642 digital media processor. In recognition of histechnical leadership and high impact innovations, he waselected as TI Fellow in 2003 – first one in TI Asia. Maheshhas done B. Tech (EE, ‘84), M. Tech (CSE, ‘86) and Ph.D.(’00) from the Indian Institute of Technology, Bombay. Hehas published more than 45 papers at international confer-ences/journals and presented many invited talks/tutorials.He was the general co-chair for the VLSI Design 2010 con-

ference. He has co-authored a book on “VLSI synthesis of DSP kernels” published byKluwer Academic Publishers and a chapter on “Introduction to SoC” for a book onSystem on a Package (SOP) published by McGraw-Hill. Mahesh holds 6 US patentsand was elected senior member of IEEE in 2000. He received the “DistinguishedAlumnus” award from IIT Bombay in March 2012.

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