actel proasic a3pe3000l-pq208 field programmable gate ......1 actel proasic a3pe3000l-pq208 field...

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Actel ProASIC A3PE3000L-PQ208 Field Programmable Gate Array Single Event Effects (SEE) High-Speed Test Plan- Phase II

Melanie Berg – Principle Investigator MEI

HAK Kim, Mark Friendlich, Chris Perez, Christina Seidlick: MEI Ken Label: NASA/GSFC

Test Dates: 9/2011 ACTEL PROASIC A3PE3000L-‐PQ208 FIELD PROGRAMMABLE GATE ARRAY SINGLE EVENT EFFECTS

(SEE) HIGH-‐SPEED TEST PLAN-‐ PHASE II .......................................................................................................... 1

MELANIE BERG – PRINCIPLE INVESTIGATOR MEI ................................................................................ 1

HAK KIM, MARK FRIENDLICH, CHRIS PEREZ, CHRISTINA SEIDLICK: MEI ............................................... 1

KEN LABEL: NASA/GSFC ..................................................................................................................... 1

1. INTRODUCTION .......................................................................................................................... 3

2. BACKGROUND ............................................................................................................................ 3 2.1 THE PROASIC3 DEVICE ARCHITECTURE AND DESIGN BUILDING BLOCKS .................................................... 3 2.2 INITIAL PHASE OF PROASIC3 HEAVY ION TESTING ................................................................................. 5

3. ANALYSIS TOOLS: NASA REAG FPGA SEU MODEL ........................................................................ 5 3.1 PCONFIGURATION ..................................................................................................................................... 6 3.2 P(FS)FUNCTIONALLOGIC ............................................................................................................................. 6

4. MITIGATION STRATEGIES ......................................................................................................... 11

5. DEVICES AND DESIGNS TESTED ................................................................................................. 13 5.1 GLOBAL ROUTES ............................................................................................................................ 14 5.2 SHIFT REGISTER ARCHITECTURES (WSRS) .......................................................................................... 14

5.2.1 Functional Description ........................................................................................................ 14 5.2.2 Combinatorial Logic and Sequential Logic Elements in the WSR ........................................ 16 5.2.3 WSR to Tester Interface ...................................................................................................... 18 5.2.4 Data Input Patterns for WSRs ............................................................................................ 19 5.2.5 WSR Output ........................................................................................................................ 19 5.2.6 WSR Expected Upsets ......................................................................................................... 20

5.3 COUNTER ARRAY ........................................................................................................................... 21 5.3.1 Counter Array Implementation .......................................................................................... 22 5.3.2 Counter I/O Interface and Expected Outputs ..................................................................... 24 5.3.3 Counter Expected Upsets .................................................................................................... 25 5.3.4 Summary of Counter Array Test Evaluations ...................................................................... 25

5.4 DSP BLOCKS ................................................................................................................................. 26 5.4.1 Process for loading ‘A’ coefficients ..................................................................................... 26 5.4.2 Process for loading ‘B’ coefficients ..................................................................................... 26

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5.4.3 Process for loading ‘C’ coefficient ...................................................................................... 26 5.4.4 DSP I/O Interface and Expected Outputs ............................................................................ 30 5.4.5 DSP Expected Upsets .......................................................................................................... 31 5.4.6 Summary of DSP Test Evaluations ...................................................................................... 31

6. LOW COST DIGITAL TESTER (LCDT) TEST VEHICLE ...................................................................... 31 6.1 ARCHITECTURAL OVERVIEW ............................................................................................................. 32

6.1.1 I/O List and Definitions ....................................................................................................... 33 6.2 RS232 COMMUNICATION FROM THE LCDT TO THE HOST PC ................................................................ 36 6.3 RS232 COMMUNICATION FROM THE HOST PC TO THE LCDT ............................................................... 36

6.3.1 User GUI ............................................................................................................................. 36 6.3.2 User Interface and Command Control ................................................................................ 38

7. DUT TEST PROCEDURES ............................................................................................................ 40 7.1 WSR TESTING ............................................................................................................................... 40

7.1.1 Dynamic: Evaluate susceptibility of WSR ........................................................................... 40 7.2 COUNTER ARRAY TESTS .................................................................................................................. 41

7.2.1 Dynamic: Evaluate susceptibility of Counter DFF cells in biased-‐dynamic states ............... 41 7.3 DSP TESTS ................................................................................................................................... 41

7.3.1 Dynamic: Evaluate susceptibility of DSP Blocks in biased-‐dynamic states ......................... 41 7.4 RUNNING A FULL TEST .................................................................................................................... 41

7.4.1 WSR Tests ........................................................................................................................... 42 7.4.2 Counter Tests ...................................................................................................................... 42 7.4.3 DSP Tests ............................................................................................................................ 43

8. PROCESSING THE DUT OUTPUTS ............................................................................................... 43 8.1 WSR, COUNTER, H3FSM SHIFT_CLK PROCESSING ........................................................................... 43 8.2 WSR DATA PROCESSING ................................................................................................................. 44

8.2.1 WSR SEU Cross Section Calculations .................................................................................. 46 8.3 COUNTER ARRAY DATA PROCESSING ................................................................................................. 47

8.3.1 Counter Array Data Capture and compare ......................................................................... 47 8.3.2 Counter Array Error Record ................................................................................................ 47 8.3.3 Counter Array SEU Cross Section Calculations ................................................................... 48

8.4 DSP DATA PROCESSING .................................................................................................................. 49 8.4.1 DSP Block Error Record ....................................................................................................... 49 8.4.2 DSP SEU Cross Section Calculations .................................................................................... 50

9. HEAVY ION TEST FACILITY AND TEST CONDITIONS .................................................................... 50

10. HEAVY ION TEST RESULTS ....................................................................................................... 51 10.1 SINGLE EVENT LATCHUP (SEL) ....................................................................................................... 51 10.2 CONFIGURATION AND TESTING DIFFICULTIES .................................................................................... 52

10.2.1 Phase I First Test Trip 05/2010 ......................................................................................... 52 10.2.2 Phase I Second Test Trip 08/2010 .................................................................................... 52 10.2.3 Phase II Test Trip 08/2011 ................................................................................................ 52 10.2.4 Summary of Reprogramming issue .................................................................................. 53

10.3 NO-‐TMR ................................................................................................................................... 53 10.3.1 Test Phase WSR σSEU comparisons ................................................................................... 53 10.3.2 Data Pattern No-‐TMR WSR σSEU comparison ................................................................... 54 10.3.3 Frequency and Combinatorial Logic Trends with No-‐TMR WSRs ..................................... 55 10.3.4 No-‐TMR Counters -‐ SEU per Bit Analysis .......................................................................... 63

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10.3.5 No-‐TMR Counters Frequency Analysis .............................................................................. 68 10.3.6 No-‐TMR Counters -‐ Multiple Bit versus Single Bit SEUs .................................................... 69 10.3.7 No-‐TMR DSP Blocks .......................................................................................................... 73

10.4 LTMR ....................................................................................................................................... 74 10.4.1 LTMR Shift Registers and LET and Input Data Pattern ..................................................... 74 10.4.2 LTMR Shift Registers – Frequency and Combinatorial Logic Effects ................................. 80 10.4.3 Contrast between No-‐TMR and LTMR σSEUs ..................................................................... 84 10.4.4 LTMR Counters ................................................................................................................. 84

10.5 DTMR COUNTER σSEUS ................................................................................................................ 88 10.6 σSEU COUNTER COMPARISONS: PROASIC3 VERSUS RTAXS ................................................................ 91 10.7 PROASIC3 BURST σSEUS ............................................................................................................... 92

11. SUMMARY ............................................................................................................................. 94

12. APPENDIX 1: ........................................................................................................................... 96

1. INTRODUCTION This study is a continuation of the initial phase of Single Event Effect (SEE) evaluation for the

ProASIC3 Field Programmable Gate Array (FPGA) family of devices device. The investigation focuses on the single event destructive and transient susceptibility of various designs implemented in the ProASIC3. In this document, the ProASIC3 is considered the Device Under Test (DUT). The DUTs will be monitored for Single Event Transient (SET), Single Event Upset (SEU), and potential destructive induced faults during heavy ion beam exposure.

2. BACKGROUND

2.1 The ProASIC3 Device Architecture and Design Building Blocks The ProASIC3 is a flash based FPGA. Flash-based FPGAs store their configuration

information in on-chip flash cells. Because flash is non-volatile, once programmed, the configuration data is an inherent part of the FPGA structure. It does not get lost during power-down hence no external (or additional) devices are required to store the configuration information to supplement the device power-up process[1].

The ProASIC3 logic building blocks are the central portion of the FPGA fabric and are referred to as VersaTiles. Their placement within the device is illustrated in Figure 1[1]. Figure 2 shows the logic that comprises a VersaTile[1]. Each Versatile can be configured to be a combinatorial logic block or a sequential logic block (Edge triggered DFF or latch). The block-level VersaTile schematic configurations are shown in Figure 3[1].

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Figure 1: ProASIC3 Device Architecture

Figure 2: VersaTile Logic. Each open switch is a programmable node controlled by a

configuration flash cell

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Figure 3: VersaTile Configuration Options 2.2 Initial Phase of ProASIC3 Heavy Ion Testing The DUT design structures investigated in the initial SEU study were:

• Windowed Shift Registers (WSRs) • Counter Arrays • Hamming Code3 State Machines

Prior heavy ion beam testing [2][3][4] has shown the following: • No Mitigation: DFF VersaTiles have the dominant SEU cross-section (σSEU) as compared to

combinatorial logic Versatiles. • Localized DFF Mitigation (LTMR): This is a mitigation strategy that logically masks upsets from

DFFs. Hence, DFFs do not contribute to the overall σSEU. Combinatorial VersaTiles have the dominant σSEU as compared to DFF VersaTiles

• High Linear Energy Transfer (LET) ions: Destructive event was observed such that the ProASIC3 was unable to be reprogrammed.

During the initial phase of this study (phase I), the devices were exposed to limited amounts of particle fluence. The phase I decision for limiting particle exposure was made to avoid destroying devices so that analysis can focus on SET and SEU characterization.

For this phase of evaluation (phase II), more devices have been obtained. Subsequently, particle fluence exposure can be increased to enhance SEU statistics without concern of destroying a limited number of parts. In addition, further investigation will be performed regarding the destructive reprogramming event.

Phase II testing replaces Hamming Code3 State Machines with semi-custom DSP blocks that perform (A*B+C) function. The goal is to further investigate SEU/SET behavior in complex design structures that contain a substantial amount of fan-in, fan-out, and combinatorial logic between DFF stages.

3. ANALYSIS TOOLS: NASA REAG FPGA SEU MODEL FPGA devices and their design implementations are complex structures to evaluate. Structure

complexity creates convoluted error signatures during radiation testing. This forces the major issue during evaluation to be the identification of SEU error sources. Accordingly, model development and application have become essential components of SEU test and analysis. Prior usage of models developed by NASA Goddard Radiation Effects and Analysis Group has successfully identified SEU sources and correlated their trends. The purpose of such evaluation is to formulate error types so that FPGA designers can optimize their design based on criticality requirements, device type, and radiation

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environment. In a synchronous design, it is understood that SEUs/SETs can occur in:

• Configuration • Flip-Flops: DFFs • Combinatorial Logic (CL) • Clock trees • Reset trees • Embedded memory • Inputs or Outputs: (I/O)

Phase II analysis does not include embedded memory analysis or I/O analysis. It has been shown [2][3] that the Single Event Upset (SEU) probability (P(fs)error) model for

Field Programmable Gate Array (FPGA) devices has three major components: Configuration SEU cross section (Pconfiguration), Data path or functional logic SEU cross section (PFuctionalLogic), and a Single Event Functional Logic SEU cross section (PSEFI). P(fs)error is reflected in (1).

𝑃!"# 𝑓𝑠 ∝ 𝑃!"#$%&'()*%"# + 𝑃(𝑓𝑠)!"#$%&'#()*'+&$+𝑃!"#$ (1) The SEU Probability model is used by NASA Radiation Effects and Analysis Group (REAG)

as a Single Event Effects (SEE) data analysis tool. Upsets that occur during radiation testing are differentiated and are categorized in order to enhance device evaluation. The model is a reflection of the SEU cross section (σSEU) for a synchronous digital system. Operational frequency (fs) is understood to be the inverse of clock period (τclk) as in (2).

(2)

3.1 Pconfiguration Because the ProASIC3 configuration is flash-based, the configuration is considered hard regarding

radiation environments (Pconfiguration≈0). In other words, the configuration’s SEU rate is low to null. However, as previously mentioned, a destructive event pertaining to the configuration has been observed during high Linear Energy Transfer (LET) exposure and is investigated in this phase of testing

3.2 P(fs)functionalLogic The functional logic data path of a synchronous design is comprised of: Combinatorial Logic,

Flip-Flops (DFFs), and Routes. Table 1 illustrates upset types that can potentially occur in a FPGA data path.

fsclk1

=τ

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Table 1: Combinatorial Logic versus Sequential Logic. Term Definition

Logic function generation (computation)

Captures and holds state of combinatorial logic

SET: Glitch in

the combinatorial logic: Capture is frequency dependent

Double-sided

SEU: DFF flips its state. Can occur at a clock edge or during the clock cycle. Depending on which part of the circuit is upset, will determine if the capture is frequency dependent.

Single-sided

Although upsets can be generated, SEUs and SETs are not considered to disrupt the system unless they are captured and manifest into the system state. The following is an explanation of how SEUs and SETs can cause a system to malfunction.

A synchronous system is comprised of DFFs and combinatorial logic blocks. Each DFF has its unique function and is evaluated as the function’s EndPoint. EndPoint DFFs are fed by a group of Start-Point DFFs and combinatorial as illustrated in Figure 4.

CLK CLKB

CLKB

CLK

CLKB CLK

CLK

CLKB

D Q

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Figure 4: Synchronous Design Cone of Logic. EndPoint DFF is fed by a group of

StartPoint DFFs and combinatorial logic

Figure 5: SEU occurring in a StartPoint DFF in between clock edges. Will it manifest as a

system upset?

Figure 6: SET occurring in a combinatorial logic gate in between clock edges. Will it

captured by its EndPoints?

Q

QSET

CLR

D

DFF will be evaluated as an End-Point with itself as a Start-Point

tdly))1(()( −= TStartDFFsfTEndDFF

“Cone of Logic”

TT-1 T+1

Combinatorial logic create delay (τdly ) from StartPointsto EndPointsEndpoints capture only at clock edge

τdly τclk

0

11

0

1

If DFFD flips its state @ time=τ:0<τ <τclk −τdly

The upset has time to get caught…Probability of capture: 1- (τdly/τclk)

1

0???

τclk@T-1

τclk@T

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

DQ

QSET

CLR

D

1

0

10

1 0(A XOR B) AND (C XOR D)XOR

XOR

AND ???

A

B

C

D

Start-Points

End-Point

If an SET is generated, it will need to:·∙ Propagate to an End-Point·∙ Be active during the End-Point’s clock edge·∙ Be captured by the End-Point

SET

t clk@T

t clk@T-1

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In order to identify error signatures during radiation testing, it is important to understand how upsets can occur and potentially manifest in a synchronous design (i.e., disrupt system state). The following is a list of scenarios of system state disruption:

• A DFF can be hit such that the SEU/SET manifests at its next clock edge. In this case, the DFF is upset at the clock edge and is considered a disruption in system state.

• A StartPoint can flip its logic value in between clock edges. This is an interim point in a synchronous design and is not yet considered a disruption in system state. The interim flip will cause an erroneous state if:

• The StartPoint DFF flip can affect an EndPoint’s logic value by the next clock cycle (see Figure 5)

• If the StartPoint is in a hold state (i.e., no new data is expected at the next clock edge) • A combinatorial logic gate can be hit such that the SET will propagate to DFFs

(EndPoints) and have the potential to be captured at their next clock edge (see Figure 6).

Terminology is as follows: An upset (SEU) that occurs in a DFF (considered the StartPoint DFF) has a probability of

occurrence (P(fs)DFFSEU). The StartPoint SEU has the potential to be captured by an EndPoint DFF with a probability of P(fs)DFFSEU→SEU. An upset can also occur as a transient in combinatorial logic. It has the potential to be captured by an endpoint DFF with a probability of (P(fs)SET→SEU).

Putting it all together (Eq. 3): SEUs that occur in the functional logic path of a synchronous

design can be modeled as such (3):

(3)

P(fs)DFFSEU→SEU and P(fs)SET→SEU have been further broken down in Eq 4. Table 2 defines the

terms used in the more detailed model.

⎟⎟⎠

⎞⎜⎜⎝

⎛+∃∝ ∑∑

=→

=→

ialCellsCombinator

iiSEUSET

DFFsStartPo

jjSEUDFFSEUDFFLogicfunctional fsPfsPfsP

#

1)(

int#

1)( )()()(

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Table 2: Definition of Terms Term Definition P(fs)DFFSEU Probability a Start-point DFF will incur an SEU. A percentage (α) of SEUs will manifest

in the StartPoint DFF at the clock edge and will subsequently be a system error. A percentage (β) of SEUs will occur in between clock edges and will need to be captured by the End-Point at the next clock edge to become a system error.

1-τdlyfs Portion of clock cycle that the End-Point DFF can capture a Start-point DFF SEU before

the next clock edge. Assumes the SEU Start-point DFF is always enabled and will have a valid value at the next clock edge

Pgen Probability a combinatorial gate will incur a SET

Pprop Probability the SET can propagate to an End-point DFF

τwidthfs SET width to clock period ratio

𝑃(𝑓𝑠)!"#$%&'#()*'+&$ ∝

((𝛼𝑃 𝑓𝑠 !""#$% ! +#!"#$"%&'(" !""#

!!!

𝛽P 𝑓𝑠 !""#$% ! (1 − 𝜏!"#𝑓𝑠)) ∗ 𝑃!"#$%) +

(𝑃!"#

#!"#$%&'(")%'* !"##$

!!!

∗ 𝑃!"#! ∗ 𝑃!"#$% ∗ 𝜏!"#𝑓𝑠)

(4)

The model in Eq 4 is used as an SEU data analysis tool. It assists in determining if DFFs or combinatorial logic have the more dominant SEU cross sections (σSEU). It also assists in evaluating the strength of the applied mitigation strategy.

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Table 3: Analysis of SEU Capture Effects: P(fs)DFFSEU→SEU versus PSET→SEU. P(fs)DFFSEU→SEU=(αP(fs)DFFSEU+βP(fs)DFFSEU(1-τdlyfs )

αP(fs)DFFSEU βP(fs)DFFSEU(1-τdlyfs ) P(fs)SET→SEU Logic Direct DFF Upset at

clock edge DFF Capture of interim Startpoint SEU

Combinatorial SET Capture

Capture percentage of clock period

? unknown

1-τdlyfs = 1-τdly /τclk

As frequency increases, PDFFSEU→SEU increases

Frequency Dependency Increase in frequency increases PDFFSEU→SEU

Increase in frequency decreases PDFFSEU→SEU

Increase in frequency increases PSET→SEU

Combinatorial Logic Effect

N/A

Increase in Combinatorial logic increases τdly and decreases PDFFSEU→SEU

Increase in Combinatorial logic increases PSET→SEU

Based on Table 3, the following is a list of trends used for evaluating σSEU data and

determining dominant sources of susceptibility:

• βP(fs)DFFSEU→SEU Dominance – Most SEUs stem from Captured Start-point DFFs: o If there is an increase in the number of combinatorial logic blocks or τdly and the σSEU

(Perror) decreases in response o If there is an increase in frequency and the σSEU (Perror ) decreases in response

• P(fs)SET→SEU Dominance – Most SEUs stem from Captured Combinatorial Logic SETs: o if there is an increase in frequency and σSEU (Perror ) increases in response o if there is an increase in combinatorial logic and σSEU (Perror ) increases in response

• Local Mitigation Strength: if the design has been mitigated using a localized-DFF mitigation scheme such as Localized Triple Modular Redundancy (LTMR) or Dual Inter Cell (DICE)[6]:

o With localized mitigation, it is expected that the DFFs are masked from σSEU contribution. P(fs)DFFSEU→SEU should be insignificant and hence σSEU is lower.

o However, if P(fs)DFFSEU→SEU has the most significant error contribution for a localized-DFF mitigation scheme, then the mitigation scheme is considered weak because it is not fully masking DFF upsets.

4. MITIGATION STRATEGIES

The ProASIC3 devices are commercial and do not contain Radiation Hardened by Design (RHBD) Circuits in their functional data path. Hence, a design without mitigation will have substantial

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P(fs)DFFSEU→SEU and P(fs)SET→SEU upset components. In order to investigate the device and the effectiveness of applied mitigation strategies, common SEU test structures were implemented such as: WSRs and Counter Arrays [2]. All designs tested have different versions of applied mitigation. Application of mitigation was performed using the Mentor Graphics RadHard Synthesis tool set[4]. Mitigation strategies were:

• None: no additional circuitry is added to the design pertaining to SEU mitigation

• LTMR: Localized Triple Modular Redundancy. Only DFFs are triplicated. Combinatorial logic paths, Clocks, and resets are shared and consequently single sources of failure. With this mitigation strategy, only the effects of P(fs)DFFSEU is reduced (because they are masked). Subsequently, transients can be captured by their destination DFFs (P(fs)SET→SEU) and Global routes can cause Single Event Functional Interrupts (PSEFI). Figure 7 is an illustration of applied LTMR.

• DTMR: Distributed Triple Modular Redundancy. The entire design is triplicated except for global routes (clocks, resets, and high fanout enables). This mitigation strategy reduces PDFFSEU and PSET→SEU. However, since the global routes are not mitigated, then PSEFI still exists. Figure 8 is an illustration of the application of DTMR.

Global Triple Modular Redundancy (GTMR – everything is triplicated included clock domains) was not examined because this scheme requires at least three separate global clock trees to have less than 500ps of skew from each other. The ProASIC clock trees have minimal skew within a clock tree but contain too much skew (for GTMR purposes) between separate clock trees.

Figure 7: Applied LTMR ... Only the DFFs are triplicated. Consequently data inputs to

each DFF are shared and are single points of failure

CombLogic

Voter

Voter

Voter

LTMR DFF

DFF

DFF

DFF

DFF

DFFDFF

DFF

DFF

DFF

DFF

DFFComb Logic

Comb Logic

Comb Logic

Comb Logic

Comb Logic

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Figure 8: Application of DTMR. All functional logic is triplicated except global routes

(Clocks and Resets are not triplicated)

5. DEVICES AND DESIGNS TESTED There are 6 designs that will be tested. 18 devices are available for heavy ion testing. The

emphasis is to test variations over the design state space. The devices were manufactured on an advanced 0.13µm, 7-level metal CMOS Process enhanced with Flash Technology. The manufacturer is Microsemi. The devices tested have Lot Date Codes of 0506 and 0543.

The designs are controlled and upsets are processed using the NASA REAG Low Cost Digital Tester (LCDT) version 2. There were 3 major designs that were tested: Windowed Shift Registers (WSR) ,Counters, and DSPs. The following is a list of the 6 designs:

• Shift Registers: 6 Windowed Shift Register (WSR) Chains with varying numbers of inverters have been implemented.

1. No mitigation: P(fs)DFFSEU→SEU + P(fs)SET→SEU + PSEFI 2. LTMR: P(fs)SET→SEU + PSEFI

• Counter Arrays (CA): It should be emphasized that the design implemented to test the counters is a novel approach. In this study, there exist 200 counters (labeled 0 to 199) in the counter array. The LCDT can determine if an upset occurs in any of the counters and what bits were affected. A more detailed description will be provided in the following section.

3. No mitigation: P(fs)DFFSEU→SEU + P(fs)SET→SEU + PSEFI

4. LTMR: P(fs)SET→SEU + PSEFI 5. DTMR: PSEFI

• DSP: 6. No mitigation is inserted

CombLogic

DTMRVoter

Voter

Voter

Voter

Voter

Voter

Voter

Voter

Voter

DFF

DFF

DFFDFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF

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5.1 Global Routes

All of the designs for radiation testing utilized the special global routing networks provided by the ProASIC3 device. There are two types of global networks: High-Drive, Low Skew Clocks, and high-drive minimal skew nets. Global Clocks can only be connected to the clock-pin of a DFF. This design rule keeps the Clock tree balanced and subsequently keeps the skew minimized. The alternate high-drive global routes are used for resets and high fan-out enables. The susceptibility of the global routes is under investigation.

The following sections provide more detailed descriptions for each implemented design. 5.2 Shift Register Architectures (WSRs)

Figure 9: Windowed Shift Register (WSR) Design contains 7 chains with various levels of

combinatorial logic between each DFF

5.2.1 Functional Description

In order to examine basic gate (sequential and combinatorial logic) sensitivity, REAG has selected a simple (yet enhanced) shift-register architecture as one of the FPGA DUT architectures for radiation testing. Data input to the shift registers is generated inside of the DUT. However, 2-bit selection is controlled by the tester. The tester selects between a constant 0-pattern, a constant 1-pattern, and an alternating checkerboard pattern. The selection architecture is illustrated in Figure 10.

Low Cost Digital Tester

4bitsWSR0 960DFFs

WS1 960DFFs

WSR2 960DFFsWSR3 960DFFs

WSR4 960DFFsWSR8 960DFFs

4bits

4bits

4bits

4bits

4bits

WSR Processing

WSR16 960DFFs 4bits

15

Figure 10: WSR Internal Data Input Circuit

The basic shift-register was enhanced by two features: (1) variations of inverter logic between flip-flop stages and (2) Windowed shift-register. The architecture is illustrated in Figure 11. The implementation of the windowed shift-register allows for reliable high-frequency testing by increasing board level signal integrity and simplifying DUT shift-register output data capture.

The DUT configuration schematic is illustrated in Figure 11:

MUX

Q

QSET

CLR

D

0

1

Checkerboard

Select from

Tester

Data Input to WSR

16

Figure 11: WSR Top Level Architecture

5.2.2 Combinatorial Logic and Sequential Logic Elements in the WSR The Principle Configuration of the WSRs contains 960 DFF’s with varying levels of combinatorial

logic (0, 1, 2, 3, 4, 8, or 16 inverters) between DFF’s. Strings are differentiated by inverter count and are referenced as: WSR0, WSR1, WSR2, WSR3, WSR4, WSR8, WSR16.

A By-4 clock divider circuit is implemented to shift the last 4 bits of the Shift register string into a DFF window (PROASIC_SHIFT_STRINGn). The window for each chain is output to the tester. A data clock (PROASIC_SHIFT_CLK) for each chain is also output to the tester for high speed synchronous data capture.

! DUT$Top$Level$Architecture$

Shift on Rising Edge of Clock

Last Shift register bits Shift on Rising Edge of Clock Once every 4 clock cycles into 4 bit Window

RTAX_SHIFT_STRINGn(3)

DUT WINDOWOutputs to Tester

CLK_SR0

Clock Tree Fans to all DFF’s

Clock Divider Circuit SHIFT_CLK

Inputs from Tester

CLK_SR0

D_SR

D_SR

Data through the shift register will change every clock cycle if the data input changes every

clock cycle



RTAX_SHIFT_STRINGn(0)ProASIC3_SHIFT-STRING(0)4

ProASIC3_SHIFT-STRING(1)4



17

Figure 12: WSR Shift Register Strings with Optional Combinatorial Logic. All DFFs in

one chain are connected to the same Clock Input and the same reset.

Various levels of combinatorial logic are used in order to measure possible transient susceptibility. If the ProASIC3 device is susceptible to transients, then faults will be frequency dependent. Table 4 and Table 5 list the logic resources contained within each shift register chain.

Each WSR chain has a delay between each shift register stage (τdly). Because the levels of combinatorial logic vary from WSR to WSR, each WSR will have a maximum frequency that the chain can operate. Subsequently, 3 clock domains (clock domain 0, clock domain 1, and clock domain 2) have been established so that chains which have similar maximum frequencies share a clock. The clock domain distribution is listed in Table 4 and Table 5.

Table 4: Detailed Breakdown of No-TMR WSR Chain Elements Chain

s #Inverters Clock

Domain DF

F Stages

Max Frequency from Static Timing Analysis Tool

Max Frequency during testing

0 None 0 960 211

200

1 1 0 960 206 200

2 2 0 960 210 180

3 3 0 960 203 180

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

N=0 Shift Register Chain

Data Input

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

WSR 4-Bit Output

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

N>0 Shift Register Chain

Data Input

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

WSR 4-Bit Output

E E E E E E E E

Enable Input

N levels of Inverters or buffers between DFF stages:

N =8, or 20

MUX

Q

QSET

CLR

D

0

1Checkerboard

Select from

Tester

Data Input to WSR

18

4 4 1 960 248 180

5 8 1 960 192 100

6 16 2 960 107 100

Table 5: Detailed Breakdown of LTMR WSR Chain Elements

Chains

#Inverters Clock Domain

DFF Stages

Max Frequency from Static Timing Analysis Tool

Max Frequency during testing

0 None 0 960 181

160

1 1 0 960 184 160

2 2 0 960 175 160

3 3 0 960 150 100

4 4 1 960 136 100

5 8 1 960 106 100

6 16 2 960 78 50

5.2.3 WSR to Tester Interface

Pertaining to Table 4 and Table 6, each WSR chain is supplied a clock (e.g. CLK_SR0) and reset (e.g. CLR_SR0) from the tester. Based on a pattern select input (PROASIC_PATTERN) to the DUT (output from tester), the DUT will calculate the desired WSR data input.

Table 6: WSR Interface. I/O direction is with respect to Tester. I/O Name B

its Dir

wrt to DUT

Description

PROASIC_SHFT_CLK0 1 OUT Chain 0 shift Clock PROASIC_SHFT_CLK1 1 OUT Chain 1 shift Clock PROASIC_SHFT_CLK2 1 OUT Chain 2 shift Clock PROASIC_SHFT_CLK3 1 OUT Chain 3 shift Clock

19

PROASIC_SHFT_CLK4 1 OUT Chain 4 shift Clock PROASIC_SHFT_CLK5 1 OUT Chain 5 shift Clock PROASIC_SHFT_CLK6 1 OUT Chain 6 shift Clock PROASIC_SHIFT_STRING0 4 OUT 4-bit windowed output of chain 0 PROASIC_SHIFT_STRING1 4 OUT 4-bit windowed output of chain 1 PROASIC_SHIFT_STRING2 4 OUT 4-bit windowed output of chain 2 PROASIC_SHIFT_STRING3 4 OUT 4-bit windowed output of chain 3 PROASIC_SHIFT_STRING4 4 OUT 4-bit windowed output of chain 4 PROASIC_SHIFT_STRING5 4 OUT 4-bit windowed output of chain 5 PROASIC_SHIFT_STRING6 4 OUT 4-bit windowed output of chain 6 PROASIC_PATTERN 2 IN Each chain shares the 2 bits from

this vector: The bits select which data input

pattern (all 0’s, 1’s, or checker board). See Table 7 for selection details

CLK_SR0 1 IN Clock to the WSR circuitry CLR_SR0 1 IN Reset to the WSR circuitry CLK_SR1 1 IN Clock to the WSR circuitry CLR_SR1 1 IN Reset to the WSR circuitry CLK_SR2 1 IN Clock to the WSR circuitry CLR_SR2 1 IN Reset to the WSR circuitry

5.2.4 Data Input Patterns for WSRs The possible shift-register data patterns are static-0, static-1, or checkerboard. The selection is

controlled by a user command prior to each test. The pattern selection is 2 bits per DUT chain.

Table 7: Shift Register Data Pattern Select Using the PROASIC_PATTERN Tester Output 2 bit Pattern Selection D_SR

00 static-0 01 static-1

10 or 11 Checkerboard

The PROASIC_EN0 and PROASIC_EN1 control signals are used to disable the shift registers that contain a significant amount of inverters between DFFs while performing high speed tests (up to 160MHz).

5.2.5 WSR Output The ProASIC_SHIFT_STRINGn is a heartbeat monitor. Where n stands for the WSR string

number (n=0 through 6) Every ProASIC_SHFT_CLKn cycle, ProASIC_SHIFT_STRINGn is evaluated to determine if an SEU occurred or if the string is alive.

The PROASIC_SHIFT_STRINGn output is the 4-bit window of the shift register. For a data

pattern of all 0’s, the PROASIC_SHIFT_STRINGn output will be all 0’s. For a data pattern of all 1’s,

20

the output will be all 1’s. For a checkerboard pattern, the last 4 bits of the shift register change every clock cycle. Because the WSR window is a snapshot of the last 4 shift register bits every 4 clock cycles, the window stays static (either a hex 5 or a hex A). The operation is illustrated in Figure 13.

Figure 13: WSR shift register operation for a checkerboard input. Every 4 clock cycles

the last 4 shift register bits are equivalent. Every 4-clock cycles the window gets a snap shot of the last 4 bits of the shift register. Consequently, the window is static under normal operating conditions

5.2.6 WSR Expected Upsets Because of the WSR structure, the string outputs are expected to be constant after the length of the

string cycles following reset de-assertion. Therefore, an error is easily detected by monitoring any change within the WSR outputs as illustrated in Figure 14: Example of WSR SEE DUT output to tester.

0 1 0 1 0 1 0 11 0 1 0 1

01 0 1 0 1 0 10 01 0 1

Hex 5

Hex A

0 1 0 1 0 1 0 11 0 1 0 1

01 0 1 0 1 0 10 01 0 1

Hex 5

Hex A

01 0 1 0 1 0 10 01 0 1

Hex AClock Cycle(n)

Clock Cycle(n+1)

Clock Cycle(n+2)

Clock Cycle(n+3)

Clock Cycle(n+4)

5 Cycles of Shift Register String

Last 4 bits of shift register. They are shifted into the window

every 4 clock cycles

Every 4 cycles, the last for bits are equivalent. Therefore the window is static under normal

operating conditions

21

Figure 14: Example of WSR SEE DUT output to tester

Primary Expected WSR Upsets:

• Bit flip in shift register: Will be observed in the window for 4 cycles (because window can only change once every 4 cycles).

• Bit flip in window: Upset will be observed for less than 4 clock cycles • Output transient: May not be able to distinguish from bit flip in window. However, the window be

upset for less than one cycle. • Global routes: An upset can occur in the clock or reset circuitry or enable circuitry (4 out of the 6

strings have enables). • Shift_clks can get disrupted or completely stop.

5.3 Counter Array During SEU testing, it would be ideal to be able to monitor every element of a complex design for

every cycle. This is generally not feasible because it would require a DUT output to the test vehicle for every observable node. Therefore, more creative designs and interfaces must be developed such that operation during irradiation is unrestricted (fast, continuous, and unobstructed) yet node observation is maximized. Just as important, the tester must be fast enough and robust enough to capture and process the data supplied by the DUT. Processing integrity is very important. Dropped or incorrectly processed data can drastically change error cross sections.

For the SEU testing of the ProASIC3 Counters, a simple yet effective interface was developed.

ProASIC_SHFT_STRINGn Stays Constant uless there is a SEE.WSR Provides Optimal Singal Integrity for SEE testing

ProASIC_SHFT_STRINGn

ProASIC_SHFT_CLKn

CLK_SR

22

5.3.1 Counter Array Implementation

Fig 15: Schematic of the 16-bit Counters and their Output Selection Logic. In this case,

the output selection logic is a shift register (Shifts up counter values to the output registers every 4 cycles)

The counter array developed by REAG is illustrated in Fig 15. The array implemented for ProASIC3 heavy ion testing contains 200 counters that were 16 bits wide. Because it is impossible to simultaneously output 200 by 16 bits, requiring 3200 outputs, an output scheme had to be employed that would not compromise the number or speed of the counters yet ensure that each counter is an observable node. Conventional thinking would suggest employing a multiplexer that sequences through the array and selects one of the 200 counters to be output at a time. Unfortunately, the function of the multiplexer, selecting 200 items, requires many levels of combinatorial logic which can be problematic during radiation testing and will slow down the operation of the circuit. Such a large block of logic can potentially mask the primary objective which is characterizing counter SEU susceptibility. Therefore, a novel output methodology had to be established.

Low Cost Digital Tester

Counter 0Counter 1

Counter 198Counter 199

Shift Up RegistersEvery 4 Clock cycles

1

198199

Simultaneously Shift All Counters

Into Register Bank once every

800 =(4*200) Clock Cycles

Once every 4 clock cycles,Output Top Most Value to Tester

Then Shift Up the next Value0

2

Cell(n-1) <= Cell(n) once

every 4 clock cycles

16 Counter Processing

16 bits

16 bits

23

Fig 16: Counter Shift Register Cycles; Numbers in shift registers represent counter labels

at a given moment in time. If there is an x with the shift register, then it is considered a “don’t-care” state

As an alternative, a “snap-shot” solution was implemented. With this methodology, each counter is captured simultaneously at a given time into a bank of registers. The number of registers is equivalent to the number of counters (i.e. each counter has its own snapshot register). This is illustrated in Fig 15. The top of the register bank (register 0) is the only register that is accessible by the tester and is 16 bits wide. Subsequently, the DUT to tester interface is simplified.

Fig 15 and Fig 16 illustrate the utilization of the snapshot shift register for each clock cycle. The nomenclature that will be used is as follows:

• n: counter label number • k: snapshot cycle. First cycle out of reset all of the counter values are snapshot (shifted over) to the

shift up register bank. k is 0 for this cycle. The next snapshot of counter values is 400 clock cycles later and k will increment to 1.

• Xn,k is the counter-n value that was snapshot into the shift up register for snapshot cycle k.

As previously stated, coming out of reset, each counter has an initial value equal (Xn0) to the counter label number (n), e.g. Counter 0 has a reset value of 0 (X0,0=0) and counter 199 has a value of 199 (X199,0=199). As the circuit comes out of reset, the counter values are loaded into its corresponding register (within the shift-up register bank – see time τ in Fig 16). The counters continue to increment simultaneously as the shift registers shift counter values up every 4 clocks cycles – illustrated in Fig 16. The purpose of the shift-up is so each counter can reach shift register 0 (the output window to the tester). After all counters have been shifted up and loaded into the tester (τ+4N= once every 800 clock cycles), all of the counters are reloaded into the shift register bank.

As a summary, the key of the snapshot output scheme, is that the shift register array has now replaced a huge multiplexer. The benefits are as follows:

1. Counter upsets can easily be identifiable

All Counters

have shifted into

their Associated

Shift Registers

1

N-2N-1

0

2


2

N-1x

1

3


x

xx

N

x

All Counters

have shifted into

their Associated

Shift Registers

1

N-2N-1

0

2

t t+4 t+(N-‐ 1)*4 t+N*4N=200

24

2. Counters are incrementing and changing state every cycle. Hence maximum performance is able to be tested.

3. If a counter becomes upset, it will stay upset and it will eventually be captured during the snap shot period Counters are continuous and are not interrupted due an elaborate output scheme

4. Routing complexity is exclusive to just the counter array 5. The shift register architecture allows for high speed counter testing. A large multiplexer

creates long paths of combinatorial logic and significantly slows down system speed. The state space of the DUT should be deterministic and traversable. Pertaining to equation 5, for a

16 bit counter running at 2MHz and a shift up period of once every 4 clock cycles, it will take approximately 65ms for every state to be reached for all counters. At 1KHz, it will take roughly a minute. Radiation tests generally last for several minutes. Hence, counter states are considered fully traversed within each test run.

(5)

5.3.2 Counter I/O Interface and Expected Outputs Table 8: DUT1 WSR Outputs. Regarding ports with TMR extensions, only TMR0 is used

when testing LTMR or no TMR designs. TMR1 and TMR2 are only used during DTMR tests. I/O Name Bits Dir wrt

to DUT Description

PROASIC_Counter_CLK_TM0 1 OUT Counter shift Clock PROASIC_Counter_CLK_TM1 1 OUT Counter shift Clock PROASIC_Counter_CLK_TM2 1 OUT Counter shift Clock PROASIC_COUNTER_TMR0 16 OUT Counter output PROASIC_COUNTER_TMR1 16 OUT Counter output PROASIC_COUNTER_TMR2 16 OUT Counter output CLK 1 IN Clock to counter circuitry CLR 1 IN Reset to counter circuitry

The DUT receives a clock and a reset from the tester. The expected output (PROASIC_COUNTER) is purely an increment by 1 starting at value 0 as illustrated in Figure 17. The first PROASIC_COUNTER will pertain to counter 0, followed by counter 1, counter 2… up to counter 99. A new snap shot is performed and PROASIC_COUNTER will restart by outputting counter 0.

With respect to the separate counters, Counter (n) is output every 400 cycles (400 cycles= 1 snapshot cycle). Therefore the counter values that represent each counter will increment by 400 for each snapshot cycle.

msMHzfs

65110652 316

=×

=

25

Figure 17: Typical SEE Counter Outputs. Each output represents a value from a

different counter in the array. Counter selection is sequential, hence, the counter number and the counter values all increment by 1 each PROASIC_Counter_Clk cycle.

5.3.3 Counter Expected Upsets

• Bit or multiple bit upset: This example is illustrated in Figure 17. If a bit flips, it will stay flipped however, the counter will still increment.

• Broken counter: Counter stops counting and its value either stays constant or becomes complete noise

• Snap shot register: o A bit can get flipped while the counter value is in the snap shot register. In this case,

the expected counter value will only be upset for one cycle. o Snap shot register can either stop shifting- in this case the output values will remain

constant or become noise o Snap shot register can skip a cycle, in this case the counter values will be off the

number of skipped shift cycles from their expected values • Global routes: An upset can occur in the clock or reset circuitry

5.3.4 Summary of Counter Array Test Evaluations

The objectives of testing the counter array strings are to: o Determine the impact to the error cross section when implementing complex structures with

fanout. SET filtration and propagation will be heavily analyzed o Frequency effect evaluation

CLK

ProASIC_COUNTER

CLK

ProASIC_COUNTER_CLK

26

5.4 DSP Blocks

One DSP block consists of a 3-stage multiplier (using Microsemi’s multiplier core generator) and an accumulator. The DSP blocks are setup as FIR Filters:

There are 2 pairs of chains (cascaded DSP blocks see Figure 18). Each pair is referred to as a bank

and has identical DSP blocks. Bank 0 consists of 2 chains of 16 bit multiply + 32 bit (truncated) accumulate. Bank 1 consists of 2 chains of 8 bit multiply + 16 bit (truncated) accumulate.

The A, and B coefficients are set up prior to starting a test. In order to enhance the test state-space, the coefficients can take on a variety of settings.

5.4.1 Process for loading ‘A’ coefficients

The basic architecture for the A coefficient storage is based on a shift-register see Figure 18. This architecture consists of 16 (16 or 8 bit) registers configured as a shift-register. Thus, if we refer to the first stage of the chain as stage 0, then the A coefficient register for stage 0 feeds the input for the A coefficient register for stage 1. Similarly, the A coefficient register for stage 1 feeds the input for the A coefficient register for stage 2. Each register within this shift-register is updated on every clock cycle by the previous stage. We were able to select the type of coefficient we wanted through means of a 4-to-1 Multiplexor feeding the input of the stage 0 register.

5.4.2 Process for loading ‘B’ coefficients The basic architecture for the B coefficient storage was based on a set of independent

registers (see Figure 19). This architecture consists of 16 (16 or 8 bit) independent registers. Each B coefficient is selected by 16 independent 4-to-1 Multiplexors, all sharing the same select lines. The selection of the MUX output stays constant throughout a test. The selection is controlled by the LCDT and is set prior to the start of the test.

5.4.3 Process for loading ‘C’ coefficient

The process for storing the C coefficient consists of selecting the appropriate 41-bit

register input by means of a 4-to-1 Multiplexor, as shown in the following figure.

i

ii ABABCy −

=∑++=23

100

27

Figure 18:There are 16 DSP Blocks in one chain. There are two chains in one bank. The

two chains are compared within each bank perform BIST upset indication. This figure illustrates how the A values are shared within one bank and the muxing structured used to determine the A0 Value. It also demonstrates how A is delayed from stage to stage via a shift register to create A-i.

Counter Processing

TMR’d BIST

Compare

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

TMR’d BIST

Compare

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

Nonzero

Nonzero

Nonzero

Nonzero

~~~~

~~~~

DSP Processing

0 1 14 15

16 blocks

Bank0

Bank1

16Q

QSET

CLR

D

16Q

QSET

CLR

D

16Q

QSET

CLR

D

16

8Q

QSET

CLR

D

8Q

QSET

CLR

D

8Q

QSET

CLR

D

8

A

A shifts through Register Banks as a FIR inputThere are two Shift Chains for A

Each Shift Chain is Shared within a Bank

MUX

All 0's

All 1's

=1

Counter

2 bit Select from Tester

AMUX

All 0's

All 1's

=1

Counter

A-1 A-24 A-15


28

Figure 19: Schematic illustrated B (coefficient) generation. Each bank has 16 Muxes. All

Mux outputs are registered before it gets to the DSP block for timing purposes

TMR’d BIST

Compare

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

Nonzero

Nonzero

~~~~ DSP

Processing

Bank0

MUX

All 0's

All 1's

=1

Counter


B0MUX

All 0's

All 1's

=1

Counter

B1MUX

All 0's

All 1's

=1

Counter

B22MUX

All 0's

All 1's

=1

Counter

B23

Counter Processing

TMR’d BIST

Compare

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

Nonzero

Nonzero

~~~~

Bank1

MUX

All 0's

All 1's

=1

Counter

B0MUX

All 0's

All 1's

=1

Counter

B1MUX

All 0's

All 1's

=1

Counter

B22MUX

All 0's

All 1's

=1

Counter

B23

2 Banks of B (coefficient Muxes): Each are Register for Timing Purposes (Not Shown in Schematic)

29

Figure 20: C0 Generation.

BIST comparisons are performed due to limited I/O. Bank comparisons are independent from each other… i.e. only the two chains in bank 0 are compared against each other and the same is true for the two chains in bank1. Because the BIST circuitry is susceptible, it is triplicated before being sent to the tester as illustrated in Figure 21.

TMR’d BIST

Compare

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

Nonzero

NonzeroDSP

Processing

Bank0

MUX

All 0's

All 1's

=1

Counter


C0

Counter Processing

TMR’d BIST

Compare

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

DSP0=A*B+C

AB

C

Y DSP1=A*B+C

AB

C

Y DSP22=A*B+C

AB

C

Y DSP23=A*B+C

AB

C

Y

Nonzero

NonzeroBank1

MUX

All 0's

All 1's

=1

Counter

C0

30

Figure 21: Bank0 Schematic of TMR'd BIST Compares. All three triplicated compares

are sent to the tester for processing. The Figure illustrates Bank0... the same circuitry exists for Bank1

5.4.4 DSP I/O Interface and Expected Outputs Table 9 lists the outputs of the DSP DUT. All output directions listed are with respect to the DUT.

I/O interface is from the DUT to the Low Cost Digital Tester (LCDT). Table 9: DSP I/O

I/O Name Bits Dir wrt to DUT

Description

Bank0_CMP0 1 OUT Triplicated string 0 compare of Bank0 DSP chains






Non_Zero_0 1 OUT DSP chain 0 non-zero value indicator Non_Zero_1 1 OUT DSP chain 1 non-zero value indicator

TMR’d BIST

Compare

DSP15=A*B+C

AB

C

Y

DSP15=A*B+C

AB

C

Y

Nonzero

NonzeroBank0

Last Stage of DSP Chain Bank 0

DSP15=A*B+C

DSP15=A*B+C

Replicate0

Replicate1

Replicate2

Replicate0

Replicate1

Replicate2

Compare0

Compare1

Compare2

Triplicate DSP values before compares


Bank0

TMR’d BIST Compare

Details of TMR Compares

All Three Compares are sent to the tester

31

Non_Zero_2 1 OUT DSP chain 2 non-zero value indicator Non_Zero_3 1 OUT DSP chain 3 non-zero value indicator A Selection 2 IN Selects the input value to A B Selection 2 IN Selects the input value to the

Coefficients C Selection 2 IN Selects the input value to C CLK_DSP 1 IN Clock to all of the DSP circuitry CLR_DSP 1 IN Reset to all of the DSP circuitry

5.4.5 DSP Expected Upsets

DSP Block: If an upset occurs in one of the DSP blocks then the compare circuitry will reflect that an upset occurred. Normal upsets should only last for one clock cycle.

A,B, or C generation circuitry: If an upset occurs in the generation circuitry, because it is shared across DSP blocks, it will not show up as an upset (the comparison will be with two of the same things).

TMR circuitry: If an upset occurs in the TMR circuitry then 2 out of 3 will determine the actual state of the design.

Global routes: Bursts (upsets that last more than one clock cycle) can occur

5.4.6 Summary of DSP Test Evaluations The objectives of testing the DSP Blocks are to:

• Determine the susceptibility of complex structures such as DSP blocks • Frequency effect evaluation • Evaluate the new SET filtration scheme implemented by Actel and determine if it has

reduced the overall error rate of the device

6. LOW COST DIGITAL TESTER (LCDT) TEST VEHICLE The following sections describe the construction of the Low Cost Digital Tester (LCDT) including

communication interfaces with the DUT and user PCs. Figure 22 is a picture taken at the Texas A&M Heavy Ion Cyclotron Facility illustrating the LCDT connected to the DUT ready to be irradiated.

32

Figure 22: Picture of Low Cost Digital Tester (LCDT) connected to Device Under Test

(DUT) at Texas A&M Heavy Ion Facility

6.1 Architectural Overview The PROASIC3 controller/processor is instantiated as a sub component within LCDT. The test set-

up consists of a Mother Board (FPGA Based Controller/Processor) and a daughter board (containing DUT and its associated necessary circuitry). The socket within the DUT Daughter board accommodates the ProASIC3 devices. The objective of this DUT Controller/processor is to supply inputs to the ProASIC3 ACTEL Device and perform data processing on the outputs of the ProASIC3. The LCDT communicates with a user controlled PC. The user interface is LAB-VIEW. It will send user specified commands to the mother board and receive information from the mother board. Please see Documents: “LCDT” and “General Tester” for further information concerning the LCDT functionality. The test setup is shown in Figure 23.

33

Figure 23: System Level Tester Architecture. Two PCs are running a Labview GUI. One

PC is running a logic analyzer to have real time processing of the DUT WSR or Counter Array outputs. The PC connected to RS232(1) sends commands to the LCDT that set test parameters and starts test operations

6.1.1 I/O List and Definitions Interface tables were supplied in the previous sections for all of the designs. The same I/O for each

of the 2 DUTs are presented with respect to the LCDT in this section.

Table 10: I/O for Shift Register Tester. Input Name b

its Direc

tion Wrt to LCDT

Description

Laptop

LaptopLaptop

Logic Analyzer Connected to WSR or Counter OutputsLabview GUI connected to

WSR or Counter Processing

Labview GUI Connected to Memory Processing in HSDT. Commands are also sent (and echoed) to the HSDT

through this RS232 interface

RTAXDUT

CLK_SR_A

DUT INPUTSDUT Outputs

SHFT_CLK

Data Processing

HIGH SPEED DIGITALTESTER

DUT ControlsGeneral

Tester Hardware

CLKRESET

RS232(1)TX232(1)

TX232(2)

34

CLK 1 IN System clock of the LCDT from Board crystal

RESET 1 IN LCDT system reset from Power supply

RX232(1) 1 IN Serial receive input from Host PC. Used for PC to send commands to the LCDT

TX232(1) 1 OUT Serial transmission line to Host PC. Used to Echo commands and to send back either Shift Register or Counter Error Data

TX232(2) 1 OUT Serial transmission line to Host PC. Used to send back memory error data

PROASIC_SHFT_CLK0 1 IN Chain 0 shift Clock PROASIC_SHFT_CLK1 1 IN Chain 1 shift Clock PROASIC_SHFT_CLK2 1 IN Chain 2 shift Clock PROASIC_SHFT_CLK3 1 IN Chain 3 shift Clock PROASIC_SHFT_CLK4 1 IN Chain 4 shift Clock PROASIC_SHFT_CLK5 1 IN Chain 5 shift Clock

PROASIC_SHIFT_STRING0 4 IN 4-bit windowed output of chain 0






PROASIC_PATTERN 2 OUT Each chain gets bits from this vector:

The bits select which data input pattern (all 0’s, 1’s, or checker board). See Table 7 for selection details

PROASIC_EN0 1 OUT Sent to chain enable or disable chain 3

PROASIC_EN1 1 OUT Sent to chain enable or disable chain 4 and 5

35

CLK_SR0 1 OUT Clock to all of the WSR circuitry

CLR_SR0 1 OUT Reset to all of the WSR circuitry

Table 11: I/O For Counter Tester. Regarding ports with a TMR subscript:TMR1 and TMR2 ports are only used if DTMR designs are being tested. With LTMR or non-mitigated circuits only the TMR0 port is utilized.

Input Name bits

Direction Wrt to LCDT

Description

CLK 1 IN System clock of the LCDT from Board crystal

RESET 1 IN LCDT system reset from Power supply

RX232(1) 1 IN Serial receive input from Host PC. Used for PC to send commands to the LCDT

TX232(1) 1 OUT Serial transmission line to Host PC. Used to Echo commands and to send back either Shift Register or Counter Error Data

TX232(2) 1 OUT Serial transmission line to Host PC. Used to send back memory error data

PROASIC_COUNTER_CLK0_TMR0

1 IN Counter shift Clock





PROASIC_COUNTER_TMR0 16

IN 16 bit counter output



36



CLK_TMR0 1 OUT Clock to counter circuitry



CLR_TMR0 1 OUT Reset to counter circuitry



6.2 RS232 communication from the LCDT to the Host PC

All RS232 communication from the LCDT to the host PC is prefaced with a header. Information from the LCDT to the Host PC is one of the following listed in Table 12: an alive-timer, a command echo, or an Error Record.

Table 12: A list of the LCDT to Host PC RS232 Header bytes. Only the LCDT uses header

information. The host PC sends pure commands to the LCDT without headers. Header Description

00 FA F3 20 Alive Header No data bytes follow (i.e. only the header is sent from the LCDT to the PC)

00 FA F3 22 Command Echo. 4 data bytes follow that represent the command that was previously sent from the Host PC to the LCDT.

00 FA F3 21 Data Error Record: 23 bytes follow.

6.3 RS232 communication From the Host PC to the LCDT

Communication from the host PC to the LCDT does not contain a header. Information sent from the host PC to the LCDT are commands and are all 4 bytes in length The interface is controlled by a user GUI designed with LabView software.

6.3.1 User GUI

Commands are sent by typing specific values into Labview fields or controlling Labview on/off buttons listed on the screen. Figure 24 is the Labview Graphical User Interface (GUI) used to control and test the WSR designs. Figure 25 is the Labview GUI used to control and test the Counter designs.

37

Figure 24: WSR GUI. Communicates with the Tester via the RS232(1) and TX232 (1)

Interfaces. Commands are sent using this GUI. Command Echoes and WSR error reports are sent to this GUI from the Tester

38

Figure 25: Counter Labview Interface. Communicates with the Tester via the TX232 (1)

Interfaces. Counter error reports are sent to this GUI from the Tester.

The following section describes the commands sent from the Host PC to the LCDT.

6.3.2 User Interface and Command Control The User controls the tests via a LABVIEW interface running on a PC. The PC communicates

with the LCDT with a RS232 serial link. The format of communication is a command/Data 4 byte word.

Table 13 : Summary of Commands Used in RTAX-S Tester

Command #

Command D0

D1

D2

Description

01 Reset LCDT

n n n Resets RTAX-S

03 Reset N N n RESETS DSPs and

39

counter and DSP tests

Counters

04 Reset + Start of DSP + Counter

N N

n Sends a reset pulse and then starts the DSPs and counter array tests

05 Start WSR n n n Only run shift registers

06 Start All n n n Run all architectures

A0 WSR Clock Frequency

y n n D0 is the Clock frequency divider of 200mhz. The synthesized clock will be sent to the DUT WSRs as their system clock.

A1 Counter Array Clock Frequency

y n n D0 is the Clock frequency divider of 120 mhz. The synthesized clock will be sent to the DUT counter Arrays as their system clock.

A2 DSP Block y N N D0 is the Clock frequency divider of 120mhz. The synthesized clock will be sent to the DUT DSP Blocks as their system clock.

90 2 Bit WSR Data input Selection

y N N 00: all 0’s 01: all 1’s 10: Checkerboard 11: half rate

Checkerboard

91 2 Bit DSP A Selection

y N N 00: all 0’s 01: all 1’s 10: =1 11: counter

92 2 Bit DSP B Selection


40

93 2 Bit DSP C Selection


7. DUT TEST PROCEDURES

7.1 WSR Testing The objectives of testing are to determine:

• Bit upset rates • Frequency effects to SET capture rates • Data Pattern effects to SET capture rates • Global route effects • Susceptibility of DSP Blocks • Is there a difference in the RTAX4000D fabric versus the RTAX2000

In order to obtain WSR objectives, tests will be performed varying several parameters as listed in

Table 14. Table 15: WSR Test Parameter Variation

Frequency Effects

Data Pattern Effects

Global Routes (Clocks only)

General Bit Upsets

Architectural: Variation in combinatorial blocks between DFFs in WSR

x x

Frequency variation from test to test x x x Data pattern variation from test to

test x x x

LET variation x x x x Static Tests x x x

7.1.1 Dynamic: Evaluate susceptibility of WSR

1. Bias the device, turn on clocks and toggle reset 2. WSR operates as tester captures WSR outputs and compares with expected DUT output

pattern (verify no errors) 3. Irradiate DUT 4. During irradiation: Tester reads DUT and compares to expected value

o If error during read, then the LCDT records that an error has occurred and sends the data value with timestamp to the PC

o Goto 4 if not done with test else goto 5 5. Stop Beam 6. Reset Tester and DUT to prepare for next test

41

7.2 Counter Array Tests

7.2.1 Dynamic: Evaluate susceptibility of Counter DFF cells in biased-dynamic states

7. Bias the device, turn on clocks and toggle reset 8. Counter logic operates as tester captures counter outputs and compare with expected counter

pattern (verify no errors) 9. Irradiate DUT 10. During irradiation: Tester reads DUT and compares to expected value


o If not done with test Goto 4, else goto 5 11. Stop Beam 12. Reset Tester and DUT to prepare for next test

Table 16: Counter Array Test Parameter Variation Frequency

Effects Global Routes General Bit

Upsets Frequency variation from

test to test x x

LET variation x x x

7.3 DSP Tests

7.3.1 Dynamic: Evaluate susceptibility of DSP Blocks in biased-dynamic states

13. Bias the device, turn on clocks and toggle reset 14. DSP operates as tester captures counter outputs and compare with expected counter pattern

(verify no errors) 15. Irradiate DUT 16. During irradiation: Tester reads DUT and compares to expected value


o If not done with test Goto 4, else goto 5 17. Stop Beam 18. Reset Tester and DUT to prepare for next test

Table 17: Counter Array Test Parameter Variation Frequency

Effects Global Routes General Bit

Upsets Frequency variation from

test to test x x

LET variation x x x Variation of DSP

parameters (A, B, and C) x x x

7.4 Running a Full Test All three architectures will operate simultaneously during a heavy ion test run. Parameters for each

of the architectures must be set before the architectures are brought out of reset. The WSRs do not

42

have a reset; hence the tester must not activate the WSR clock signal until all parameters are set. The following are examples of test commands per run.

7.4.1 WSR Tests RunWSR: WSR (Checkerboard 200MHz); In this case all parameters are default (200MHz)

• command 1 x x x (reset tester) • command 5 x x x (Start all DUT architectures) • Start Beam and irradiate DUT • Stop Beam • goto step 1 for new test

Runb: WSR (all 1’s 200MHz); • command 1 x x x (reset memory control logic) • command 1 x x x (reset tester) • command 90 1 x x (all 1s WSR Data input) • command 5 x x x (Start all DUT architectures) • Start Beam and irradiate DUT • Stop Beam • goto step 1 for new test

Runc: WSR (All 0s 100MHz); • command 1 x x x (reset tester) • command A0 2 x x (Divide WSR 200MHz clock by 2=100MHz) • command 90 0 x x (all 0s WSR Data input) • Start Beam and irradiate DUT • Stop Beam • goto step 1 for new test

7.4.2 Counter Tests RunA: Counter Array (80MHz);

• command 1 x x x (reset tester) • command 3 x x x (Counter Arrays) • command 5 x x x (Start All DUTArchitectures) • Start Beam and irradiate DUT • Stop Beam • goto step 1 for new test

RunB: Counter Array (40MHz);

43

• command 1 x x x (reset tester) • command 3 x x x (reset DSP) • command A0 2 x x (Divide Counter 80MHz clock by 2=40MHz) • command 5 x x x (Start All DUTArchitectures) • Start Beam and irradiate DUT • Stop Beam • goto step 1 for new test

7.4.3 DSP Tests RunA: DSP (A=counter, B=counter, C=0, 80MHz). command 1 x x x (reset tester) command 3 x x x (reset DSP) command 93 0 x x (C=0 during AxB+C operations) A and B are default to counters) command 5 x x x (Start All DUTArchitectures) Start Beam and irradiate DUT Stop Beam goto step 1 for new test RunB: DSP (A=counter, B=counter, C=1, 40MHz). command 1 x x x (reset tester) command 3 x x x (reset DSP) command A0 2 x x (Divide DSP 80MHz clock by 2=40MHz) command 93 1 x x (C=1 during AxB+C operations) A and B are default to counters) command 5 x x x (Start All DUTArchitectures) Start Beam and irradiate DUT Stop Beam goto step 1 for new test 8. PROCESSING THE DUT OUTPUTS

The outputs of the DUT are fed to the tester for data processing. The objective of the data processing is to capture data from the DUT, compare to an expected value, and report to the host PC if there is an error. The DUT system clock and reset signals are generated in the LCDT.

8.1 WSR, Counter, H3FSM SHIFT_CLK Processing

Regarding the SHIFT_CLK, it is used to alert the tester that the DUTs are alive. The SHIFT_CLKs are always ¼ of the speed of the DUT system clock.

Due to the interface delays and device latencies and in order to consequently decouple the DUT to tester timing restrictions, the DUT SHIFT_CLK is considered asynchronous to the tester and is sampled using the LCDT system clock. Thus, the tester’s sampling clock will always be 4 times as fast as SHIFT_CLK. The SHFT_CLK is fed into a metastability filter and an edge detect. This process takes 1 to 2 clock cycles of the sampling clock (detection will be delayed by 1 to 2 sampling

44

clock cycles of the actual edge).

Figure 26: Shift_ClK Capture consists of a Metastability Filter and a Edge Detect

The SHIFT_CLK edge is expected to come at a frequency that is ¼ of the LCDT clock. If the edge is stopped, glitched, or missing, the event is reported to the host PC by the LCDT.

8.2 WSR Data Processing

Figure 27: Another look at a WSR string. The 4-bit window is the registers in the

illustration that are underneath the shift register string. The last 4-bits of the string are shifted

Q

QSET

CLR

DSynchronous

Signal

Reset from

clock tree

Q

QSET

CLR

D

Q

QSET

CLR

DShift Clock

Clock

Reset from

clock tree

Metastability Filter

Edge Detect

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

N levels of Inverters between DFF stages:

N = 0, 4, and 8Shift Register Chain

4-bit Window Output

45

into window, once every 4 clock cycles. In order to avoid metastable events due to an error in the output, data is registered twice before

evaluation. As illustrated in Figure 13, the four-bit WSR output window stays constant for all of the tested data patterns (all 0’s, all 1’s, and checkerboard). Therefore determining bit flips are simple… it’s merely checking for a change in data input (does the data from the current cycle(n) equal the data from the last cycle(n-1)?).

One must take caution when evaluating WSR LCDT SEU output records. Because of the

windowing structure, data output is expected to stay constant. Any disturbance to the output suggests an upset. Accordingly, the tester reports changes in data (i.e. the LCDT doesn’t simply report an upset – it reports changes in data output). This requires a record report when data changes from expected to corrupted, and then a record report when data changes from corrupted to expected. In other words, not every report from the tester suggests data is bad. The inclusion of the timestamp gives the user the ability to post process and to determine how long data is in error and if recovery is possible.

Table 18: Types of Errors with Detection and Reporting Scheme Error LCDT Detect Bit flip in shift register string Has the data changed from the previous

cycle? Global Route glitch: Clock, reset, or

enable There will be a burst of bad data in the

data string. A reset has a strict error signature because of how the string comes out of reset… e.g. the string is set to all 0’s for a certain number of cycles. A clock or enable glitch can cause a burst of noise data. All cases are eventually recoverable for a WSR.

Bit flip in window or I/O Has the data changed from the previous cycle and is only corrupt for less than the 4 clock cycle window.

Figure 28: WSR Error Record Data Fields. Each error record is prefaced with an error

header (00 FA F3 21) when being sent from the LCDT to the Host PC. Figure 28 demonstrates an error record that is sent from the LCDT to the user PC regarding a WSR

behavior. The relationship between the previously captured and currently captured WSR windowed values explains the error signatures and event occurrences within the WSR structure during testing.

CURRENTDATA VALUE

DATAPATTERN

ERROR FLAG

TIME STAMP

171:136

50

49:48

23:0

STATUS FLAGS

183:181

PREVIOUSDATA VALUE

47:24

46

Table 19 WSR Field Table. Yellow shading indicates fields that are generated from DUT intputs. White Fields are sourced from either tester settings or tester logic

Field # of Bits

Description

Current Value

28

Currently captured data (cycle N)

Previous Value

28

Previously captured data (cycle N-1)

Data Pattern

2 2 bit data pattern set by commands (00 or 01 or 10)

Error Flag

1 Not used

Freq 8 DUT frequency set by user command Error

Count 1

6 Unused

Time Stamp

32

Cycle counter. Must multiply by the DUT frequency to convert to time. Used to determine error burst sequences

Status 3 Indicates type of error record: “001” is a timeout – one of the shift clocks not

detected “011”Out of timeout – all shift clocks are recovered “000” Error or non-error – current value does not

equal previous value “010” Debug check – command was sent to check

value settings

Table 20: WSR Current Value and Previous Value Processing Previous Value and Current Value Indication Previous = good; and Current=bad WSR just reported an error Previous = bad; and Current=good WSR has recovered from error Previous= bad; and Current = bad WSR is in a burst of error Previous = exact inversion of

Current Either an enable was struck or there

was a shift clk hit (e.g. previous = hex 5 and current = hex A).

8.2.1 WSR SEU Cross Section Calculations

Generally, calculating the SEU Cross Section for WSR chains is a simple process. Count the number of upsets and divide by the reported particle fluence. The WSR cross section is then normalized to the number of bits within the chain that is being analyzed. When there is a burst of data, the total fluence must be adjusted because upsets are not being captured during the inoperable burst period. Hence, the number of particles that the device experienced during said period is subtracted off of the total.

47

𝝈𝑾𝑺𝑹_𝑺𝑬𝑼|𝑩𝑰𝑻 =#𝑼𝒑𝒔𝒆𝒕𝒔

#𝑷𝒂𝒓𝒕𝒊𝒄𝒍𝒆𝒔∗#𝑫𝑭𝑭𝒃𝒊𝒕𝒔𝒄𝒎𝟐

𝒃𝒊𝒕

(6)

8.3 Counter Array Data Processing The DUT output to the tester will increment once every 4 cycles. The increment is a continuous

sequence of counts. It is important to note the difference between the terms counter number and counter value. The counter number is a tag (or name) given to a counter. The counter value is the actual data that is stored in the counter (or the current state of the counter). The tester keeps a local copy of the expected counter number with respect to the incoming counter value in order to keep track of the integrity of each counter.

8.3.1 Counter Array Data Capture and compare

In order to avoid metastable events due to an error in the output, data is registered twice before evaluation. Both the data and the counter number are expected to increment every 4 cycles and will wrap around at its boundaries as listed in Table 21.

Table 21 Counter Value and Counter Number Wrap around Boundaries B

its Wrap Around Value

Counter values 16

216-1 (after 216-1 next value is 0)

Counter Number 8 199 (after 199 next value is 0) Regarding DUT value comparisons, any change in DUT output counter value must be an increment

of 1 from the previous DUT counter value. If not, then an error record is sent to the LCDT. One must take caution because this will require at least 2 records per upset. The first record will be the counter that is in upset and the next record will be the following counter that is not in upset. This is because neither of the two counters will be an increment of 1 apart.

Post processing of the output records will help to determine if the upset occurred within the snap shot register or in the counter. The events can be easily differentiated due to the fact that if a counter is upset, it will stay upset. However, an upset in the snapshot register will only be upset for 1 snapshot cycle.

Upsets in the counter shift_clk value (should be a signal that is ¼ the DUT clock) was described in Section 8.1.

8.3.2 Counter Array Error Record

A significant amount of post processing is expected to be performed on this data. Subsequently, the error record should contain enough information to comprehend and differentiate between events.

48

Figure 29: DUT2 Counter Array Error Record. Cycle n represents capture cycles.

Capture cycles are once every 4 LCDT tester clock cycles.

Table 22: Counter Array Error Record Fields: Yellow indicates Fields generated from DUT Inputs

Field Bits

Description

Data Cycle N 16

Current DUT output. Error: If it is not an increment of 1 from the

previous counter value and not an increment of 2 from the data value received cycle (n-2)

No error (recover from error): If it is not an increment of 1 from the previous value but is an increment of the data value received cycle (n-2)

Otherwise: DUT is in a burst of error Data Cycle N-1 1

6 Capture cycle n-1 DUT output (capture cycle

n-1 is actually 4 LCDT clock cycles from Data cycle N)

Data Cycle N-2 16

Capture cycle n-2 DUT output (capture cycle n-2 is actually 8 LCDT clock cycles from Data cycle N)

Data Cycle N-3 16

Capture cycle n-1 DUT output (capture cycle n-3 is actually 12 LCDT clock cycles from Data cycle N)

Counter Number 8 Tester local copy of expected counter number. (0 through 199)

Error Count Time Stamp 3

2

Status flags 3

8.3.3 Counter Array SEU Cross Section Calculations Because each of the DFFs within each counter has different logic feeding into its data pin, all 16

bits of the counter are analyzed separately. Hence, there are 16 different cross sections. As an example, given that there are 100 counters total, the Cross section for bit0 will be made up of upsets on the 100 different bit0 per counter. Counter Array SEU cross sections in this document will be reported as binned cross sections. Each bin is an average of 4 counter bit SEU cross sections. The first bin in the average cross section for bit0, bit1, bit2, and bit3. There are six bins in total because there are 16 bits in a counter. There are 400 bits within each bin.

DATA FORCYCLE n

TIME STAMP

177:146

23:0

STATUS FLAGS

183:181

DATA FORCYCLE n-1

47:24

ERRORCOUNT

145:130

DATA FORCYCLE n-2

71:48

DATA FORCYCLE n-3

95:72

COUNTERNUMBER

107:96

49

𝝈𝑪𝒐𝒖𝒏𝒕𝒆𝒓_𝑺𝑬𝑼|𝑩𝑰𝑻 =#𝑼𝒑𝒔𝒆𝒕𝒔

#𝑷𝒂𝒓𝒕𝒊𝒄𝒍𝒆𝒔∗#𝑫𝑭𝑭𝒃𝒊𝒕𝒔𝒄𝒎𝟐

𝒃𝒊𝒕

(7) 𝝈𝑪𝒐𝒖𝒏𝒕𝒆𝒓_𝑺𝑬𝑼|𝑩𝑰𝑵 =

#𝑼𝒑𝒔𝒆𝒕𝒔#𝑷𝒂𝒓𝒕𝒊𝒄𝒍𝒆𝒔∗𝟒𝟎𝟎

𝒄𝒎𝟐

𝒃𝒊𝒕

(8) 8.4 DSP Data Processing

The tester will monitor the 3 TMR compares for Bank0 and the 3 TMR compares for BANK1. The best 2 out of 3 will determine if one of the DSP blocks were upset. If all three values of the TMR circuit are not equal, that will also be reported (as a separate upset).

The non-zero flags will also be monitored in order to guarantee that the chains are not dead.

Figure 30: TMR'd Compares for DSP Bank0 8.4.1 DSP Block Error Record

A significant amount of post processing is expected to be performed on this data. Subsequently, the error record should contain enough information to comprehend and differentiate between events

TMR’d BIST

Compare

DSP23=A*B+C

AB

C

Y

DSP23=A*B+C

AB

C

Y

Nonzero

NonzeroBank0

Last Stage of DSP Chain 0 and Chain 1 in Bank 0

DSP23=A*B+C

DSP23=A*B+C

Replicate0

Replicate1

Replicate2

Replicate0

Replicate1

Replicate2

Compare0

Compare1

Compare2



Bank0

TMR’d BIST Compare

Details of TMR Compares

All Three Compares are sent to the tester

Chain 0

Chain 1

50

Figure 31: DSP Block Processing Error Record Table 23: DSP Block Error Record Field B

its Description

TMR Bank 0 3 3 Triplicated error indicators from the DUT Bank0 DSP Blocks

TMR Bank 1 3 3 Triplicated error indicators from the DUT Bank1 DSP Blocks

Nonzero 4 Indicates that the string has a non-zero value. When unexpected, an error record will be sent. Each of the 4 chains has a dedicated bit.

TMR Error Count 8 LCDT will increment this counter each time one of the TMR strings does not match during one clock cycle

Error Count 16

LCDT will increment this counter each time the TMR strings match but an upset has been detected

Time Stamp 32

Clock Cycle based time stamp (LCDT increments this value every clock cycle after reset is released)

8.4.2 DSP SEU Cross Section Calculations

Upsets (2+ BIST outputs=1 in one of the banks) are counted. Each Bank will have its own σSEU because the DSPs multiply and accumulate registers have different widths

𝝈𝑪𝒐𝒖𝒏𝒕𝒆𝒓_𝑺𝑬𝑼|𝑫𝑺𝑷𝑩𝒂𝒏𝒌𝟎 =#𝑼𝒑𝒔𝒆𝒕𝒔

#𝑷𝒂𝒓𝒕𝒊𝒄𝒍𝒆𝒔∗#𝑫𝑺𝑷𝑩𝒂𝒏𝒌𝟎𝒄𝒎𝟐

𝒃𝒊𝒕

(9) 𝝈𝑪𝒐𝒖𝒏𝒕𝒆𝒓_𝑺𝑬𝑼|𝑫𝑺𝑷𝑩𝒂𝒏𝒌𝟏 =

#𝑼𝒑𝒔𝒆𝒕𝒔#𝑷𝒂𝒓𝒕𝒊𝒄𝒍𝒆𝒔∗#𝑫𝑺𝑷𝑩𝒂𝒏𝒌𝟏

𝒄𝒎𝟐

𝒃𝒊𝒕

(10)

9. HEAVY ION TEST FACILITY AND TEST CONDITIONS

Facility: Texas A&M University Cyclotron Single Event Effects Test Facility, 15 MeV/amu tune). Flux: 1.0x105 to 2.0x107 particles/cm2/s

Time Stamp Error Count

TMR Bank1TMR Bank0

Nonzero values per chain

0123

Bits 6…0Bits 11...8Bits 71...40 Bits 39...24

TMR Error Count

Bits 23...16

TMR Values do not match

TMR Values match and

there’s an error

51

Fluence: All tests were run to 1 x 107 p/cm2 or until destructive or functional events occurred. Table 24: LET Table I

on Energy

(MEV/Nucleon) LET

(MeV*cm2/mg) 0° LET

(MeV*cm2/mg) 45 ° N

e 15 2,8 5.6

Ar

15 8.5 12.6

Cu

15 20.3

Kr

15 28.7 40.73

Xe

15 52.7 75.09

Test Conditions:

Test Temperature: Room Temperature Operating Frequency: 15 MHZ to 160MHZ Power Supply Voltage: 3.3v I/O and 1.5V Core.

The PROASIC3 devices were irradiated with Argon, Krypton, and Xenon beams at normal

incidence, 0, and 45 degrees (yielding effective LETs values listed in Table 24: LET Table) at the Texas A&M University Cyclotron Single Event Effects Test Facility. The following is a synopsis of ProASIC3 heavy ion testing.

• Each device is placed in the beam until a Single Event latch (SEL) event occurs; a significant number of upsets has occurred; or a fluence of 107 ions/cm2 is reached. The beam fluence is recorded for each radiation test.

• The PROASI3C devices are monitored for SEL under the above conditions by observing all of the voltage domains within the device during irradiation.

• An average cross section per bit is determined for a given LET as the number of fault events observed divided by the total fluence of the associated run at that LET.

10. HEAVY ION TEST RESULTS

10.1 Single Event Latchup (SEL) The following is a combination of the SEL results from phase I and phase II irradiation. The

PROASIC devices were monitored for Single Event latchup under the above conditions. Each part was placed in the beam until a Single Event latch (SEL) event occurred or 107 ions/cm2 – the beam fluence was then recorded. During our experiment, no Single Event latchup events occurred, yielding a threshold SEL LET for latchup of > 74.5 MeV•cm2/mg.

52

10.2 Configuration and Testing Difficulties A synopsis of Phase I initial test plan is as follows:

• Place a device within the socket on the DUT test board.

• Configure the device with the target design (e.g. No TMR WSRs, LTMR Counter, DTMR WSR, etc…). The target design is tested at various frequencies and data patterns.

• On completion of the tests, a new design is configured into the DUT and it is tested with various frequencies and data patterns.

• The reprogramming only occurs while the heavy ion beam is turned off. This procedure of testing and reprogramming (configuration management) is performed until the

device has acquired 10Mrad. At this point, a new DUT replaces the old in the DUT board socket and test procedure recommences.

10.2.1 Phase I First Test Trip 05/2010

During the first test trip, the initially planned procedure was not able to be successfully performed. Tests started at high LET values (Xe = 53 MeV*cm2/mg). At these LET values, we found that we would not be able to reprogram the devices after approximately 3 to 7 test runs (about 5Mrads). It is important to note that:

1. Configuring the device (reprogramming) only occurred when the beam was off and 2. The designs were fully operational prior to reprogramming. However, it is noted that a

reset was required (not a power on reset and not a power cycle) when the design’s functionality was completely disrupted during radiation exposure. Most importantly, the reset would flush the corrupted design – i.e.; full functionality was restored after a reset

3. The devices were fully functional until attempting to reconfigure them after about 5Mrads of high LET ion exposure. During reconfiguration, the device’s functionality is erased and consequently, the device is no longer usable.

Hence, it was only the reprogramming circuitry that would cause the device to fail. No devices annealed. This is assumed to be a destructive event that only occurs at relatively high LET values: > 40 MeVcm2/mg.

10.2.2 Phase I Second Test Trip 08/2010

Due to the difficulties first observed with reprogramming the device, the test procedures were changed. Each device had a dedicated design – no reprogramming was performed.

Only lower LET values were used during heavy ion testing (2.8MeV*cm2/mg – 28MeV*cm2/mg). Although no attempts to reprogram were performed on test-site, once the devices were returned to the REAG lab, reprogramming tests were performed. The objective was to further investigate potential programming damage after heavy-ion beam exposure. No upsets were observed.

10.2.3 Phase II Test Trip 08/2011 One of the goals of phase II was to recreate the reconfiguration issue in order to validate the

potentiality for destructive events. With a new set of devices, the reconfiguration destructive failure was observed once again for relatively high LET values: > 40 MeVcm2/mg.

53

10.2.4 Summary of Reprogramming issue

Device reprogramming failures were observed with LET>40MeV*cm2/mg. Attempts to re-program the dead devices have been performed to determine if there are annealing effects. It is interesting to note that, devices that will not reprogram with one particular design may reprogram with another (and be fully functional). However, this is not always the case, some devices are not able to be reprogrammed at all. This reprogramming effect was not observed at lower LET values.

It is suggested that due to this phenomena reconfiguring the ProASIC3 device while in flight not be performed.

10.3 No-TMR

The following pertains to WSR strings. As a reminder N indicates the number of combinatorial logic stages between shift register DFFs. Hence, WSR N=0 refers to shift register test structures with no combinatorial logic between DFFs; where WSR N>0 refers to shift register test structures with some number of combinatorial logic between DFFs.

No-TMR designs do not contain mitigation. Hence there is no logic masking; and as a result, the SEU cross section (σSEU) is based on DFFs, combinatorial logic, and global routes (SEFIs) as in equations (11) and (12).

𝑵𝒐𝑻𝑴𝑹: 𝑵 = 𝟎: 𝝈𝑾𝑺𝑹_𝑺𝑬𝑼|𝑵!𝟎(𝒇𝒔) ∝ 𝑷(𝒇𝒔)𝑫𝑭𝑭𝑺𝑬𝑼→𝑺𝑬𝑼+𝑷𝑺𝑬𝑭𝑰 (11)

𝑵𝒐 𝑻𝑴𝑹: 𝑵 > 𝟎:𝝈𝑾𝑺𝑹_𝑺𝑬𝑼|𝑵!𝟎(𝒇𝒔) ∝ 𝑷(𝒇𝒔)𝑫𝑭𝑭𝑺𝑬𝑼→𝑺𝑬𝑼+𝑷(𝒇𝒔)𝑺𝑬𝑻→𝑺𝑬𝑼 + 𝑷𝑺𝑬𝑭𝑰 (12)

10.3.1 Test Phase WSR σSEU comparisons

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

0 5 10 15 20 25 30 35

σSEU (cm

2 /bit)

LET MeV*cm2/mg

Phase I No TMR 100MHz WSR Strings: Checkerboard

N=8 BUFF

N=8 INV

N=0

N=0 (1)

54

Figure 32: Phase I: No-TMR Log-linear curves at 100MHz for N=0 and N=8 Strings. Checkerboard pattern was input to WSR strings

Figure 33: Phase II: No-TMR Log-linear curves at 100MHz for all phase II WSR Strings.

Checkerboard pattern was input to WSR strings

Figure 32 and Figure 33 are calculated σSEUs from phase I and phase II respectively. The σSEUs pertain to WSRs operating at 100MHz with checkerboard data input patterns. The σSEUs are statistically equivalent across test dates and devices. This is a validation point of SEU test procedure and evaluation confidence.

10.3.2 Data Pattern No-TMR WSR σSEU comparison Figure 34 illustrates the phase II WSRs operating at 100MHz with Zero data input pattern. The

0 pattern σSEUs are not significantly different than the checkerboard σSEUs. Figure 35 illustrates the phase II WSRs operating at 100MHz with a constant ones data input pattern. This data pattern also yields similar σSEUs. This analysis suggests that data pattern does not significantly affect the σSEU.

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

0 5 10 15 20 25 30 35 40 45

σSEU (cm

2 /bit)

LET MeVcm2/mg

Phase II No TMR 100MHz WSR Strings: Checkerboard

WSR16 WSR8 WSR4 WSR3 WSR2 WSR1 WSR0

55

Figure 34: Phase II: No-TMR Log-linear curves at 100MHz all phase II WSR Strings. A

constant zero-pattern was input to WSR strings

Figure 35: Phase II: No-TMR Log-linear curves at 100MHz all phase II WSR Strings. A

constant ones-pattern was input to WSR strings

10.3.3 Frequency and Combinatorial Logic Trends with No-TMR WSRs

Trends across frequency and amount of combinatorial logic are studied to determine cell

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

0 10 20 30 40 50

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)

No-‐TMR 100MHz : Zero Pa_ern

WSR16 WSR8 WSR4 WSR3 WSR2 WSR1 WSR0

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

0 5 10 15 20 25 30 35 40 45

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)

No-‐TMR 100MHz : Ones Pa_ern

WSR16

WSR8

WSR4

WSR3

WSR2

WSR1

WSR0

56

dominance and variable SEU effects. Regarding SEU effects, it has been shown that with non-mitigated synchronous designs (i.e., No-TMR), DFFs are the dominant source of system upsets versus upsets from combinatorial logic. Hence the following discussion pertaining to No-TMR synchronous designs focuses on the NASA REAG FPGA SEU Model term:

P(fs)DFFSEUèSEU ∝αP(fs)DFFSEU + βP(fs)DFFSEU(1-tdlyfs)

Prior to the evaluation of SEU effects on system, it is important to emphasize the difference between the DFF SEU terms αP(fs)DFFSEU and βP(fs)DFFSEU(1-tdlyfs):

• αP(fs)DFFSEU is the probability of DFF flipping its state (P(fs)DFFSEU) at the DFF’s clock edge. α is the percentage of DFFs flips that occur at the clock edge versus in between clock edges. SEUs associated with αP(fs)DFFSEU directly disrupt system state and are directly proportional to frequency; i.e., the probability that a DFF can flip its state at a clock edge increases as frequency increases.

• βP(fs)DFFSEU is the probability of DFF flipping its state (P(fs)DFFSEU) in between clock edges. β is the percentage of DFF flips that occur in between clock edges versus at the clock edge. SEUs associated with βP(fs)DFFSEU in a synchronous design are not guaranteed to cause system disruption because they are generated between clock edges. They will disrupt system state if they are captured by an EndPoint DFF (see Figure 5); and their capture rate is indirectly proportional to frequency; i.e., the probability that a DFF can flip its state in between clock edges and manifest into the next state will decrease as frequency increases.

Figure 36, Figure 37, and Figure 38 are WSR cross sections with checkerboard input pattern across operational frequency. The following is an analysis of frequency effects given the data in Figure 36, Figure 37, and Figure 38.

Frequency Independent Trends:

• As frequency increases, more DFFs can flip their state (i.e., P(fs)DFFSEU increases with frequency)

• DFFs are more dominant sources of upsets versus combinatorial logic in non-mitigated synchronous designs

Lower frequency Trends:

• A large percentage of StartPoint DFF flips can reach EndPoints (i.e., the term 1-τdlyfs approaches 1). Hence, in this frequency range the σSEU drop across frequency is not observable. (i.e., (1-τdlyfs) is insignificant in this frequency range)

• Subsequently, the dominant trend in this frequency range stems from P(fs)DFFSEU which increases with frequency: P(fs)DFFSEUèSEU ∝αP(fs)DFFSEU + βP(fs)DFFSEU

Higher frequency Trends:

• In this frequency range, a large percentage of StartPoint DFF flips can reach their EndPoints. Hence, although more DFFs are flipping their state (P(fs)DFFSEU increases as frequency increases) – they cannot reach the EndPoints and the σSEU drop across frequency is observable

57

• Subsequently, the dominant trend in this frequency range stems from 1-τdlyfs and σSEU decreases as frequency increases: P(fs)DFFSEUèSEU ∝αP(fs)DFFSEU + βP(fs)DFFSEU(1-τdlyfs)

o The trend is controlled by the relationship of τdly to fs; !"#$!"#$

; if the delay takes up most of the clock period, then very few StartPoint DFFs will not reach their endpoint

o Increasing combinatorial logic in the path increases τdly and subsequently decreases P(fs)DFFSEUèSEU. This is apparent at high frequencies. However, when the frequency is very slow relative to the τdly, the effects are insignificant (i.e., the inverse relationship to frequency is not observable for data paths with small τdlyfs term).

It is important to note that the trend is not simply dependent on frequency. It is dependent on the relationship of τdly to fs. When !"#$

!"#$ is small, the drop-off of P(fs)DFFSEUèSEU with respect to frequency

is insignificant. However when !"#$!"#$

is large regardless of frequency (e.g. a path with a large number of combinatorial logic stages between StartPoint DFF to EndPoint DFFs), P(fs)DFFSEUèSEU drop off is apparent.

8.00E-‐08

1.00E-‐07

1.20E-‐07

1.40E-‐07

1.60E-‐07

1.80E-‐07

2.00E-‐07

2.20E-‐07

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08 2.50E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)

LET = 28.8 No TMR -‐ checker pa_ern

WSR16

WSR8

WSR4

WSR0

58

Figure 36: σSEU over frequency for LET=28.8MeVcm2/mg. σSEU decreases as frequency increases. The addition of combinatorial logic within the path enhances the trend.

Figure 37: σSEU over frequency for LET=12.1 MeVcm2/mg. σSEU decreases as frequency

increases. The addition of combinatorial logic within the path enhances the trend.

1.80E-‐08

2.30E-‐08

2.80E-‐08

3.30E-‐08

3.80E-‐08

4.30E-‐08

4.80E-‐08

5.30E-‐08

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08 2.50E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)


WSR16

WSR8

WSR4

WSR0

7.00E-‐10

1.20E-‐09

1.70E-‐09

2.20E-‐09

2.70E-‐09

3.20E-‐09

3.70E-‐09

4.20E-‐09

4.70E-‐09

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08 2.50E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)


INV=16

INV=8

INV=0

59

Figure 38: σSEU over frequency for LET=2.8 MeVcm2/mg. σSEU decreases as frequency increases. The addition of combinatorial logic within the path enhances the trend.

Although data effects are not statistically significant regarding WSR σSEUs (see Figure 33

through Figure 35), a closer evaluation can assist in differentiating upsets from clock circuitry, reset circuitry, and data path.

Synchronous circuitry logistics: • Clock circuitry: In the WSR test structure, clock effects can either stem from a global clock tree

or from a clock transmission gate in a DFF. The transistors used in a clock tree versus a DFF transmission gate are distinctly different: clock trees require higher drive than internal DFF gates. A clock SET can cause:

o A DFF to sample its data path early. If data is still changing, metastability can occur. Constant data paths will not be affected (i.e., WSR constant logic 0 and WSR constant logic 1 SEU tests).

o If the clock glitch is too noisy, depending on the DFF structure, it can cause the DFF contents to become metastable

• Reset circuitry: In the WSR test structure, reset effects can either stem from a global clock tree, or from a clock transmission gate in a DFF. The implemented reset circuit for this test structure is asynchronous assert with synchronous de-assert. The transistors used in a global route versus a DFF transmission gate (such as a reset) are distinctly different: global routes require higher drive than internal DFF gates. A reset SET can cause:

o The DFF can be forced to its reset state • Data path circuitry: Cone of logic DFFs (StartPoints and EndPoints) with combinatorial logic

o DFF can flip its state o DFF can capture an SET from combinatorial logic

SEU testing WSRs with a constant logic-zero data input mostly isolate events to DFFs capturing data path circuitry (i.e., DFF flipping its state or a DFF capturing an incoming SET). Events from clock glitches or resets are insignificant. To be specific, resets events are insignificant for our WSR test structures with a constant zero pattern because every DFF’s reset state is also a logic zero.

Figure 39 through Figure 41 are σSEUs versus frequency pertaining to WSRs tested with a

constant zero data input. Figure 39 illustrates that the WSR chain σSEUs are relatively close in value. Figure 40 and Figure 41 zoom in on the WSR σSEUs. The following is an evaluation of WSRs with constant zero pattern inputs versus WSRs with checkerboard inputs:

• The inverse relationship to frequency at higher frequencies is not as significant with the constant zero pattern. Hence, in the case of a constant zero input pattern, more DFFs are flipping state at the clock edge (αP(fs)DFFSEU has more significance) as opposed to DFFs with checkerboard pattern inputs

• Constant zero input consistently produce lower σSEUs than the Checkerboard input.

60

Figure 39: Log-Linear Graph of WSR Constant Zero Data Pattern at

LET=20.3MeVcm2/mg. Demonstrates that there is not a large difference in the over σSEU between WSR string types

1.0E-‐10

1.0E-‐09

1.0E-‐08

1.0E-‐07

1.0E-‐06

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08 2.50E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)

LET = 20.3MeVcm2/mg No TMR -‐ zero pa_ern; Log-‐Linear

INV=16

INV=8

INV=4

INV=0

0.00E+00

1.00E-‐08

2.00E-‐08

3.00E-‐08

4.00E-‐08

5.00E-‐08

6.00E-‐08

7.00E-‐08

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)

LET = 20.3MeVcm2/mg No TMR -‐ zero pa_ern; Linear -‐ Linear

INV=16

INV=8

INV=4

INV=0

61

Figure 40: Linear-Linear Graph of WSR Constant Zero Data Pattern at LET=20.3MeVcm2/mg.

Figure 41: Linear-Linear Graph of WSR Constant Zero Data Pattern at

LET=2.8MeVcm2/mg. Figure 42 through Figure 44 illustrate WSR SEU testing with a constant logic-1 data input

pattern. The trends start to approach that of the checkerboard pattern; i.e., as the frequency and τdly increase, the σSEU decreases. Testing with the constant-logic-1 data input pattern masks clock upsets however reset upsets are now incorporated in the sSEU. The βP(fs)DFFSEU term increases significance with logic “1” or checkerboard input patterns versus a constant zero input pattern.

0.0E+00

2.0E-‐10

4.0E-‐10

6.0E-‐10

8.0E-‐10

1.0E-‐09

1.2E-‐09

1.4E-‐09

1.6E-‐09

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)

LET = 2.8MeVcm2/mg No TMR -‐ zero pa_ern

INV=16

INV=8

INV=4

INV=0

62

Figure 42: Linear-Linear Graph of WSR chains with a Constant Logic One Data Pattern

at LET=20.3MeVcm2/mg.


at LET=12.1MeVcm2/mg.

0.0E+00

2.0E-‐08

4.0E-‐08

6.0E-‐08

8.0E-‐08

1.0E-‐07

1.2E-‐07

1.4E-‐07

1.6E-‐07

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)

LET = 20.3MeVcm2/mg No TMR -‐ ones pa_ern

INV=16

INV=8

INV=4

INV=0

0.0E+00

1.0E-‐08

2.0E-‐08

3.0E-‐08

4.0E-‐08

5.0E-‐08

6.0E-‐08

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)


INV=16

INV=8

INV=4

INV=0

63


at LET=2.8MeVcm2/mg. 10.3.4 No-TMR Counters - SEU per Bit Analysis

SEU Cross sections are calculated in order to perform error rate predictions per orbit. As previously mentioned in the introduction, Shift-register strings have been the traditional FPGA design test-structure used for SEU analysis. It is well understood that implemented designs for space-flight projects are significantly more complex than shift registers strings. Hence, the purpose of testing counters is to investigate how design-complexity affects SEU Cross sections. Such a study assists in extrapolating SEU cross sections from tests circuits to target space-flight designs.

Figure 45 through Figure 49 illustrate counter σSEUs for Phase I (24-bit counters) and Phase II (16bit counters). Phase I graphs represent σSEUs per bit. However, instead of listing all 24bits, the bit σSEUs are binned. Each bin is the average of 4 σSEUs. Alternatively, Phase II graphs list σSEUs for each of the 16 bits of the counters. The comparison of Phase I of Phase II σSEUs shows that the separate test campaigns yield statistically equivalent results. The comparison is a validation point of the NASA Goddard REAG SEU test process.

0.0E+00

2.0E-‐10

4.0E-‐10

6.0E-‐10

8.0E-‐10

1.0E-‐09

1.2E-‐09

1.4E-‐09

1.6E-‐09

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)


INV=16

INV=8

INV=4

INV=0

64

Figure 45: Phase I: No TMR Counter bits. Bits are placed into bins of 4. Average Cross

Section per bit-bin is illustrated for LETs ranging from 2.8MeVcm2/mg to 8.6MeVcm2/mg

1.0E-‐11

1.0E-‐10

1.0E-‐09

1.0E-‐08

1.0E-‐07

1.0E-‐06

Bit 0-‐3 Bit 4-‐7 Bit 8-‐11 Bit 12-‐15 Bit 16-‐19 Bit 20-‐23

SEU Cross Sec^o

n (cm

2 /bit)

Counter-‐Bit Bins

80MHz No-‐TMR Counter Binned SEU Cross Sec^ons Low LETs

LET = 2.8MeV*cm2/mg

LET=3.9 MeV*cm2/mg

LET=8.6 MeV*cm2/mg

65

Figure 46: Phase I: No-TMR Counter σSEUs. Counters are 24bits each. Bits are placed

into bins of 4. Average σSEU per bit-bin is illustrated (i.e., each bin has 4 bits and the average of the 4bits is illustrated per bin). LETs ranging from 12.1MeVcm2/mg to 28.8MeVcm2/mg

1.0E-‐11

1.0E-‐10

1.0E-‐09

1.0E-‐08

1.0E-‐07

1.0E-‐06

Bit 0-‐3 Bit 4-‐7 Bit 8-‐11 Bit 12-‐15 Bit 16-‐19 Bit 20-‐23

SEU Cross Sec^o

n (cm

2 /bit)

Counter-‐Bits Bins

80MHz No TMR Counter Binned SEU Cross Sec^ons Higher LETs

12.16223664

20.3

28.70853532

66

Figure 47: Phase II: No-TMR Single-bit Counter σSEUs at 120MHz. Counters are 16bits

each. σSEUs are listed per bit. LETs ranging from 2.8MeVcm2/mg to 12.1MeVcm2/mg. Phase II σSEUs correlate with phase I testing.

2.8

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15

σSEU(cm

2 /bit)

Single Bit Upsets for No-‐TMR Counters @ 120MHz

2.8 3.9 8.6 12.1

67

Figure 48: No-TMR Single-bit Counter σSEUs at 80MHz. Counters are 16bits each. σSEUs

are listed per bit. LETs ranging from 2.8MeVcm2/mg to 12.1MeVcm2/mg. Phase II σSEUs correlate with phase I testing.

2.8

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05


σΣEU(cm

2 /bit)


2.8 3.9 8.6 12.1

68

Figure 49: No-TMR Single-bit Counter σSEUs at 1MHz. Counters are 16bits each. σSEUs

are listed per bit. LETs ranging from 2.8MeVcm2/mg to 12.1MeVcm2/mg. Phase II σSEUs correlate with phase I testing.

10.3.5 No-TMR Counters Frequency Analysis Figure 50 illustrates counter upsets across frequency. Counter upsets in this graph are not

differentiated by bit. In addition, no differentiation is made between whether the counter had a single bit or a multiple bit upset. Accordingly, the σSEU axis is per counter (not per bit). This is an evaluation of phase II counters that are 16-bits each. In order to map the σSEUs in Figure 50 into the other σSEUs provide in Figure 45 through Figure 49, the Figure 50 cross sections should be divided by 16.

Figure 50 suggests that the No-TMR counter σSEUs do not strongly decrease over frequency as they do with the WSR chains. However, the σSEUs at 1MHz have are the highest. The

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05


sSEU

(cm

2 /bit)


2.8 3.9 8.6 12.1

69

trend isn’t as strong because: τdly for most of the paths in the counter are << τclk. The reason being is that the longest path in the counter dictates the maximum frequency of operation. Subsequently, the other faster paths do not have a much of an influence on the (1- τdly fs) trend.

Figure 50: Phase II No-TMR Counter σSEUs across frequency. σSEUs are normalized per

counter and Counters are 16bits for Phase II. Counter σSEU trends do not appear to be frequency dependent due to the complexity of design topology and its opposing SEU effects.

10.3.6 No-TMR Counters - Multiple Bit versus Single Bit SEUs

Figure 51 illustrates the σSEUs for counter upsets that resulted in multiple bits in error versus counter upsets that resulted in single bits in error. Counter bit logic are physically space far apart (the essence of an FPGA), hence, multiple bit upsets are not due to charge sharing between logic nodes. Multiple bit upsets in the counters can occur in one of the following ways:

• DFF flips state between clock edges. The next state should change to a plus 1 from the upset state. However, due to τdly, some bits will change to the correct next state, however, some bits will not. The result appears as a multiple bit upset

• SETs that propagate to multiple nodes due to fanout. • Shared clock or reset node hits multiple DFFs

According to Figure 51, Single bit errors appear to be dominated by DFFs and hence follow the term P(fs)DFFSEUèSEU ∝αP(fs)DFFSEU + βP(fs)DFFSEU(1-τdlyfs) term.

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

0.00E+00 5.00E+07 1.00E+08 1.50E+08

σSEU(cm

2 /coun

ter)

Frequency (Hz)

No-‐TMR Counters -‐ Event Cross Sec^ons: Normalized per Counter

LET=2.8

LET=3.9

LET=8.6

LET=12.1

70

Figure 51: Multiple bit and Single Bit SEUs for No-TMR 16-bit Counters Figure 51 compares Single-bit events to Multiple-bit events per counter. Figure 52 through

Figure 54 illustrate multiple-bit events per-bit (counter error-bit distribution). Regarding Figure 51, although multiple-bit events are directly proportional to frequency, it is assumed that the trend is not fully attributed to SETs. The following explain the rational for multiple-bit frequency effects:

• No-TMR schemes have repeatedly shown that DFFs have dominant upsets such that captured SETs are insignificant

• With counters, some paths have much less logic than others (variable τdlys). Hence some StartPoints will have a higher probability of getting to their EndPoints than others. When a StartPoint upset can’t reach all of its EndPoints in a counter, a multiple-bit event will occur. This phenomenon is more significant at higher frequencies.

o Low Frequencies, most of the upsets are single-bit because a large percentage of StartPoint events can reach all of their EndPoints

o High Frequencies, multiple-bit events increase because a significant number of StartPoint events cannot reach all of their EndPoints

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

0 2 4 6 8 10 12 14

σSEU(cm

2 /coun

ter)

LET (MeVcm2/mg)

Mul^ple and Single Bit Upsets for ProASIC3 No-‐TMR 16-‐bit Counters

MBU 2kHz Single 2kHz MBU 1MHz Single 1MHz MBU 80MHz Single 80MHz MBU 120MHz Single 120MHz

71

Figure 52: No-TMR Multiple-bit Counter σSEUs at 120MHz. Counters are 16bits each.

σSEUs are listed per bit. LETs ranging from 2.8MeVcm2/mg to 12.1MeVcm2/mg.

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15

Cross S

ec^o

n (cm

2 /bit)

Mul^ple Bit Upsets for No-‐TMR Counters @ 120MHz

2.8 3.9 8.6 12.1

72





1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05 Cross S

ec^o

n (cm

2 /bit)


2.8

3.9

8.6

12.1

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

Cross S

ec^o

n (cm

2 /bit)


2.8

3.9

8.6

12.1

73

10.3.7 No-TMR DSP Blocks The importance of this section is to illustrate an additional evaluation point of complex test

structures. Figure 55 and Figure 56 illustrates the DSP cross sections normalized to bits per DSP block. The figures show that the DSP bit upsets are statistically equal to the counter bit upsets. This implies that for complex design topologies, the DSP or counter cross sections per bit can be extrapolated to predict upset rates for a design. More importantly, when the counter and DSP σSEUs are compared to σSEUs from a simple topology such as a WSR string, the difference in σSEUs is within a decade.

Figure 55: Comparison of DSP, Counters and WSR strings at LET=12.1MeVcm2/mg

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)

LET = 12.1 No TMR -‐ checker pa_ern; Counters; DSP Blocks

INV=16 INV=8 INV=0 DSP16 Counter No-‐TMR

74

Figure 56: Comparison of DSP, Counters and WSR strings at LET=8.6MeVcm2/mg

10.4 LTMR

10.4.1 LTMR Shift Registers and LET and Input Data Pattern

The LTMR mitigation strategy triplicates every DFF and places a majority voter after the triplication. This scheme forces the Plogic term for the DFFs in Equation (4) equal to 0. Consequently, SEUs in an LTMR synchronous design stem from:

• Clock global routes

• Reset global routes

• Captured data path SETs

Figure 57 through Figure 68 are graphs of LTMR-WSR σSEUs across LET values ranging from 2.8MeVcm2/mg to 40.7MeVcm2/mg. The figures illustrate :

• As Frequency decreases, the LET threshold (LETTH) increases. This is as expected because DFF upsets are masked. Hence, upsets stem from SETs. Low LETs produce small SETs. In addition, small SETs have a lower probability of being captured as frequency is decreased (τwidthfs relationship).

• As the amount of combinatorial logic is reduced, the LETTH increases. Less combinatorial logic in a path has a lower probability of SET generation.

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

Cross S

ec^o

n (cm

2 /bit)

Frequency (Hz)

LET = 8.6 No TMR -‐ zero pa_ern

INV=16

INV=8

INV=0

DSP16

Counter No-‐TMR

75

Figure 57: WSR 180MHz Checkerboard Pattern across LET. σSEUs for WSR0 (INV=0)

and WSR2 (INV=2)are represented.

Figure 58: WSR 100MHz Checkerboard Pattern across LET. σSEUs for WSR0 (INV=0),

WSR4 (INV=4), and WSR8 (INV=8) are represented.

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)

LTMR WSR 180MHz : Checker Pa_ern

INV=2

INV=0

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)


INV=8

INV=4

INV=0

76


WSR4 (INV=4), WSR8 (INV=8), and WSR16 (INV=16) are represented.



1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)


INV=16

INV=8

INV=4

INV=0

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)


INV=16

INV=8

INV=4

INV=0

77

Figure 61: WSR 180MHz Constant Ones Pattern across LET. σSEUs for WSR0 (INV=0),

and WSR2 (INV=2) are represented.


WSR4 (INV=4), and WSR8 (INV=8) are represented.

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)

LTMR WSR 180MHz : Constant Ones Pa_ern

INV=2

INV=0

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)

LTMR WSR 100MHz : Constant Ones Pa_ern

INV=8

INV=4

INV=0

78


WSR4 (INV=4), and WSR8 (INV=8), and WSR16 (INV=16) are represented.


WSR4 (INV=4), and WSR8 (INV=8), and WSR16 (INV=16) are represented.

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

Eff. LET (MeVcm2/mg)

LTMR 50MHz : Ones Pa_ern

INV=16

INV=8

INV=4

INV=0

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)

LTMR WSR 1MHz : Ones Pa_ern

INV=16

INV=8

INV=4

INV=0

79

Figure 65: WSR 50MHz Constant Zeros Pattern across LET. σSEUs for WSR0 (INV=0)

and WSR2 (INV=2) are represented.

Figure 66: WSR 100MHz Constant Zeros Pattern across LET. σSEUs for WSR0 (INV=0)

,WSR4 (INV=4), and WSR8 (INV=8) are represented.

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)

LTMR WSR 180MHz : Zero Pa_ern

INV=2

INV=0

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)


INV=8

INV=4

INV=0

80

Figure 67: WSR 50MHz Constant Zeros Pattern across LET. σSEUs for WSR0 (INV=0),


Figure 68: WSR 50MHz Constant Zeros Pattern across LET. σSEUs for WSR0 (INV=0),

WSR4 (INV=4), WSR8 (INV=8), and WSR16 (INV=16) are represented

10.4.2 LTMR Shift Registers – Frequency and Combinatorial Logic Effects

As previously mentioned, DFFs in an LTMR scheme do not contribute to the overall σSEU because they are masked and corrected via the triplication and voting circuitry. As a result, the dominant term in the P(fs)functionallogic portion of the SEU Model is:

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)


INV=16

INV=8

INV=4

INV=0

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.8 3.9 8.6 12.1 20.3 28.8 40.7

Cross S

ec^o

n (cm

2 /bit)

LET (MeVcm2/mg)

LTMR WSR 1MHz : Constant Zero Pa_ern

INV=16

INV=8

INV=4

INV=0

81

P(fs)functionallogic ∝PgenPpropPlogicτwidthfs (for each combinatorial logic cell within the cone of logic of an EndPoint)

This implies that LTMR circuits are directly proportional to frequency and directly proportional to the amount of combinatorial logic within an EndPoint’s cone of logic. This is illustrated in Figure 69 through Figure 72.

Figure 69: LTMR WSR with checkerboard input pattern. σSEU across frequency at

LET=20.3MeVcm2/mg. In agreement with Eq (4), σSEUs are directly proportional to frequency and amount of combinatorial logic in the EndPoint’s cone of logic

1.0E-‐09

6.0E-‐09

1.1E-‐08

1.6E-‐08

2.1E-‐08

2.6E-‐08

3.1E-‐08

3.6E-‐08

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

σSEU(cm

2 /bit)

Frequency

LTMR Checkerboard Pa_ern LET=20.3MeVcm2/mg

WSR8

WSR16

WSR0

82

Figure 70: LTMR WSR with constant logic-1 input pattern. σSEU across frequency at


0.0E+00

5.0E-‐09

1.0E-‐08

1.5E-‐08

2.0E-‐08

2.5E-‐08

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

σSEU(cm

2 /bit)

Frequency

LTMR Constant 1 Pa_ern LET=20.3MeVcm2/mg

WSR8

WSR16

WSR0

83

Figure 71: LTMR WSR with constant zero input pattern. σSEU across frequency at


Figure 72: LTMR WSR with checkerboard input pattern. σSEU across frequency at


0.0E+00

5.0E-‐09

1.0E-‐08

1.5E-‐08

2.0E-‐08

2.5E-‐08

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

σSEU(cm

2 /bit)

Frequency

LTMR Constant Zero Pa_ern LET=20.3MeVcm2/mg

WSR8

WSR16

WSR0

0.0E+00

5.0E-‐10

1.0E-‐09

1.5E-‐09

2.0E-‐09

2.5E-‐09

3.0E-‐09

3.5E-‐09

4.0E-‐09

0.00E+00 5.00E+07 1.00E+08 1.50E+08 2.00E+08

σSEU(cm

2 /bit)

Frequency

LTMR Checkerboard Pa_ern LET=8.6MeVcm2/mg

WSR8

WSR16

WSR0

84

10.4.3 Contrast between No-TMR and LTMR σSEUs

Figure 73: No-TMR and LTMR σSEUs are illustrated for similar WSR strings. A

comparison of the frequency and combinatorial logic effects for No-TMR versus LTMR show opposing trends

Figure 73 illustrates the opposing trends of No-TMR versus LTMR as discussed in the previous

sections.

10.4.4 LTMR Counters Regarding Figure 74, LTMR counters have a slight dependency on frequency because the upsets

stem from SETs. However, the trend across frequency isn’t as strong as WSR strings because of the inherent logical masking (Plogic) of counters.

85

Figure 74: LTMR counters – frequency effects per LET. Upsets at LETs <

8.6MeVcm2/mg are not observed until testing at higher frequencies (80MHz in this case). σSEUs are per counter. Normalize (divide by 16) for σSEUs per bit.. Single bit upsets are not differentiated from multiple bit upsets. 80MHz upsets at 2.8MeVcm2/mg and 3.9MeVcm2/mg are multiple bit upsets.

Figure 75 and Figure 76 illustrate the Single-bit σSEUs. σSEUs are provided for each bit of the 16-bit counter. As previously mentioned, the Single-bit appear to have a slight dependence on frequency. In addition, the higher-order bits tend to have a larger concentration of error events. This is due to the fact that the upsets are due to combinatorial logic SETs. The higher order bits have larger cones of logic which contain a larger number of combinatorial logic gates – hence more combinatorial logic equates to higher σSEUs when DFFs are masked (this is an LTMR scheme).

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.00E+03 1.00E+06 8.00E+07

σSEU(cm

2 /coun

ter)

Frequency (Hz)

LTMR Counters -‐ Event Cross Sec^ons

LET=2.8

LET=3.9

LET=8.6

LET=12.1

LET=28.8

LET=40.7

86

Figure 75: Single bit upset bit distribution at 80MHz

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Cross S

ec^o

n (cm

2 /bit)

Single Bit Upsets for LTMR Counters @ 80MHz

2.8

3.9

8.6

12.1

28.8

40.7

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Cross S

ec^o

n (cm

2 /bit)

Single Bit Upsets for LTMR Counters @ 1MHz

2.8

3.9

8.6

12.1

28.8

40.7

87

Figure 76: Single bit upset bit distribution at 1MHz Figure 77 illustrates that while the single-bit counter events are frequency dependent (directly

proportional), frequency dependency for multiple bit upsets is not as apparent. However, LETTH is higher for multiple events at 80MHz versus 1MHz. At higher LETs, global routes start to contribute more to multiple-bit counter upsets. In the LTMR scheme, multiple bit upsets at lower LETs have a low probability of occurring.. This is explained by the following:

• All upsets in the LTMR scheme stem from combinatorial logic. • Each DFF is actually three DFFs (i.e., they are triplicated). Hence for a single bit upset each

SET must travel through three separate routes and be active at two out of the three EndPoint DFFs during their clock edge. Each path will have a different delay (τdly).

• For an SET to affect multiple DFFs, it must travel down greater than 6 separate paths. Each path will have a different delay (τdly).

• The problem then becomes, the probability for a transient to travel down multiple paths with variable delays and be active at the multiple EndPoint DFFs during the clock edge

Figure 77: Comparison of Single-bit upsets in LTMR counters versus multiple-bit upsets

in LTMR counters. σSEUs are provided for a variety of frequencies across a range of LET values (2.8MeVcm2/mg to 40MeVcm2/mg). σSEUs are per counter. Normalize (divide by 16) for σSEUs per bit.

1.0E-‐10

1.0E-‐09

1.0E-‐08

1.0E-‐07

1.0E-‐06

0 5 10 15 20 25 30 35 40 45

σSEU(cm

2 /coun

ter)

LET (MeVcm2/mg)

Mul^ple vs. Single Bit Upsets for ProASIC3 LTMR Counters

MBU 2kHz Single 2Khz MBU 1MHz Single 1MHz MBU 80MHz Single 80MHz

88

Figure 78: Multiple-bit upsets for LTMR counters at 80MHz. Bit Distribution

Figure 79: Multiple bit upsets for LTMR counters at 1MHz. Bit Distribution

10.5 DTMR Counter σSEUs Figure 80 and Figure 81 illustrate ProASIC3 DTMR counter σSEUs. Although the upsets are

listed as single bit events, because of the mitigation, the upsets are actually generated in the global routes. The probability of upset is relatively low. However, the mitigation implementation will be

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05 Cross S

ec^o

n (cm

2 /bit)

Mul^ple Bit Upsets for LTMR Counters @ 80MHz

2.8 3.9 8.6 12.1 28.8 40.7

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Bit8

Bit9

Bit10

Bit11

Bit12

Bit13

Bit14

Bit15

Cross S

ec^o

n (cm

2 /bit)

Mul^ple Bit Upsets for LTMR Counters @ 1MHz

2.8 3.9 8.6 12.1 28.8 40.7

89

further investigated to validate triplication and voter insertion.

Figure 80: Single Bit Counter upsets. DTMR Bit distribution for 16-bit Counters at

80MHz

Figure 81: Single Bit Counter upsets. DTMR Bit distribution for 16-bit Counters at 1MHz

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Cross S

ec^o

n (cm

2 /bit)

Single Bit Upsets for DTMR Counters @ 80MHz

3.9 8.6 20.3 28.7 40.7

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Cross S

ec^o

n (cm

2 /bit)

Single Bit Upsets for DTMR Counters @ 1MHz

3.9 8.6 12.1 28.7 40.7

90

Figure 82: DTMR Counter upsets. Single bit upsets and multiple bit upsets are not

differentiated. σSEUs are per counter. Normalize (divide by 16) for σSEUs per bit. Figure 83 shows the σSEU relationships between single-bit upsets and multiple-bit upsets in the

DTMR counters. As the mitigation strength grows (e.g. DTMR has a stronger mitigation strength than LTMR), the differentiation between single bit s σSEUs and multiple σSEUs is reduced:

• No-TMR: Single bit σSEUs are about two decades greater than multiple bit σSEUs • LTMR: Single bit σSEUs are about one decade greater than multiple bit σSEUs • DTMR: Single bit σSEUs are less than a decade greater than multiple bit σSEUs

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

2.00E+03 1.00E+06 8.00E+07

Cross S

ec^o

n (cm

2 /coun

ter)

Frequency (Hz)

DTMR Counters -‐ Event Cross Sec^ons

LET=8.6

LET=12.1

LET=20.3

LET=28.7

LET=40.7

91

Figure 83: Multiple vs. Single Bit upsets in DTMR counters.

10.6 σSEU Counter Comparisons: ProASIC3 versus RTAXs Figure 84 illustrates σSEUs for a variety of counters. All cross-sections in Figure 84 are normalized

by bit. It is best to compare counters σSEUs that are at the same LET with similar frequencies. The RTAXs and ProASIC3 counters were not tested at exactly the same frequencies for all cases. Subsequently, a variety of σSEUS at different frequencies are shown.

• Microsemi ProASIC3 No-TMR: This counter contains no mitigation. σSEUs at 120MHz and 80MHz are graphed. As previously mentioned, No-TMR counters do not appear to be frequency dependent.

• Microsemi ProASIC3 LTMR: This counter has triplicated DFFs with a voter placed after the triplication. All upsets that can affect the circuit design are either from SETs in the data-path or global routes. Figure 84 shows ProASIC3 counters σSEUs at 80MHz. LTMR counters do have frequency dependency.

• Microsemi RTAXs: The RTAXs FPGA has embedded LTMR and hardened global routes. Regarding counter designs, RTAXs counter σSEUs are slightly lower than ProASIC3 LTMR counters.

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

0 5 10 15 20 25 30 35 40 45

Cross S

ec^o

n (cm

2 /coun

ter)

LET (MeVcm2/mg)

Mul^ple vs. Single Bit Upsets for ProASIC3 DTMR Counters

MBU 2KHz Single 2kHz MBU 1MHz Single 1MHz MBU 80MHz Single 80MHz

92

Figure 84: Comparison of Counters Microsemi ProASIC3 and RTAXs

10.7 ProASIC3 Burst σSEUs The LCDT is able to capture every cycle of data, determine if it is in error, time stamp the upset,

and send it to the host PC upon error. Bursts are defined as consecutive cycles of upsets. They generally occur when a clock or reset global route incurs an SET and that SET disrupts several DFFs.

Figure 85 through Figure 87 illustrate burst cross sections for counter arrays. No-TMR circuits appear to be more susceptible than LTMR and DTMR. This is because LTMR and DTMR have mitigation; hence global upsets that occur near DFFs (i.e., at the lower leafs of the global net tree) have the opportunity to be masked by the mitigation circuitry. As a result, DTMR has a higher LETTH for bursts versus all of the other mitigation schemes (i.e., No-TMR and LTMR).

Regarding Figure 86 and Figure 87, burst σSEUs are similar for LTMR and DTMR designs specifically at higher LETs. Most of the bursts at the higher LET values were resets and they occur relatively high in the reset global route tree.

At lower LETs, LTMR burst σSEUs are higher than DTMR burst σSEUs. This suggests that a large portion of the global route SETs that propagate to the data-path occur in transistors close to the DFFs (i.e., SETs that occur high in the global tree are less likely to propagate to the data-path DFFs). This is a reasonable assumption because global routes have large fan-out and subsequently high capacitance nets. SETs are less likely to propagate through highly capacitive circuitry.

1.00E-‐12

1.00E-‐11

1.00E-‐10

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

0 10 20 30 40 50 60 70 80

σSEU(cm

2 /bit)

LET (MeVcm2/mg)

Counter Comparison between ProASIC3 and RTAX Technologies

ProASIC LTMR Counters 80MHz

ProASIC No-‐TMR Counters 80MHz

RTAX Counters 60MHz

RTAX Counters 120MHz

ProASIC No-‐TMR Counters 120MHz

93

Figure 85: No-TMR bursts with Phase II Counters

Figure 86: LTMR bursts with Phase II Counters

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

1.00E-‐04

2000 1000000 80000000 120000000

Cross S

ecô

n (cm

2 /de

vice

Frequency (Hz)

No-‐TMR Counter Burst Cross Secôns

LET=2.8 LET=3.9 LET=8.6 LET=12.1

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

1.00E-‐04

2000 1000000 80000000

Cross S

ecô

n (cm

2 )/device

Frequency (Hz)

LTMR Counter Burst Cross Secôns

LET=3.9 LET=8.6 LET=12.1 LET=28.8 LET=40.7

94

Figure 87: DTMR bursts with Phase II Counters 11. SUMMARY A variety of test structures were evaluated while being exposed to heavy ions. The test

structures and their error responses are listed in Table 25 through Table 28. In these tables, σSEULETTH represents the error cross section calculated at the listed LETTH.

The global routes are not hardened in the ProASIC3 device. The effects of not hardening the global routes are apparent for all mitigation strategies tested (No-TMR, LTMR, and DTMR). GTMR is the strategy that mitigates against global route SETs. However, because there is too much skew between the ProASIC3 clock trees, GTMR is infeasible to implement in this device. It is noted that as the mitigation strength increases, the global route upsets become less significant for LET<30MeVcm2/mg. As LET increases, the global route SETs increase; and subsequently, the LTMR and DTMR error cross sections start to approach one another.

Shift registers have traditionally been the preferred test structure for radiation testing. Due to their linear topology, shift registers have no logical masking of SEUs. Subsequently, shift registers are an efficient means for evaluating DFF (SEU), SEU/SET error responses. As an example, shift registers are a good method for testing the mitigation strength of hardened DFFs and the effects of varying the amount of simple combinatorial logic gates. Alternatively, because of their linear topology, shift registers tend not to accurately characterize error responses for real (more complex) designs. It is important to note, that in systems where DFF upsets are significant (e.g. they’re not logically masked from the system), testing designs with several StartPoints per EndPoint is paramount. In other words, systems are cones of logic (see Figure 4 and Figure 5) and should be evaluated as such.

In order to evaluate more complex design topologies, counters and DSPs were tested. Both design topologies contain cones of logic that consist of multiple StartPoint DFFs per EndPoint. Such topologies increase the σSEU; however at the same time the inherent logic masking decreases

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

1.00E-‐04

2000 1000000 80000000

Cross S

ec^o

n (cm

2 /de

vice)

Frequency (Hz)

DTMR Counter Burst Cross Sec^ons

LET=8.6

LET=12.1

LET=20.3

LET=28.7

LET=40.7

95

σSEU. It is important to note that the overall σSEU appears to increase with these complex structures (see Figure 55 and Figure 56), the opposing effects appear to negate other well-known effects such as frequency.

More importantly, after normalizing per bit, the opposing effects of the more complex structures resulted in σSEUs that were statistically equivalent. This suggests that the normalized σSEUs of complex structures can be extrapolated for error prediction of actual designs.

Table 25: WSR SEU Error Response W

SR LETTH Frequen

cy Effect Dominant

Element N

o-TMR 2.8MeVcm2/mg σSEULETTH=2.5e-9cm2/bit

Inversely

Proportional

DFFs with low to medium LET values; global routes at high LETs

LTMR

≈8.6MeVcm2/mg σSEULETTH=1.56e-11cm2/bit

Directly proportional

Combinatorial logic; global routes at high LETs

Table 26: Counter SEU Error Response C

ounters LETTH Frequen

cy Effect Dominant

Element N

o-TMR <2.8MeVcm2/mg σSEULETTH=1.5e-8cm2/bit

Not significant


LTMR

≈2.8MeVcm2/mg σSEULETTH=1.5e-11cm2/bit


Combinatorial logic with low to medium LET values; global routes at high LETs

DTMR

≈12.1MeVcm2/mg; σSEULETTH=6e-11cm2/bit

Not significant

Global routes

Table 27: Burst (Global Routes) SEU Error Response B

ursts LETTH Frequen

cy Effect Dominant

Element N

o-TMR <2.8MeVcm2/mg; σSEULETTH=5e-8cm2/device

Not significant

DFFs with low to medium LET

96

values; global routes at high LETs

LTMR

<3.9MeVcm2/mg; σSEULETTH=5e-8cm2/device


Combinatorial logic with low to medium LET values; global routes at high LETs

DTMR

<8.6MeVcm2/mg; σSEULETTH=1e-7cm2/device

Not significant

Global routes

Table 28: DSP SEU Error Response D

SP LETTH Frequen

cy Effect Dominant

Element N

o-TMR <2.8MeVcm2/mg σSEULETTH=1.5e-8cm2/bit

Not significant


12. APPENDIX 1:

[1] Actel Datasheet: “PROASIC/SL RadTolerant FPGAs” http://www.actel.com/documents/PROASIC_DS.pdf, V5.2, October 2007.

[2] M. Berg “An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel PROASIC Family Field Programmable Gate Arrays,” IEEE Trans. Nucl. Sci., vol. 53, n° 6, Dec. 2006.

[3] M. Berg “Trading Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) Considerations for System Insertion”, NSREC Short Course, Quebec City, CN, July 2009

[4] M. Berg et. al “Incorporating Probability Models of Complex Test Structures to Perform Technology Independent FPGA Single Event Upset Analysis, NSREC Poster, Las Vegas, ‘NV, July 2011

[5] Mentor Graphics Precision Documentation: https://supportnet.mentor.com/docs/201009057/docs/pdfdocs/precisionRTL_users.pdfhttps://supportnet.mentor.com/docs/201009057/docs/pdfdocs/precisionRTL_users.pdf (see chapter 7)