FEATURES

16 “top gros” digital inputs

Inputs polarization provided on the board

Level adaptation

Adjustable thresholds

Comparison sign selectable

Digital interface to bus board

Product developped for harsh environment

DESCRIPTION

The ACTG board performs acquisition of 16 pseudo digital parameters.

It is part of remote acquisition boards designed by ADAS.

It features :

input polarization, level adaptation, comparison, selectable comparison sign, interface to bus board.

Threshold adjustments, resistors, polarization and selectable levels and edges make this board a highly versatile product for the acquisition of digital parameters.

9 rue Georges Besse – BP 47 – 78330 FONTENAY LE FLEURY – FRANCE

Tél.:(33) 1 30 58 90 09 - http://www.adas.fr - mail@adas.fr

ACTG16 “TOP GROS” DIGITAL INPUTS

trademarks and logos are registered

ACTG

SPECIFICATIONS (t = 25°C)TYPE PSEUDO DIGITAL BOARD INPUTS - Number 16 - Input impedance ≥ 100KΩ - Levels Adjustable by means of resistors

(± 10V rated voltage with no attenuation) - Polarization resistors Stepped rheostats, selectable or not - Polarization voltage + 5V or + 15V for all channels COMPARATORS - Comparison thresholds 4 thresholds 1 for 4 channels - Adjustments For each potentiometer ± 10V - Compared outputs TTL Type - Level The logic level can be inverted for each channel SIZE (H x W x D) in mm 114 x 78 x 18 Front panel 88 x 17,6 WEIGHT

135 Gr POWER REQUIREMENT

+ 15V / 50mA ; - 15V / 50mA + 5V / 80mA CONNECTIVITY Front panel : DMC.M. 2 x 20 pts Back panel : AMP 501 80-pt MINIBOX ENVIRONMENT - Storage temperature - 55 + 100°C - Working temperature - 40 + 75°C - Specifications - 10 + 60°C - Relative humidity 90 % (no condensation) - Sinusoïdal vibrations 20 to 2000Hz - 5g - Shocks 100g - 6ms - Pressure 25 to 1100 mbar - Electromagnetic environment Standards : MIL STD 461A and 462 EUROPEAN NORMS EMC - EN 61326 - EN 55011 Class A CE Compliance ROHS - 2002/95/EC

HOW TO ORDER? ACTG

ACCESSORIES

2 24/46

GLOSSARY

R

RBL

MA

EV X

= Reserved (do not wire)

= Shield recovery

= Analog ground

= Channel inputs

PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL 5 MA 10 EV4 15 EV0 20 MA

B 4 MA 9 EV5 14 EV1 19 MA 3 MA 8 EV6 13 EV2 18 MA 2 MA 7 EV7 12 EV3 17 MA 1 RBL 6 MA 11 R 16 MA

PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL 5 MA 10 EV12 15 EV8 20 MA A 4 MA 9 EV13 14 EV9 19 MA 3 MA 8 EV14 13 EV10 18 MA 2 MA 7 EV15 12 EV11 17 MA 1 RBL 6 MA 11 R 16 MA

ACTG – Rev. A – Edition 4 – 26/11

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TRACEABILITY FORM

DOCUMENT FOLLOW-UP

Title: Titre : ACTG

English documentation Edition: 1 (Document creation - Création du document)

Ph. DUTIN

B. THOUËNON

D. PIMONT

Revised

Approved

Written

by

by

by

21/14

21/14

21/14

on

on

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Warning: Unless otherwise stated, this revision overwrites the previous one which must be destroyed, along with any copies given to your collaborators.

Avertissement : En l’absence d’indication contraire, cette nouvelle édition annule et remplace l’édition précédente qui doit être détruite, ainsi que les copies faites à vos collaborateurs.

Edition Edition

Nature of the modifications (key words) Nature des évolutions (mots clés)

Written Rédigé

Revised/ApprovedRevu/Approuvé

2

Update of the documentation Rev. A

on

Visa

by D. PIMONT

21/30

on

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by Ph. DUTIN

21/30

3

Suppression of DMC connector in the documentation Rev. A

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Update of low address of the board Rev. A

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B. THOUËNON

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DOCUMENT ARCHIVEDDOCUMENT ARCHIVE No Yes on

∆ ed. .. [ ] = Document input/output (Entrée/sortie modification de la documentation) # ed. .. [ ] = Board new function input/output (Entrée/sortie nouvelle fonctionnalité du produit)

DSQ - 4.5.a - Indice F - 98/41 T.S.V.P.

ACTG – Rev. A – Edition 4 – 26/11

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NOTES :

ACTG – Rev. A – Edition 4 – 26/11

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ACTG

SUMMARY

Chapter A Overview...............................................4

Chapter B Operation..............................................5

B.1. Input stage............................................................................... 5

B.2. Comparators............................................................................ 5

B.3. EPLD......................................................................................... 6

B.4. Bus Interface ........................................................................... 6

Chapter C Implementation ....................................7

C.1. General instructions ............................................................... 7

C.2. Installation into the rack......................................................... 7

C.3. Front panel connection .......................................................... 7

C.4. Back panel connection........................................................... 7

C.5. Tests points ............................................................................. 8

C.6. Address of the board.............................................................. 8

C.7. Inputs polarization .................................................................. 9

C.8. Level dividers .......................................................................... 9

C.9. Edge selection........................................................................... 9

Appendix ...........................................................10

CONFIGURATION DRAWING ................................................................. 10

ASSEMBLY DRAWING.......................................................................... 10

ACTG – Rev. A – Edition 4 – 26/11

4

Chapter A Overview

The ACTG board performs the acquisition of 16 pseudo-numerical parameters. It fulfills the following functions:

! Inputs polarization ! Level adaptation ! Comparison ! Sign choice for comparison ! Interface with the Bus board

ACTG – Rev. A – Edition 4 – 26/11

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Chapter B Operation

B.1. Input stage

The input stage of each channel consists in an operational amplifier which performs impedance match. A stepped rheostat RPXX can be wired in order to ensure a given load on outputs of the “OPEN COLLECTOR” type, for example. The choice of the associated logical level is set for all channels to 5 or 15V. A diode in series with the load resistor ensures protection against possible input overloads. When the signal is higher than 10V, it is possible to attenuate it accordingly to bring it back to this voltage level. Stepped RDXX rheostats are provided for that purpose.

>>>Example: If the maximum input level is 20V, RDXX will have a value of 100KΩ 10V (100K) RP = VIN > 10V (VIN – 10V) A protection diode protects the input from the amplifier.

B.2. Comparators The “standardized” signal from the input amplifier is compared with a threshold set by the potentiometer of the considered group. The comparator is wired with a 1/1000 feedback to avoid any oscillations at the time of transition at the switching threshold. The compared input of the HA4900 is then reversed, or not, by a “exclusive or” circuit. This connection lets you choose the equation: VIN > V threshold or VIN < V threshold

ACTG – Rev. A – Edition 4 – 26/11

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FUNCTIONAL SAMPLE OF INPUT

R POLARIZATION

J2B13

INPUT

R DIVISION

ADJUSTMENT THRESHOLD

COMPARATOR

FOLLOWERAMPLIFIER

TRIGGER DIRECTIONINVERSION

CHANNEL

B.3. EPLD

The “inversion” function as well as the whole logic have been brought together in a EPLD 7128. The EPLD adds the function “Debounce” (numerical filtering) to the signals from the comparator. This filter ensures a sampling of 3CLK (CLK = clock bus at 6 MHz)

#∆ ed. 2 [

B.4. Bus Interface The 16-bit word thus formed by the comparison of the pseudo-numerical channels is transferred by the digital bus from the ACCR rack to the connection board. An ACCR rack can manage up to 4 « Top Gros » boards. The DIP SWITCH “SW5” makes it possible to select the address of the board for “DATA” exchanges.

#∆ ed. 2 ]

ACTG – Rev. A – Edition 4 – 26/11

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Chapter C Implementation C.1. General instructions

The user will read beforehand the electronic document available on our Internet site, in chapter Other Services "Implementation":

GENERAL INSTRUCTIONS FOR IMPLEMENTING ADAS PRODUCTS

INSTRUCTIONS GENERALES DE MISE EN OEUVRE DES PRODUITS ADAS

C.2. Installation into the rack An ACCR rack can receive 4 ACTG boards. The ACTG board can be used with other analog ACHB or ACTP boards. For possible restrictions with other boards, please refer to the documentation on rack ACCR.

C.3. Front panel connection The ACTG board uses a DMC 40-pt connector (2 X 20). Please see the board’s datasheet.

C.4. Back panel connection See drawing on next page.

ACTG – Rev. A – Edition 4 – 26/11

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#∆ ed. 2 [

C.5. Tests points TP1, TP2, TP3, TP4 These points make it possible to control the adjustment of the threshold potentiometers.

THRESHOLD TEST CHANNELS PR1 TP1 Channels from 0 to 3 PR2 TP2 Channels from 4 to 7 PR3 TP3 Channels from 8 to 11 PR4 TP4 Channels from 12 to 15

#∆ ed. 2 ]

C.6. Address of the board #∆ ed. 4 [

Switch SW5 selects the address of ACTG board.

SW5

A4 A3 A2 A1 LOW ADDRESS ON ON ON ON

ON ON ON OFF

0 Equivalent CCE2 even address 1 (group 0)

ON ON OFF ON

ON ON OFF OFF

2 Equivalent CCE2 odd address 3 (group 1)

NB : ! The other configurations are not considered in ACCR racks ! The HIGH address is set to 5 by SW6

#∆ ed. 4 ]

ACTG – Rev. A – Edition 4 – 26/11

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C.7. Inputs polarization

Stepped rheostats are provided for inputs polarization. Their selection or not is possible via switches provided for that purpose on SW3 and SW4. Their polarization voltage is common to all the channels and can be set to 15V or 5V via the selection switch provided.

C.8. Level dividers The amplitude of the input signals is ± 10 V full scale in order to be able to support a comparison threshold. For signals of higher amplitudes, divider bridges are considered.

100 K

VIN

R DIV

VCOMP -

+

R DIV x 0 V ANA VCOMP = VIN 100 K + R DIV

C.9. Edge selection The logical signal of the comparator can be or not reversed. This allows to choose the ‘idle’ logical state. Switches on SW1 and SW2 make this choice possible for each channel.

ACTG – Rev. A – Edition 4 – 26/11

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Appendix

CONFIGURATION DRAWING

ASSEMBLY DRAWING