adrian ionescu nanolab, epfl switzerland 1. prove that energy efficient nanolectronics is a must for...
TRANSCRIPT
1
NEMS Devices OPPORTUNITIES AND CHALLENGES
Adrian IonescuNanolab, EPFL Switzerland
2
Goal of this talk…
Prove that energy efficient nanolectronics is a must for the future…
… and NEMS is a potential key enabling low power technology.
3
Switch made for performance…
Source: Heike Riel, IBM.
4
… not for energy efficiencyPower crisis in nanoelectronics• Leakage power dominates in advanced technology nodes.• VT scaling saturated by 60mV/dec limit, voltage scaling slowed.
Po
wer
Den
sity
(W
/cm
2 )
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
0.01 0.1 1Gate Length (μm)
Passive Power Density
Active Power Density
Source: B. Meyerson (IBM) Semico Conf., January 2004
5
Today’s computing: energy/bit
What matters: energy / computed bit scaling systemability system level metrics prevail
over device level
Integrated approach for energy/bit at system level: Switch Memory Interconnects Architecture Embedded Software
1940 1960 1980 2000 2020
10-19
10-16
10-13
10-10
10-7
10-4
10-1
10-1
102
105
108
1011
1014
1017
1020
Ene
rgy
[Jou
le]
Year
Tod
ay
energy / logic operationinverter only incl. on-chip comm.
Ene
rgy
[kT
]
3kT ln(2)
6
Average subthreshold swing
)/log(/)/log(/ offonddoffTGoffTavg IIVIIVVS (mV/decade)
@ VD=VddVG
7
Subthermal switches
A fundamental issue?
10ln)1(log)(log q
kT
C
C
I
V
I
VS
ins
s
n
D
S
m
S
g
d
g
n less than (kT/q)ln10# injection in the channel Tunnel FETs Impact Ionization MOS
m less than 1active gate devices:
NEM relay or NEMFET negative capacitance
8
Nano-Electro-Mechanical (NEM) Devices NEM switch NEM memory NEM resonators
9
Electro-mechanical info processing
as a multi-state logic, with the logic states dictated by a spatial configuration of movable objects
as vibrational modes of mechanical elements, based upon waves.
as a sensed or transduced signal operation.
10
NEMS simulation and modeling
Source: G. Li et al, Urbana-Champaign.
11
NEM relay as subthermal switch
• Advantages: - zero Ioff (zero static
power). - abrupt transition
between off and on states.
• (Unwanted?) feature of NEM switch:
- hysteresis due to different values of pull-in, Vpi (off-on transition) and pull-out, Vpo (off-on transition) voltages.
60mV/dec
Idealswitch
MOSswitch
NEM switch
VpiVpo
Gate voltage
Dra
in c
urre
t
G
D
S60mV/dec
Idealswitch
MOSswitch
NEM switch
VpiVpo
Gate voltage
Dra
in c
urre
t
G
D
S
A
gkV effeff
pi027
8
Pull-in voltage:
12
MEMS process integration
• For low cost & high performance, post-CMOS integration is desirable.
• Thermal process budget is constrained for MEMS fabrication: surface micromachining is low T
Si Substrate
foundry CMOS MEMS
Source: T.J. King.
13
Electro-mechanical design
air-gapMovable electrode
source draingate
insulator
substrate
air-gap
source draingate
insulator
substrate
OFF state
ON state
air-gapMovable electrode
source draingate
insulator
substrate
air-gap
source draingate
insulator
substrate
OFF state
ON state
3-terminal relay:Stanford
4-terminal relay:UC Berkeley
air-gapMetal
Si n+
insulator
substrate
thinoxide
anchor
anchor
air-gapMetal
Si n+
insulator
substrate
thinoxide
anchor
anchor
2-terminal relay: EPFL
14
MEM logic relay
Body
Drain
Source
Body
Gate
Channel
A
A’
(a) Relay schematic
(b) AA’ cross-section: OFF-state
Drain Source
Gate
Body
Gate oxide
Substrate
(c) AA’ cross-section: ON-state
Insulator
IDSBody
Drain
Source
Body
Gate
Channel
A
A’
(a) Relay schematic
(b) AA’ cross-section: OFF-state
Drain Source
Gate
Body
Gate oxide
Substrate
(c) AA’ cross-section: ON-state
Insulator
IDS
1.00E-14
1.00E-12
1.00E-10
1.00E-08
1.00E-06
1.00E-04
1.00E-02
-6 -4 -2 0 2 4 6 8 10
Gate to body voltage, VGB [V]
Dra
in c
urr
en
t, I D
S [
A]
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-1.5 -1 -0.5 0 0.5 1 1.5
Drain voltage, VDS [V]
Dra
in c
urr
en
t, I D
S [
mA
]
12μm
27μm
30μm
19μm
16μm
ANCHOR
GATE
BODY
DRAIN SOURCE
3μm
5μm
2μm
15μm
1μm
5μm12μm
27μm
30μm
19μm
16μm
ANCHOR
GATE
BODY
DRAIN SOURCE
3μm
5μm
CHANNEL2μm
15μm
1μm
5μm
10-2
10-4
10-6
10-8
10-10
10-12
10-14
(a) (b)
VS=VB=0VPI=6V
VG>VPI
VG=5V (<VPI)
VG=1.1·VPI
1.2·VPI
1.4·VPI
1.6·VPI
1.8·VPI
2·VPI
VD=10mV100mV
1V
VD=10mV100mV1VVD
VS
VGVB
n-relay
VD
VS
VG VB
p-relay
VS=0VDD=8V
GND
VDD
Source: V. Pott, T.J. King, UC Berkeley.
Nice but large (10’s micrometer) size!Scalable?
15
Metal NW relays
W. W. Jang et al, Appl. Phys. Lett., 92(10), 103110, 2008.
Nice,small size!Ioff excellentBut voltagelarge: > 10VScalable?
16
Relay-based IC designCMOS to real logic mappping
Relay technology
F. Chen et al, ICCAD 2008.
100x less energy per
half-adder
17
Comms: energy per useful bit
Energy / useful bit = transmit energy + transmitted energy + receive energy= signal processing +
front-end= signal processing +
front-end + sleep (“scan”) mode
10 pJ @ 2m
~1000 less than SoA
PHY, MAC, NETW
Role of MEMS/NEMS in
low power communications?
18
First MEMS memoryB. Halg, "On a micro-electro-mechanical nonvolatile memory cell", IEEE Transactions on Electron Devices, Vol. 37, Iss. 10, 1990.• thin micromachined
bridge elastically deformed:two stable mechanicalstates : “0” and “1”• MOS process: Si02 layer bridge covered by a 2nm thin Cr• state of the bridge changed using electrostatic forces• read out by sensing the capacitance• Size: ~hundreds mm2
• Actuation voltage: > 40V
19
Bistable NEM NV memory cell
Y. Tsuchiya, K. Takai, N. Momo, T. Nagami, H. Mizuta, S. Oda, "Nanoelectromechanical nonvolatile memory device incorporating nanocrystalline Si dots", Journal of Applied Physics, 100, 2006.
20
NEMORY cell concept (1)
Write word line (WWL)
Read word line (RWL)
ONO stack
Bit line (BL)
Insulator
Air gap 2
Air gap 1
tgap2
tgap1
tbeam
• Nano-Electro-Mechanical NV memory – RWL as a top electrode– BL as a movable mechanical beam: information stored as BL position– ONO stack for charge storage– WWL as a lower electrode
W.Y. Choi; H. Kam; D. Lee, J. Lai, T.-J. King Liu, "Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration", Technical Digest of IEEE International Electron Devices Meeting, IEDM 2007.
21
NEMORY cell concept
VBL-WWL (= VBL - VWWL)
tgap1
Vpull-inVreleaseVBL-WWL (= VBL - VWWL)
tgap1
Vpull-in’Vrelease’
“1”
“0”
Fresh nitride Charge-trapped nitride
Shift byVoffset
Vpull-in’= Vpull-in - Voffset
Vrelease’= Vrelease - Voffset
“Fresh” = no charge trapped in nitride
• NEMory cell operation is based on the hysteretic behavior of a mechanical gap-closing actuator.
• Charge in the ONO layer is used to shift the hysteresis curves by Voffset, to achieve bistability at 0 V (VBL-WWL VBL - VWWL), thus enabling non-volatile storage.
22
FinFACT –switch & memory
J.W. Han, Jae-Hyuk Ahn, Min-Wu Kim, Jun-Bo Yoon, and Yang-Kyu Choi, "Monolithic Integration of NEMS-CMOS with a Fin Flip-flop Actuated Channel Transistor (FinFACT)", IEDM 2009.Principle: laterally movable (suspended) silicon FIN, bistable & sensed by transistor current flow.
23
FinFACT (2)
- Depending on design (width) can be used both as NV (ROM) or SRAM.- Trade-off between the endurance and retention.
24
CNT-based memory cell
NEM switched capacitor structure based on vertically aligned MW CNTs
- Capacit. of CNT NEM DRAM cell (diameter=60 nm; length=1.6 mm; SiNx,=40 nm): value of 0.59 fF with available potential of 2.4 mV for bit line sensing in a conventional DRAM design.-15 fF and 60–80 mV (Gbit DRAM) possible by the integration of high-k (not shown)- voltages > 14V
J.E. Jang et al, "Nanoscale memory cell based on a nanoelectromechanical switched capacitor", Nature Nanotechnology, Vol. 3, Jan. 2008, pp. 26-30.
25
NEMS memory figures of merit
90nm Technologies: NEMory NOR Flash Phase-Change Memory Ionic Memory
Storage mechanismmechanical gap-closing actuator
charge on floating gate
reversible material phase change
Ion transport and redox reaction
Cell area 6~12 F2 10 F2 4.8 F2 5~10 F2
Program/erase time 0.9 ns / 0.3 ns 1 ms / 10 ms 50 ns / 120 ns < 20 ns
Read time >1.5 ns 10 ns 60 ns <10 ns
Program/erase voltage 1.5 V 12 V 3 V < 0.5 V
Read voltage 3 V 2 V 3 V < 0.2 V
Program/erase energy 3 10-17 J/bit 10-14 J/bit 5 10-12 J/bit 10-15 J/bit
• comparable cell area• scalable/comparable operation voltages • lowest program/erase energy: sub-10-16 J/bit.
26
NEM resonators
Adrian Ionescu, GRC 2012 26
• Probably the most promising family of RF M/NEMS.• Embedding full equivalent circuit functions (RLC) with
very high-Q and voltage tuning (possible replacement of quartz).
• Applications: oscillators, mixing, filtering, sensing.
Passive MEMS resonatorResonant body transistor
27
Their scaling…
Frequency, mass, Qmass & force detection
nm SOI-CMOS technologyintegration density, complexity
Nanowire RB-FET: 40 nm x 40 nm x 2 um
Fully-depleted RB-FET: 0.5 µm x 0.25 µm x 10 µm
400 nm
NW-FET body
28
Low power characteristics
Tunable operation point: Trade-off: gain versus power. Experiment: resonance from strong to weak
inversion. nW static power consumption in weak-inversion
(PDC < PAC ).
S. T. Bartsch, A.M. Ionescu, IEDM 2010.
29
Vibrating body transistors
• Double-gate (in-plane) VB-FET resonator: transistor detection improves output signal by more than +30dB.
D. Grogg et al, IEDM 2008.
Capacitive
Transistor
30
Full circuit functions…• Transistor-based homodyne / heterodyne mixing.• Mixing coupled to mechanical motion.• Signal-to-background improvement.• Applications: VHF mixer-filter, closed-loop configurations.
Imix ~ gm
S.T.Bartsch et al, ACS Nano 2011.
Mixer output [a.u.]
Frequency [MHz]
Gate
Votl
age[V
]
Cc-Beam: 0.15 x 0.2 x 3 µm3
f0=78 MHz, Q=1100
31
Ultra-scaled single-NEM radio Highly sensitive integrated sensor arrays (~10-100
attogram) Ultra miniaturized single-device radios (RF front ends)
32
Vibrating body CNT FET
Adrian Ionescu, GRC 2012 32Adrian Ionescu 32 32A.M. Ionescu, IEDM 2011
Device concept:• SW CNT instead of Si• fres ~100MHz-1GHz• strong piezores. Effect 2xf• DG, 100nm airgap• By resist-assisted DEP(>107 CNTs/cm2)
33
Nano-scale active mass balance
Source: Ji Cao, EPFL.
34
Summary (1)
Energy efficient devices: a must for the future! Challenges:
NEMS
Relays• scaling of:
gaps & size operation voltage
• reliability of contacts & packaging• dedicated IC design
Resonators• analog/RF & sensing
35
Summary (2)
NEM memory: exploit the. electromechanical hysteresis of movable
structures by a gap closing Storage layer: specific purpose for shifting the hysteresis (NEMory, Oda’s memory, SG-FET)!
excellent co-integration with silicon CMOS. Low temperature processing, BEOL (3D-) integration possible, low cost.
Low voltage operation possible, limits ~1V Program/erase & read times: <10ns energy efficiency: less than 10-16 J/bit in NEMory & SBM. Trade-off between endurance & retention in FIN-FACT. Robust in high temperature and radiation environments. CNT-based memory: immature Promising for embedded memory applications
36
Roadmap of NEMS applications