advanced through silicon viasfor pixel detectors€¦ · § tsvs+ wafer thinning + aligned bonding...

WP 2 SESSIONF. HÜGGING, N. OWTSCHARENKO, N. WERMES (U BONN)T. FRITZSCH, O. EHRMANN, K. ZOSCHKE (FRAUNHOFER IZM)

ADVANCED THROUGH SILICON VIAS FOR PIXEL DETECTORS

INTRODUCTION

− Through Silicon Vias are nowadays widely used in industry for different purposes, e.g:

− Memory chips, 3D integration, interposers etc.

− Usually these are dedicated, highly industrialized processes which are not accessible for other costumers

− Scope of the project is the development of a post processing TSV for a wider range of input material like:

− Readout ICs for silicon pixel detectors− Project and TSV run started off in spring 2017− Current status and first results

− Industrial applications− X-ray imager − IR cameras− Packaging of CMOS cameras

26.04.18 Advanced TSV for Pixel Detectors - F. Hügging - AIDA-2020 3rd Annual Meeting Bologna 2

3D INTEGRATION TECHNOLOGY USING TSVS

Yole Report 2012: 3DIC & TSV

Interconnects

3D Packaging:• CMOS Image Sensors• MEMS

Lateral die stacking for high bandwidth:• Power/RF/Analog• Logic & Analog• Logic & Memory

(GPU for Gaming)

3D Chipstacking:• Logic & DRAM for

higher bandwidth(WIDE I/O interface)

• Memory stacking

3D WLCSP 3D IC 2.5D Interposer


TSV LANDSCAPE MAPlargest lengthmiddle aspect ratio

taken from T. Fritzsch, Interposer – An enabling technology for fan-out hybrid pixel modules, IWORID 2016, Barcelona.


TSVS FOR PIXELDETEKTORS

BONN-IZM TSV PIXEL PROJECT

§ TSVs + wafer thinning + aligned bonding are the key technical elements for a 3D extension of electronics integration -> eminent field of industrial research

o denser packaging - lower power - larger I/O bandwidth - more functionality at lower cost

§ Huge interest (and market) in packaging industry with fast recent advances

§ Promise for pixel detectors à more compact modules with active area maximization, no wire bonds, and 4-side abuttable (X-ray), use backside for wiring (RDL) à joint interest Bonn - IZM

§ Needs/challenges which both partners profit from

o large length and relatively large aspect ratio (length/diameter) TSVs with reliable fabrication yield

§ Goal: develop pixel modules for HL-LHC employing TSVs in a via-last process (after CMOS process)

Standard moduleATLAS IBL

TSV module


THROUGH SILICON VIA TYPES

§ via-last process in FE-I4:

§ Metal layers in the pad connect M8 to M1

FE-I4 BEOL layer stack

Al pad

TSV


ADVANCED THROUGH SILICON VIAS FOR PIXEL DETECTORS

§ Goal: establish high yield TSV + RDL process for pixel modules

§ straight vias through ultra thinned FE-I4 wafers and chips: note 2x2 cm2 chip size

§ 80 – 100 µm thickness (to be optimized),

§ aspect ratio = 2 : 1 (via diameter 60 µm)

§ thin wafer backside process using carrier wafer

§ complete development including flip-chipping process for the final pixel module

naked

with UBM

support waferattached

2nd support wafer for flip

chip

Challenges of the project

§ reliable TSV fabrication ... yield hoped/expected to be much better than for project 2§ thin (o(100 µm)) wafers are needed for the goal of “large yield” challenge is the handling of large and

very thin wafers/chips§ surprises during flip-chipping can also be an issue


TSV PROJECT IMPLEMENTATION PLAN

qWP1:

§ Process optimization for very thin (80-120 µm) readout wafers

qWP 2:

§ Design optimization of the TSV and RDL layers

qWP 3:

§ TSV run with optimized RDL design on FE-I4 wafer batch incl. electrical tests

qWP4:

§ Optimization of bumping and flip-chip using ultra thin TSV chips to sensors

qWP 5:

§ Characterization of TSV chip sensor assemblies


March to July 2017

July to September 2017

October 2017 to April 2018

May to August 2018

August to December 2018

WP1: TSV process step evaluation

− Fabrication of process setup wafer with dedicated test structures à first structures characterized, further tests ongoing

− Evaluation of individual process steps (wafer thinning, TSV etching, passivation and RDL layer deposition) à in progress

− Characterization of test structures à ongoing

WP2: TSV wafer design and mask fabrication

− Development of gds2 wafer layout mask set including all lithography mask layers à design finished, mask ordered

− Fabrication of lithography glass masks à done

WP3: ATLAS FE-I4 batch TSV process

− UBM deposition on the wafer front side à finished

− thinning of the wafer à finished

− bonding of the thinned wafer onto carrier à finished

− backside processing including TSV etch, deposition of passivation, plating base TSV filling and RDL multi-layer à finished

− Carrier wafer release, cleaning, dicing à in progress

WP4: Flip chip bonding process

− Assembly of setup modules and optimization of bonding parameters

− Characterization of bonding interfaces and bonding yield

− Assembly of functional modules

WP5: Characterization of TSV chip sensor assemblies

− Initial functional tests and tuning

− Full characterization of TSV pixel detector modules in lab and at test beams


AIDA 2020 PROOF OF CONCEPT: ATLAS FE-I4

TSV WORK STATUS OVERVIEW

© DISCO

1. Wafer Thinning: Grinding, (Wet Etching), DRIE

2. TSV Si-etching: DRIE BOSCH Process

3. TSV-Insulation: (TEOS), PE-CVD, (SA-CVD, Polymer)

4. Adhesion-/Barrier-/Seed-Layer: Ti (TiW, TiN, Ta(N)) / Cu HI-PVD

5. Via filling: ECD Cu (bottom up filling), liner filling

6. RDL / UBM pad metallization

All pictures courtesy of Fraunhofer IZM, Berlin. 26.04.18 Advanced TSV for Pixel Detectors - F. Hügging - AIDA-2020 3rd Annual Meeting Bologna 11

ATLAS FE-I4 TSV RUN: PROCESS STEPS

ATLAS FE-I4 TSV WAFER BATCH: PROCESS STATUS

− UBM deposition on the wafer front side - done

− bonding of the thinned wafer onto carrier - done

− thinning of the wafer - done

− backside processing including:

− TSV etch – done− deposition of passivation – done− TSV filling – done− passivation – done− probe pads – done

− Release of carrier wafer - done

− Cleaning of ATLAS FE-I4 wafer frontside

− Dicing


ATLAS FE-I4 wafer: frontside after UBM process

ATLAS FE-I4 wafer: backside after RDL+UBM-Pad process



ATLAS FE-I4 Wafer: Frontside bonded onto carrier

ATLAS FE-I4 Wafer: Backside thinned to 100 and 80 µm

Silicon thickness measurement after wafer thinning: 80µm left / 100µm right


Via formation etch steps – etch depth 80/100 µm:

• Silicon etch TSV

• Oxide etch between bulk Si – poly-Si

• Poly-Si etch

• Oxide etch between poly-Si – M1-BEOL Cu metal


Backside step 1: (left) Silicon TSV etch (wafer surface), (middle) focus via bottom - poly-Si + M1-BEOL layer

Backside step 2: Oxide etchfocus via bottom - BEOL layer M1


RDL formation steps:

• TSV filling – Cu-liner filling process

• RDL-formation on top side

• Passivation layer deposition and opening

• Probe/wire bond pad formation - NiAu


Backside step 3: (left) Backside-RDL and filled TSVs, (middle) Cu TSV filling X-ray check

Backside step 4+5: Passivation & Probe pads,view onto Probe pads

TSV DAISY CHAIN MEASUREMENT AND TSV RESISTANCE MEASUREMENT ON SETUP WAFER

Test features:

− 1x full Daisy Chain with 168 TSVs− 3x Daisy Chain segments with 56 TSVs− 2x individual TSV-electrical resistance probe

structuresStatus:

− Individual test structures measured− Full wafer testing/programming ongoing


Resistance of individual TSV: 15…16 mΩ

Wafer backside with probe pads

Wafer frontside with Al/Cu pads

MEASUREMENT OF TSV PASSIVATION LAYER

BREAKDOWN VOLTAGE ON SETUP WAFER

− TSV diameter: 60µm

− Passivation layer thickness:1000nm…~500nm (top to bottom)

− Detectable breakdown voltage starting at 40V, max. 100V

− Slightly increase in current to be investigated

− Disadvantage: position of breakdown not visible

− Process optimization possible àbenchmark of 80V breakdown achievable but not required here


0,0E+00

2,0E-04

4,0E-04

6,0E-04

8,0E-04

1,0E-03

0 20 40 60 80 100 120

Curr

ent [

A]

Voltage [V]

ATLAS FE-I4 TSV – CAPACITY TEST

STRUCTURES ON TSV TEST WAFERS

• Capacity test structures implemented into new wafer TSV design

• Will be part of TSV setup wafer with M1-layer processed with ATLAS FE-I4 TSV wafer batch


Picture taken from previous TSC process setup wafer

a b

Pictures from functional ATLAS FE-I4 wafer: test pads but no bulk contact due to possible interferences with functionallity

TOWARDS INDUSTRIAL

APPLICATIONS

Yole Report 2012: 3DIC & TSV Interconnects

3D Packaging:• CMOS Image Sensors• MEMS• Hermetic Packaging

3D WLCSP

3D Chipstacking:• Logic & DRAM for higher

bandwidth(WIDE I/O interface)

• Memory stacking

3D IC

Lateral die stacking for high bandwidth:• Power/RF/Analog• Logic & Analog• Logic & Memory (GPU for Gaming)

2.5D Interposer

POSSIBLE IMPACT ON FURTHER TSV APPLICATION: OVERVIEW

− Main Focus for TSV is via last process but even other applications (i.e. interposer + hermetic packaging) are possible


• TSV Module: MEDIPIX3 TSV ROC + edgeless Sensor Chip• TSV Module mounted on test board, backside contacts with solder balls • Functional test with x-ray source at DESY side

• TSV process from wafer backside • Cu-filled TSV• Cu-RDL and NiAu-solder ball pads

TSV-APPLICATION: X-RAY CAMERA MODULES FOR SYNCHROTRON APPLICATION/IMAGING


Fraunhofer IZM – Process Development for Industry Partners:

§ Sensor chips are arranged in arrays on PCB

§ Wafer level packaging of sensor chips with through silicon vias(TSVs)

§ Redistribution of electrical connections to back side of chips enables dense side-by-side placement with minimal gaps for high efficient usage of array surface area

§ Each sensor chip is protected by a thin glass layer which is transparent for light

§ Array assembly of sensor chips on PCB by pick & place and reflow soldering

TSV-APPLICATION: 4×4 SENSOR ARRAY IN HIGH-DENSITY TECHNOLOGY


Process at IZM:§ TSV-frontside process

§ Completely-filled Cu-TSV

§ Frontside and backside RDL

§ Fronside Solder Bumps/Pillars

§ Backside solderable Pad Metallization

§ Hybridization to sensor

§ 2nd level assembly to LTCC

UFXC32k Readout Chip developed by AGH Krakow, Poland

Cross section of Bare Module, with Cu filled TSVs in ROC

TSV ROC

Bare Module, with sensor and two TSV-ROCsComplete Module: Sensor + TSV-ROC + LTCC Board, functional test

TSV PROCESS FOR ULTRA FAST XRAY PIXEL MATRIX CHIP


CONCLUSIONS & OUTLOOK

− A versatile via last TSV process with straight side vias on IO pads and a multi-layer RDL is being developed for the ATLAS FE-I4 Pixel Detector as Proof-of-Concept

− Design and process optimization is finished

− Detailed electrical characterization of the TSV properties is currently pursuit with dedicated test structures coming from setup and process monitor wafers

− Processing of 3 FE-I4 is basically finished on time and first chips are expected in these days at Bonn for testing

− Flip Chip to sensors and building of full pixel detector assemblies is the next step

− Second goal is to generalize this approach not only for HEP pixel detectors but also for similar industrial detector projects

− Several projects at IZM have already benefited from the work of this project

− A process tool set for via last TSV on CMOS wafers is being developed and offered to other customers


Thank you for your attention

Fabian Hügging

University of Bonn

Physikalisches Institut, Nussallee 12, D-53115 Bonn

[email protected]

advanced through silicon viasfor pixel detectors€¦ · § tsvs+ wafer thinning + aligned bonding...

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