advances in mixicsensitivity degradation in a tri -band gsm bicmos direct-conversion receiver caused...
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![Page 1: Advances in mixicSensitivity degradation in a tri -band GSM BiCMOS direct-conversion receiver caused by transient substrate heating. IEEE Journal of Solid-State Circuits, Vol. 43,](https://reader034.vdocument.in/reader034/viewer/2022042108/5e87b1d883a0c76343576d22/html5/thumbnails/1.jpg)
Lund University - Department for Electrical and Information Technology
2008/09 Advances in themixed signal IC design group
Mattias Andersson
Mixed-Signal IC Design Department for Electrical and Information Technology
Lund University
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Lund University - Department for Electrical and Information Technology
Mixed Signal IC Design Researchers
• Associate Professor, Pietro Andreani• Assistant Professor, Martin Anderson (SoS-DSCs, nov 2008)• Post-Doc, Ping Lu (VR-ADPLL, april 2009)• Ph.D Student, Dejan Radjen (VR-UPD, feb. 2009)• Ph.D Student, Mattias Andersson (SoS-DSCs, feb. 2009)
• Adjunct Professor, Lars Sundström• Adjunct Professor, Sven Mattisson• Professor Emeritus, Jiren Yuan
CAD support: Stefan MolundLinux support: Erik Jonsson
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Lund University - Department for Electrical and Information Technology
Publications Summary 2008/2009
• Journal Papers: 6 (4 JSSC, 1 TMTT, 1 TCAS-II)• International Conference Papers: 3 (2 ISSCC, 1 NORCHIP)• Ph.D Thesis: 1• National Conference Papers / Presentations: >3
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Lund University - Department for Electrical and Information Technology
Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise
Andrea Mazzanti and Pietro AndreaniIEEE Journal of Solid-State Circuits
Vol. 43, No. 12, pp. 2716-2729, Dec. 2008
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Lund University - Department for Electrical and Information Technology
Class-C thanks to tail capacitance Ctail
• Class C Larger amplitude, same noise for same Ibias
• Ctail from foe to friend
• MOS must not leave saturation Shift of MOS DC gate voltage
• 6M (Cu) 0.13µm CMOS (no thick metal layers)
• 2.0nH inductor, A-MOS varactors, tank-Q≈16-17
Ctail= 2·C2
Ibias
VDD
Ctank
L
Vbias
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Lund University - Department for Electrical and Information Technology
State-of-the-art phase-noise performance
fosc=4.90GHz
fosc=5.52GHz
-130dBc/Hz
• 4.90 GHz < fc< 5.65 GHz
• Vdd= 1V, Idd=1.4 mA
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Lund University - Department for Electrical and Information Technology
General result on phase noise
• Harmonic oscillators Phase noise generated by active devices in
oscillator core largely independent of the active device dimensions
Instead, determined by resonator losses
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Lund University - Department for Electrical and Information Technology
DT Modeling and Reductionof Clock Jitter Sensitivity
in CT Delta-Sigma Modulators
Martin Anderson and Lars Sundström
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 7, pp. 530-534, 2009
IEEE Journal of Solid-State Circuitsvol. 44, no. 2, pp. 473-483, 2009
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Lund University - Department for Electrical and Information Technology
Clock Phase-Noise Sensitivity Intro
DAC
H(s)vd[n]
clk
va(t)
vc(t)
clk
∫f0
Sd(f)
fclk
f
Sclk(f)
Close-in PN Input signal
Wideband PN Quantization noise
Shaped q-noise
Close in noise
Wideband noise
Desired signal
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Lund University - Department for Electrical and Information Technology
DT Clock Phase-Noise Modeling Method
Pulse-Width Noise (PWN) models the modulation between quantization
noise and wideband PN
Pulse-Position Noise (PPN) models the modulation with strong signals and
close in PN
Faster simulations witharbitrary input signals andarbitrary clock PN spectra
CT ∆Σmodulator
vc vd
Noisy clock
DT ∆Σmodulator
vd
Ideal clock
PPNmodel
Signal gen
PWN model
vc
PWN
PPN
vd PN
PNvd
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Lund University - Department for Electrical and Information Technology
1 10 100
-140
-120
-100
-80
-60
-40
PPN
PWN
DT sim.OFDM input signal
QN
Frequency [MHz]
Typical DT simulation output
spectra
DT Clock Phase-Noise Modeling Method
CT ∆Σmodulator
vc vd
Noisy clock
DT ∆Σmodulator
vd
Ideal clock
PPNmodel
Signal gen
PWN model
vc
PWN
PPN
vd PN
PNvd
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Lund University - Department for Electrical and Information Technology
DT Modeling Summary and Conclusions
• In-band noise a function of– phase-noise spectra– input signals– quantization noise spectrum (NTF)
• DT modeling method enables fast and accurate PN simulations• Verified with simulations and measurements• Conclusion
– PWN limits the performance in many practical situations.
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Lund University - Department for Electrical and Information Technology
SC-feedback reduces clock jitter sensitivity
CT ∆Σ modulator with SI RZ feedback CT ∆Σ modulator with SCR feedback
- High sensitivity to PW variations+ Small peak current
+ Low sensitivity to PW variations- Large peak current
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Lund University - Department for Electrical and Information Technology
SC-feedback with variable series resistor
Reset Constant current
Switched capacitor Reduced sensitivity to PW variations
Variable resistance Reduced peak current
Exponential discharge
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Lund University - Department for Electrical and Information Technology
PN Measurements – PN Amplitude Sweep
Sensitivity to systematic (single tone) phase-noise
IBN
[dB
FS]
30 dB IBN improvement
PW jitter, (σpw / Ts) [%]
@ fo / fs = 0.3
Total measured IBN
SI DAC PWN simulation
Total simulated IBN
SI DAC PWN simulation
PN tone amplitude sweep
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Lund University - Department for Electrical and Information Technology
Summary and Conclusions
• The SCSR feedback DAC concept is proposed– Reduced sensitivity to wideband phase-noise– Reduced peak feedback current
• ADC circuit fabricated– A 5-mW, 312-MHz, 2nd-order CT ∆Σ modulator with SCSR
feedback, 66dB SNR.– 30dB reduction of sensitivity to wideband clock PN measured
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Lund University - Department for Electrical and Information Technology
Work in Progress – Ping Lu (postdoc)
REF
PFD/TDCΣ
a
b
Tuning Bank
Controller
∑Δ Modulator
/N
Loop Filter
DCO
New Time-to-Digital Converter design
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Lund University - Department for Electrical and Information Technology
Work in Progress – Dejan Radjen (Ph.D student)
• Ultra low power 3rd order, 3 bits CT ∆Σ - ADC with modified feedback pulses
• Sampling frequency = 5MHz, Bandwidth = 125 kHz, SNDR = 74 dB, Power consumption = 100 μW
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Lund University - Department for Electrical and Information Technology
Work in Progress – Mattias Andersson (Ph.D student)
• CT ∆Σ ADC for LTE (short term goals)– 3rd order, fs=288MHz, BW=9MHz
• Protection• New clocking scheme• Multibit DACs and DEM
• Tapeout planned Q1 2010
DAC
H(s)vd[n]
va(t)
vc(t)
clk
∫
clk
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Lund University - Department for Electrical and Information Technology
Journal Publications 2008/2009
S. Mattisson, H. Hagberg, P. Andreani, Sensitivity degradation in a tri-band GSM BiCMOS direct-conversion receiver caused by transient substrate heating. IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, pp. 486-489, 2008. A. Mazzanti, E. Sacchi, P. Andreani, F. Svelto, Analysis and design of a double-quadrature CMOS VCO for subharmonic mixing at Ka-band, IEEE Transactions on Microwave Theory and Techniques, Vol. 56, No. 2, pp. 355-363, 2008. L. Lu, Z. Tang, P. Andreani, A. Mazzanti, A. Hajimiri, Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators””, IEEE Journal of Solid-State Circuits, Vol. 43, No. 9, pp. 2170-2170, 2008. A. Mazzanti, P. Andreani, Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise, IEEE Journal of Solid-State Circuits, Vol. 43, No. 12, pp. 2716-2729, 2008. M. Anderson, L. Sundström, Design and Measurement of a CT Delta-Sigma ADC with Switched-Capacitor Switched-Resistor Feedback, IEEE Journal of Solid State Circuits, Vol. 44, No. 2, pp. 473-483, 2009. M. Anderson, L. Sundström, DT Modeling of Clock Phase Noise Effects in LP CT Delta-Sigma ADCs with RZ Feedback, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 7, pp. 530-534, 2009.
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Lund University - Department for Electrical and Information Technology
Conference Publications 2008/2009
P. Lu, H. Sjöland, A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM, Norchip, Tallinnn, 2008. J. Citakovic, P. F. Høvesten, G. Rocca, A. van Halteren, P. Rombach, L. J. Stenberg, P. Andreani, E. Bruun, A compact CMOS MEMS microphone with 66dB SNR, 2009 IEEE International Solid-State Circuits Conference (ISSCC), Digest of TechnicalPapers, San Francisco, Vol. 52, pp. 350-351, 2009. A. Mazzanti, P. Andreani, A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz, 2008 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, S. Francisco, CA, pp. 474-475, 629, Feb. 4-6, 2008.
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Lund University - Department for Electrical and Information Technology
SCANDINAVIAN EXCELLENCEDEFINED IN LUND