ANALOG ELECTRONIC CIRCUITS LAB[ICE 212]

2 BIT SYNCHRONOUS COUNTER USING T FLIPFLOPS

Submitted by

1.Sunanda Rajmohan : 1209211802. Joel John Mathai : 120921260

DEPARTMENT OF INSTRUMENTATION AND CONTROL ENGINEERING

MANIPAL INSTITUTE OF TECHNOLOGY(A Constituent College of Manipal University)MANIPAL – 576104, KARNATAKA, INDIA

January-May 2014

Signature:1. Sunanda Rajmohan 2. Joel John Mathai

Lab In-charge: Mr. Mukund Kumar Menon

Date of submission: 26th April , 2014

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ContentsPage No

Abstract 3

List Of Figures 3

List Of Tables 3

Chapter 1 INTRODUCTION

1.1 Introduction

1.2 Literature Reviews

1.2.1 2 input NOR gate

1.3 …………………………………

1.4 ………………………………....

Chapter 2 METHODOLOGY

2.1 Introduction (NOTE: brief about the outline of the chapter)

2.2 Theory

2.3 Designing Procedure

Chapter 3 RESULT

3.1 Introduction (NOTE: brief about the outline of the chapter)

3.2 Observation

Chapter 4 CONCLUSION/INFERENCE

3.1 Conclusion/Inference

3.2 Extension to the project

REFERENCE

ANNEXURE (NOTE: Include transistor datasheets etc.)

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ABSTRACTA synchronous up counter using T flip flop is designed using 2n2222 transistors and resistors. Each flip flop was individually constructed and then connected together to obtain the counter.

LIST OF TABLES

Table No Table Title Page No1 2 input NOR gate 72 3 input And gate 83 T flip flop 8

LIST OF FIGURES

Figure No Figure Title Page No1 Asynchronous counter output 92 Logic Diagram T flip flop 93 Circuit for BJTcharacteristics (2N2222a)

4 Rising and falling edges of synchronous counters

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CHAPTER 1

INTRODUCTION

1.1 IntroductionThis specific chapter discusses the usage, construction and making of an synchronous 3 bit counter using T(toggle)- flipflop.

Counters are specialised registers. They go through a prescribed sequence of states upon the application of input pulses. There are 2 catagories of counters based on different design styles:

a) Asynchronous/ Ripple Counters : In this counter the flipflop are not triggered by the common clock pulse but by the transition in the other flip flop outputs.

b) Synchronous counter : In this counter the flipflops are triggered by a common clock

pulse.

1.2Literature Review

1.2.1 In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.

Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous), clocked devices are described as flip-flops.

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1.2.1 Two input NOR gate

Fig 1.

Fig 2.

State Table for 2 input NOR gate

Input 1 Input2 Action1 0 0

1 1 1

0 0 0

0 1 0Table 1.

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1.2.2 Three input AND gate

Fig 3.

Fig 4.

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State Table for a 3 input AND gate

Input 1 Input 2 Input 3 Action

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

Table 2.

1.2.3 State table of T flipflop

Input Input2 Action

0 1 No change

1 1 Toggle

Table 3.

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1.2.4 Timing diagram of 3 bit synchronous counter using T flip flop

Fig 5.

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CHAPTER 2

METHODOLOGY

2.1 INTRODUCTION

A synchronous up counter using T flip flop is designed using 2n2222 transistors and resistors of 33k, 4.7k and 10k. Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time

2.2 THEORYA synchronous binary counter counts from 0 to 2n-1 where n is the number of bits or flipflops in the counter. Each flipflops is used to represent one bit . The flipflops in the lowest order position is complement/ toggled with every clock pulse and a flipflop in any other position is complemented.

The flipflop in the lowest order position is complemented on the next clock provided to all the bits in the lower order positions are equal to one.

The counter works in this fashion:A3 A2 A1 = 011On the next count A3 A2 A1 = 100.A1, the lowest order bit is always complemented. A2 is complemented because all the lower order positions (A1 only in this case are 1s. A3 is the complement because all the lower order positions A2 and A1 are 1s.

To implement a synchronous counter , we need a flipflop for every bit, except the first and the last bit.

Although the counter is synchronous and is supposed to change simultaneously, we have a propagation delay through the AND gates which add up to give an overall propagation delay which is proportional to the number of the bits of the counter.

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2.3 DESIGNING PROCEDURE

1. The synchronous counter constructed is a 3 bit, hence consist of 3 bit T(toggle) flip flop.

2. The toggle flip flop was constructed using 2 three input AND & 2 two input NOR gates.

3. The output of the first flip flop is fed to the second, which is fed to the third and the final

output is taken from here.

4. The T flip flop has a tendency to toggle when both inputs are high.

5. The transistors used in the circuit are common emitter transistors with output from the

emitter.

6 . The three flip flops are made on the bread boards using connecting wires and then

connected to the IC trainer kit using patch chords.

7. Data sheet of the transistor 2N2222A

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVCBO collector-base voltage open emitter2N2222A − 75 VVCEO collector-emitter voltage open base2N2222A − 40 VIC collector current (DC) − 800 mAPtot total power dissipation Tamb ≤ 25 °C − 500 mWhFE DC current gain IC = 10 mA; VCE = 10 V 75 −fT transition frequency IC = 20 mA; VCE = 20 V; f = 100 MHz2N2222A 300 − MHz

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CHAPTER 3

RESULT

3.1 INTRODUCTIONThe two bit synchronous counter was designed. It was tested by triggering each t flip flop individually and checking the outputs according to the state table of a T flip flop. Then the two flip flops were connected together as a two bit synchronous counter.

3.2 OBSERVATIONIt is observed that the T flip flop retains the state when T='0' and the T flip flop toggles its state when T='1' .

The T input of each flip-flop is connected to a constant 1, which means that thestate of the flip-flop will be toggled at each active edge of its clock. The purpose of this circuit is to count the number of pulses that occur on the primary input called Clock.Thus the clock input of the first flip-flop is connected to the Clock line. The other two flip-flops have their clock inputs driven by the output of the preceding flip-flop. Therefore, they toggle their states whenever the preceding flip-flop changes its state from Q = 1 to Q = 0, which results in a positive edge of the signal.

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CHAPTER 4CONCLUSION/INFERENCE

4.1 CONCLUSION/INFERENCE

With the Synchronous Counter, the external clock signal is connected to the clock input of every individual flip-flop within the counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the same time giving a fixed time relationship. In other words, changes in the output occur in “synchronisation” with the clock signal.

The result of this synchronisation is that all the individual output bits changing state at exactly the same time in response to the common clock signal with no ripple effect and therefore, no propagation delay.

Synchronous Counters use edge-triggered flip-flops that change states on either the “positive-edge” (rising edge) or the “negative-edge” (falling edge) of the clock pulse on the control input resulting in one single count when the clock input changes state.

Generally, synchronous counters count on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple counters count on the falling-edge which is the high to low transition of the clock signal.

Fig 4.

 It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state, but this makes it easier to link counters together because the most significant bit (MSB) of one counter can drive the clock input of the next.

This works because the next bit must change state when the previous bit changes from high to low – the point at which a carry must occur to the next bit. Synchronous counters usually have a carry-out and a carry-in pin for linking counters together without introducing any propagation delays.

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REFERENCE

1. Textbook – A. Anand Kumar2. Datasheetcatalog.com3. Wikipidea.com4. allaboutcircuits.com5. ilovecircuits.com6. transistorcktwrld.com

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ANNEXURE

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