NATIONAL INSTITUTE FOR NUCLEAR AND HIGH ENERGY PHYSICS

ETR XX

ALABUF2 analog buffer chip TECHNICAL DOCUMENT

LHC / ALICE / Inner Tracker System / Silicon Strip Detector /

EndCap modules

Project no: 43000

Vladimir Gromov, Ruud Kluit

Abstract: For the purpose of driving of analog signals from the on-detector front-end electronics of the ALICE SSD to the off-detector ADC, an analog buffer chip (ALABUF) has been designed. The design is performed in 0.25µ CMOS technology. Inputs of the design as well as the design goals specification to be met are described along with circuit optimization procedures and detail chip description. Results on testing of the chips taken from the experimental batch are presented and compared to the simulations.

email: r.kluit@nikhef.nl vgromov@nikhef.nl

Friday, 28 February 2003

NIKHEF, DEPARTMENT OF P.O. box 41882, NL 1009 DB AMSTERDAM ELECTRONIC TECHNOLOGY

2

Report on analogue buffer chip (ALABUF) development in 0.25u CMOS technology for the ALICE Silicon Strip Detector (SSD). 28 March 2002.

V. Gromov (vgromov@nikhef.nl), R. Kluit. ET NIKHEF, Amsterdam.

Abstract.

For the purpose of driving of analog signals from the on-detector front-end electronics of the ALICE SSD to the off-detector ADC, an analog buffer chip (ALABUF) has been designed. The design is performed in 0.25µ CMOS technology.

Inputs of the design as well as the design goals specification to be met are described along with circuit optimization procedures and detail chip description.

Results on testing of the chips taken from the experimental batch are presented and compared to the simulations.

Introduction.

The ALICE SSD detector will be readout by the HAL25 front-end chip [1]. This chip contains 128 analogue channels with preamps, shapers, sample-and-hold circuits, analogue memory and a differential output buffer. Front-end chips on P-side and N-side of the detector operating at different potentials will be connected to an external electronics via decoupling capacitors [2] (see Fig.1).

The limited space available stipulate for daisy-chain connection of the front-end chips on each side of the detector by means of a low-volume low-mass Kapton cable. To provide connection with off-detector electronics a 25m long twisted-pair cable is foreseen.

Fig.1. Principal diagram of the on-detector

electronics of ALICE SSD. To be able to use the same twin-pair cable for read-

out of front-end chips of both sides an analog multiplexer is needed. Such a solution let us by factor of two reduce number of signal wires coming out of the detector, saving space and diminishing amount of material inside the detector.

Being transported over 25m long cable, the output differential signal will be affected by external disturbances known as pick-up noise. In order to reach the best signal-to-noise ratio, the signal must be amplified to the maximum possible value (rail-to-rail of supply voltages, in principle). Schematic solution of such an amplifier is extremely power consuming and hence cannot be implemented in output buffer of a single front-end chip. A structure with an output buffer shared over many front-end chips is much more reasonable solution (see Fig.1). All the more, the buffer could diminish external disturbances when having a high common mode suppression capability.

A front-end chip, being intended to drive a long length cable, suffers from feedback current spikes coming to high sensitive input. These spikes cause signal distortion and trigger self-oscillation. Therefore, it is very reasonable to let a remote buffer drive signals to off-detector electronics thus providing decoupling for the front-end chip.

On the basis of the arguments listed above an analog buffer with multiplexing functionality ought to be designed and located on the ALICE SSD detector.

Inputs for the analog buffer design.

Operation conditions of ALICE SSD playing significant role for the analog buffer design are: [3]

. average trigger rate 1kHz .signal dynamic range ± 13MIP (1MIP=22000e). The analog buffer must not worsen specifications of

the HAL025 front-end chip, which are [1]: .equivalent noise charge (ENC) ≤ 400e . signal nonlinearity < 1.5% (for ± 2MIPS in

13MIP range) .power consumption 14.75mW (for 128 channels) .read-out rate 10 MHz .differential output current 250uA/1MIP. .type of the output signal STEP The buffer chip is supposed to be on detector

therefore: .it must be designed in radiation hard process .it must provide high common mode signal

suppression. Characteristic impedance of the Kapton cable as

well as twin-pair cable is ≈110Ω.

Specifications of the analog buffer.

31. Radiation hard technology.

With the use of the 0.25u CMOS process and additional layout rules the analog buffer design can be made with acceptable sensitivity for radiation damages [4].

2. Linearity. Nonlinearity of the analog buffer should be better

than linearity of HAL25 i.e. 1.5% for 2MIPS in 13MIP range.

3. Dynamic range. CMOS devices of the process are able to stand

maximum 2.5V, therefore power supply voltage cannot exceed this value. Output signal dynamic range of the analog buffer is enclosed within the power supply range and should approach the range with reasonable increasing of its power consumption. We expect to get at least 2V output dynamic range within the required nonlinearity tolerance.

4. Differential gain. The needed differential gain is a ratio of output

signal dynamic range over input signal dynamic range as follows

Gain=2V/(250uA/MIP 13MIP 110Ω) 5.6

5. Intrinsic electronic noise. Electronic noise of the analog buffer adds to the total

noise 4% when its noise level (standard deviation) 5 times lower than that of HAL25. Thus equivalent noise charge of the analog buffer must lower than 80e (0.5mV RMS at the output).

4. Common mode signal suppression factor.

The common mode signal suppression factor is determined by mismatch of the components in layout of the chip. It seems to be possible to reach value better than 1%.

5. Settling time.

Input signal for the analog buffer is a step, which must be settled to its nominal value within 100ns (1/read-out rate). Precision of the settling must be a few times better than the nonlinearity tolerance i.e. ≈ 0.3%

6. Power consumption.

To be able to estimate allowable level of power consumption we should take into account that an analog buffer must be in ON-state just during the time when the 12 front-end chips are being readout. This event occurs at each coming trigger i.e. every 1mS in average (1/trigger rate). Time we need to read-out 12 chips is

12 128channels 100ns/channel = 153us. Let us consider an analog buffer adding 10% to

power consumption of attached 12 front-end chips: P 153us/1000ms = 12chips 14.75mW/chip 10%,

this equation gives the value are looking for:

P 115mW, I=P/2.5V=46mA.

7. Differential output offset.

The differential output offset occurs due to mismatch of supposed to be identical transistors. We intend to keep it (standard deviation of distribution of the offsets) within 15mV.

The circuit.

Principal diagram of the analog buffer board is given

in Fig.2. Reference voltage sources (Vref_P-side and Vref_N-side) provide bias voltages for the current outputs of the front-end chips of each side. Load resistors (55Ω) convert the output current into voltage with proper termination of the Kapton cable. The capacitors (C, C1, C2, C3) decouple operating bias of the inputs of the analog buffer.

The analog multiplexer connects inputs of the differential amplifier to one of the board terminals (IN P-side or IN N-side). In between readout cycles, right sides of the decoupling capacitors are connected to a reference voltage (Vref) to avoid any voltage drift during this quiet state.

A fully complementary differential amplifier and an output stage form the operational amplifier (OPAMP). An external feedback circuit determines operational properties of OPAMP.

The inputs and the outputs of the OPAMP are self-biased to the Vref value (1/2 the supply voltage) by means of common mode feedback.

In order to ensure oscillation-free behavior, Miller compensation capacitors (Cm, Cm1) have been implemented in output stage.

Fig.2. Principal diagram of the analog buffer board.

The ALABUF chip. Top schematic of the ALABUF chip is given in

Appendix 1. The chip consists of two analog buffers with common enable control (BufEnable) and external voltage reference (Vref) terminals.

4Signals at terminals Sel1A, Sel1B Sel2A, Sel2B are

steering analog multiplexers for both channels. In our application the control signals are ac-connected to the outside. For the bias reason a special receiver circuit (CMOS_AC_in) with dc-hysteresis has been used (see Appendix 2).

Detail schematics of all the components used throughout are given in Appendix 3-10.

Layout of the ALABUF chip is plotted in Appendix 11 and the bond scheme is in Appendix 12.

For the chip bond pads assignment and applied signals specification look in Table5 (Appendix 13).

Table 1 shows main specifications of the ALABUF chip taken from the test results.

Table1.

Specifications. Number of channels 2 Nominal readout rate 10MHz

Current consumption from power supply

91mA (ON state) 10.4mA (OFF state)

Current consumption from reference voltage source

140uA

Single power supply (VDD) 2.5V Output dynamic range (at 1%

nonlinearity level) ±1.85V

Differential gain 5.66 Input referred noise 68uV RMS (60e)

Nonlinearity (within the specified dynamic range)

<1%

Settling time 20ns Common mode suppression

factor <0.7%

The design.

1. Analog miltiplexer design. The analog multiplexer is formed by a set of analog

switches (see Appendix 8) capable to connect input bond pads to either the OPAMP inputs or to a reference voltage (Vref). Zero-voltage threshold transistors constitute the analog switches. Signal size dependant transimpedance (R_ON) of the transistors adds to the input impedance of the OPAMP (1K) altering the overall gain and causing nonlinearity. We have chosen dimensions of the transistors in such a way that variations of theirs R_ON are confined to 10Ω within specified input dynamic range (±180mV) (see Fig.3). It means that analog switches related nonlinearity is limited to 1% as long as the variations are 100 time lower than input impedance of the OPAMP.

Fig.3. Transimpedance of the analog switches

as a function of input signal.

2. The output stage. In this application we intend to reach the maximum

swing of the output signal. Therefore the general-amplifier configuration (GA) is the most appropriate solution for our output stage [5]. In this configuration drains of the transistors (see Fig.4) could sweep in the full power supply range with the deduction of saturation voltage drops of upper and lower transistors i.e. Vsat M14

up to (2.5 - Vsat M15). The outputs of the stage have been biased to 1/2 VDD (1.25V) value to be able to equally drift in any direction.

Fig.4. Schematics of the output stage.

For the best efficiency we would prefer to choose

the quiescent current Iquies (current coming through the transistors when differential signal at the inputs is zero) to be much lower than the maximum load current (see Fig.5) i.e

Iload max >> Iquies. (Class-AB).

In this case the circuit consumes a little current if there is no differential input signal or it is quite small (Class-AB operation) [5]. On the other hand Class-AB operation has a few drawbacks. First, schematic solution of the Class-AB biasing is a subject to design. But the most significant is that the frequency compensation becomes very tricky to conduct. As long as current

Transimpedance (R_ON)

Ω

Input signal, V

-180mV +180mV

10Ω

5through output transistors and hence transconductance (gm) turn out very much dependant on the input signal size. That influences frequency poles position (as it will be shown later), thus results in different Phase Margins for small and large signals.

54

54

f x( )

f1 x( )

f x( ) f1 x( )

0

40 x Fig.5. The output stage. Class-AB operation. The currents as a function of the input differential signal.

Operation in Class-A (quiescent current is roughly

equal to maximum load current (see Fig.6)) does not give any problems with frequency compensation.

Iload

max ≈ Iquies. (Class-A)

For Class-A operation the transistor transconductance (gm) is much higher than that in Class-AB (quiescent current is larger). It is not changing considerably due to the signal size variations, providing stability of the related frequency poles and good bandwidth properties (see frequency compensation section below in this report).

We expect to meet specification requirement on current consumption with the output stage operating in Class-A at the same time avoiding all the problems just mentioned.

f2 x( )

f3 x( )

f2 x( ) f3 x( )

0

x Fig.6. The output stage. Class-A operation. The currents as a function of the input differential signal.

Output sweep range and the quiescent current

depend on dimensions of the output stage transistors (see Fig.7).

By using large transistors (p-channel ones with W=424.9u, L=0.28u and n-channel ones W=171.3u, L=0.28u) we reach sweep range of 2.2V while the current consumption is still within specification limit (2 Iquies. = 43.64ma).

We diminish the quiescent current by factor of two and loose 300mV of the sweep range by scaling down the transistors in two times (see Fig.7).

Fig.7. DC-sweep of the output stage. Equivalent small-signal circuit of the output stage is

given in Fig.8 where gm – CMOS transistor tranconductance, gds – CMOS transistor output conductance, Cgd – gate-to-drain capacitance,

+Iloadmax

-Iloadmax

Pch –transistor current

Quiescent current, Iquies.

+1.25V

Load current (Iload)

Input differential signal input+ - input-

+Iloadmax

Nch –transistor current

Quiescent current, Iquies.

+1.25V

Load current (Iload)

Input differential signal input+ - input-

-Iloadmax

Pch –transistor current

Nch –transistor current

Input differential signal, V input+ - input-

outputs+

outputs-

2.2V

1.9V

Pch tran. 424.9u/0.28u Nch tran. 171.3u/0.28u

Iquies. = 21.82ma

Pch tran. 212.5u/0.28u Nch tran. 85.65u/0.28u

Iquies. = 10.9ma

6Cgs – gate-to-source capacitance, Cdsub – drain-to-substrate capacitance. Differential gain of the circuit at low frequencies is:

Gosds

dif = (gm15+gm14)/(gds15+gds14+1/(0.5 110Ω)) =

= 4.5. For the differential signal frequency pole at the

output of the circuit is almost entirely determined by the load resistance (110Ω) and the load parasitic capacitance (we expect 2x10pf at the worse case) since the related values of the transistors are much lower (drain capacitances of the transistors are 2x572fF and their output conductances are 2x3.2mS). Thus, the roll-off frequency is:

fos-3db

dif= 2π [Cpar + Cdtot15+Cdtot14)]/ [gds15+gds14+1/(0.5 110Ω]-1 = 325.5MHz

Fig.8. Equivalent small-signal circuit of the output

stage. The circuit does not respond to common mode

signal in the same way as it does for differential one. That is due to the fact that both outputs swing synchronously without driving current through the load resistor (R_load). The load resistor becomes “invisible” for the outputs.

The common mode gain at low frequencies is as follows:

Gosds

com = (gm15+gm14)/(gds15+gds14) = 28.2.

The roll-off frequency for the common mode signal

is : fos

-3dbcom = 2π [Cpar + Cdtot15+Cdtot14)]/

[gds15+gds14]-1 = 49.7MHz Such a common mode response behavior does not

have negative influence on the circuit performance.

3. The differential amplifier.

A differential amplifier constitutes input stage of the OPAMP (see Fig.9). It has fully complementary

structure with identical transistors. The same bias current (Id) flows for corresponding transistors from upper (p-channel transistors) and lower parts (n-channel transistors). In order to keep identical value of transconductance (gm), p-channel transistors must be 3 wider than n-channel ones.

Fig.9. Schematics of the differential amplifier. On the base of mismatch consideration we can

specify size of the transistors. The mismatch of the differential pairs transistors (M803 vs M19, M814 vs M21) give an offset between the differential outputs. The standard deviation of mismatches in the inputs voltages is:

σ(δVin)= [σ(δVinpch)]2 + [σ(δVin

nch)]21/2, where

σ(δVinnch) is standard deviation in mismatches of

input voltages for n-channel transistors (M803 vs M19), σ(δVin

pch) is standard deviation in mismatches of input voltages for p-channel transistors (M814 vs M21).

In turn the deviations could be expressed as:

σ(δVinnch)=[MnV/(W•L)1/2]2+(Id/8Kn) [MnK/(W•L)1/2]1/2

(3.1) , where W, L are effective width and length of the transistors, Id is drain current, MnV,MnK ,Kn are constant of the process.

Differential input voltage mismatch as a function of

the width of the transistors is plotted in Fig.10 (transistor’s length is taken 0.320µm). Contribution to

7the overall mismatch on the part of p-channel transistors is much lower in comparison to that of n-transistors because of the 3 times larger area (see Fig.10). The smaller the width of the transistor the bigger the mismatch is. For the value of the width of 27µm we reach 3mV differential input mismatch.

0 10 20 30 40 500

0.002

0.004

0.006

0.008

0.01

1.032 103.

Gn w I0,( )

Gp w I0,( )

G w I0,( )

501 w

Fig.10 Differential input voltage mismatch as a

function of width of the transistors (L=0.320µm). The first item prevails in formula (3.1) therefore the

mismatch is almost independent on drain current. That let us vary the drain current optimizing other specifications of the design.

Mismatch of the feedback resistors (see Appendix 7) comes up in a non-zero differential output response to a common input signal. For the chosen type of the resistors (polycilicon) and their dimensions, 3σ matching tolerance is:

MM = (Sa•2• (W+L) + Ma2/W•L)1/2 ,where

W, L are width and length of the resistors, Sa, Ma are constants of the process. We have chosen dimensions of the resistors (1k is

15.14µm/3µm) in such a way to keep the mismatch at 1.3% level. That gives 4.7% of the output differential response to a common mode input signal and further converts in common mode rejection factor as low as below 1% (differential gain is 5.6).

Equivalent small-signal circuit of the differential amplifier is given in Fig.11, where

gout = gdsM20/M7 + gdsM27/M26 =21.5 mS is output

impedance of the differential amplifier,

gdsM20/M7 = (gds7•gds20)/(gm20+gds7+gds20) = 10.4uS is output impedance of cascode pair (M20/M7), gdsM27/M26=(gds26•ds27)/(gm27+gds27+gds26) =11.1uS output impedance of cascode pair (M27/M26),

Fig.11. Equivalent small-signal circuit of the

differentiall amplifier. Differential gain of the differential amplifier at low

frequencies is: Gda

dsdif

= (gm19+gm21)/(gout2) = 50dB Drain capacitors (Cdtot27+Cdtot20) (see Fig. 11) in

sum with gate capacitors of the output stage (see Fig.8) determine frequency pole together with the output impedance of the differential amplifier. The roll-off frequency of the pole is:

fda

-3dbdiff = 2π [(Cgs15+Cgs14+Cdtot27+Cdtot20) +

Gosds

dif (Cgd15+Cgd14+Cm)]/ [gout]-1 = = 1.3MHz (3.2)

4. Frequency response of the Analog buffer. Overall frequency response of the Analog buffer

contains both poles just mentioned. Since roll-off frequency of second pole (fda

-3dbdiff =1.3MHz) is much

lower than that of the first pole (fos-3db

dif =325.5MHz) it is dominant in the overall transfer function. Mutual position of the poles in frequency domain determines stability performance of the analog buffer.

In principle, a two poles operational amplifier with a feedback can fall into self-oscillation. The analog buffer turns to be oscillation free when phase difference between signal at the gate of the differential amplifier and the signal coming to the same point from the feedback side is less than 360° till amplitude gain is higher that unity (known as Phase Margin) (see Fig.12).

Figure 12 shows that without special measures Phase Margin of the analog buffer is 61.6°.

Width of the transistors, µm

Differential input

mismatch, V

Mismatch between p-channel transistors

Mismatch between n-channel transistors

Overall mismatch

27 µm

3mV

8

Fig.12. Differential feedback. Open loop characteristics.

Difference between signal at the gate of the differential amplifier and the signal coming to the same point from the feedback side. Cm=0fF. Phase Margin is 61.6°.

To improve the value we used Miller compensation

method [5]. In out design the MIMCAP capacitor (Cm=946fF) has been added to the output stage to provide local negative feedback. The feedback shifts the dominant pole further in low frequency region (see 3.2) and another pole to the high frequencies. By means of that the poles have been split in frequency domain and Phase Margin becomes 85.3° (see Fig.12).

Fig.13. Differential feedback. Open loop characteristics.

Difference between signal at the gate of the differential amplifier and the signal coming to the same point from the feedback side. Cm=946fF. Phase Margin is 83.5°.

On the other hand such a correction leads to

degradation of the speed performance of the analog buffer. Without the Miller capacitor open loop unity gain frequency is 660MHz, whereas with the capacitor it goes down to 358MHz (see Fig.14). Taking into account that differential gain must be 5.6, the cut-off frequency in the close feedback configuration becomes ≈50MHz (≈358MHz/5.6) and full settling time is ≈20ns (1/64MHz) (see Fig.15).

Fig.14. Differential Open loop gain of the analog buffer

as a function of frequency.

Fig.15. Closed loop configuration of the analog buffer. Differential transient response and frequency response.

Common mode signal is suppressed at the output of

the buffer by factor of –0.85 in wide frequency band (cut-off frequency is 202MHz) (see Fig.16).

Cm=0fF

Cm=946fF Unity gain

frequency is 660MHz, Cm=0fF

Unity gain frequency is 358MHz, Cm=946fF

Phase

Amplitude

Unity gain line Phase margin=61.6

Phase

Amplitude

Unity gain line

Phase margin=83.5

OutP

InP

InN

OutN

Settling time 20ns

InN

OutN

Cut-off frequency 50.7MHz

OutN, OutP

InN, InP

Cut-off frequency 202 MHz

9Fig.16. Closed loop configuration of the analog buffer.

Common mode transient response and frequency response.

5. Common mode feedback. Inputs of the analog buffer are AC-coupled to the

front-end electronics. Feedback circuit delivers DC-bias to the inputs from outputs of the buffer (see Fig.17). In order to keep the outputs at the middle of dynamic range (+1.25) we employed common mode feedback.

Fig.17. Schematic solution for the common mode

feedback. The common mode feedback has sufficient Phase

margin (74°) that keeps the circuit far away from oscillation break-down (see Fig.18).

Fig.18. Common mode feedback. Open loop

characteristics. Difference between signal at the gates of M1012 and M987 and the signal coming to the same point from the feedback side. Phase Margin is 74°.

Test results.

Recently we have received ALABUF chips from the multi-project submission (MWP6 2001/Q4). Results of the testing are presented further.

1. Power consumption.

The ALABUF chip current consumption is: measurements simulations

VDD bus (+2.5V)

91mA (ON state) 10.4mA (OFF state)

90.7mA (ON state) 10.3mA (OFF state)

Vref bus (+1.25V)

140µA 168µA

Fig.19. Experimental set-up to measure linearity and

dynamic range. For one chip the characteristics were measured

minutely and for the other just in a few points (see Fig 20).

Phase

Amplitude

Unity gain line

Phase margin=74

3. Linearity and dynamic range. Experimental set-up used to measure linearity and

dynamic range is given in Fig.19.

10

0 100 200 300 400 500 6000

500

1000

1500

2000

25002500

0

dOut2_2Bi

dOut2_1Bi

k x.

Out1_1Bj

Out1_2Bj

Out3_1Bj

Out4_1Bj

Out6_1Bj

Out7_1Bj

Out8_1Bj

Out9_1Bj

Out10_1Bj

Out11_1Bj

6000 dIN2Bi dIN2Bi, x, dj,

Fig.20. Measurements of linearity and dynamic range of the ALABUF chips.

500 900 1300 1700 2100 25000.05

0.04

0.03

0.02

0.01

0

0.01

0.02

0.05

L2_2Bi

L2_1Bi

2500500 5.66dIN2B.( )i 5.66dIN2B.( )i, 1.85,

Fig.21. Linearity curve for the measured channels

(1A,2A) of chip#1. The measurements show dynamic range at the level

of 1.85V (see Fig.21) within 1% nonlinearity, whereas simulations give value of 2.04V (see Fig.22, 23)

Fig.22. Simulations of linearity and dynamic range of the

ALABUF chips.

Fig.23. SPICE simulations. Linearity curve. Diversity in differential gain between the tested

chips is hardly visible within precision of the measurements (≈0.5%).

3. Differential transient response and settling time.

Measured differential transient response is given in Fig.24 and 25. Thanks to sufficient phase margin (83.5°) there no overshoots or undershoots noticeable. Settling time is 20ns as it the simulations predicted (see Fig. 25).

Input differential signal, InP-InN, mV

Output differential signal,

OutP-OutN mV

Chip#2, channel 1B

Chip#2, channel 2B 5.66 (InP-InN)

Chip#1 …Chip#11

Output differential signal, OutP-OutN, mV

Linearity [OutP-OutN-

5.66*(InP-InN)]/ [5.66*(InP-InN)]

1.85V

5.6 (InP-InN)

OutP-OutN

361mV

Input differential signal, InP-InN, mV

2.04V

Input differential signal, InP-InN, mV

-1%

-1%

361mV

Linearity [OutP-OutN-

5.66*(InP-InN)]/ [5.66*(InP-InN)]

+1%

-1% 1% level

11

Fig.24. Measurements. Differential transient response of

the ALABUF chip.

Fig.25. Measurements. Differential transient response of

the ALABUF chip.

Fig.26. SPICE Simulations. Differential transient

response of the ALABUF chip

4. Common mode transient response. The measured common mode response is plotted in

Fig.27. The leading edge of the outputs is very steep ( ≈5ns) therefore the settling is a bit distorted by nonideal tracing on the test board (see Fig.27). Such a fast settling is an evidence that the common mode suppression is valid in the wide frequency band (cut-off frequency is ≈200MHz). Unfortunately, due to lack of the balance between the probes, it is not possible to measure mismatch between the outputs precisely. Merely we can give the estimation that differential response to a common mode GainCM signal is below 4% (for nine chips out of ten). That yields common mode rejection factor (CMRF)

CMRF= GainCM/GainDIFF < 4% /5.6 ≈ 0.7%

Fig.27. Measurements. Ttransient response to a common

mode signal of the ALABUF chip. In simulation the common mode response looks very

similar to the measured one but without mismatch between the outputs (see Fig 28).

Fig.28. Simulations. Transient response to a common

mode signal of the ALABUF chip.

InP, Ch1

InN, Ch2

OutN, Ch3

OutP, Ch4

OutP, Ch4

InP, Ch1

InN, Ch2

OutN, Ch3

Settling time 20ns

OutP

InP

InN

OutN

InP=InN, Ch2

OutP, Ch4 OutN, Ch3

OutN-OutN, Math Nonideality of the

test board

InP=InN

OutP=OutN

12

5. Intrinsic electronic noise. Electronic noise of the analog buffer have been

measured by MATH facilities of the digital scope as follows:

Noise = (Noise2Σ - Noise2

∗ )1/2 = 385µV RMS, where

Noise∗ - noise at the scope without the buffer NoiseΣ - total noise at the scope. Consider the full dynamic range is 1.85V (13 MIPS)

and 1MIP is 22000e, the intrinsic noise is Noise = 2.7 10-3 MIP = 60e.

6. Differential output offset.

Values of voltage difference between the outputs of the ALABUF chip at quiescent state have been measured over 20 channels (10 chips). The values are given in Table 2. Due to insufficiency of the data we are not capable to derive statistic parameters. The only conclusion could be drawn is that standard deviation is about 7mV and mean value is close to zero.

Table 2. Differential output offsets.

Chip number Channel number Differential offset value

1 -7mV 1 2 -10mV 1 +6.7mV 2 2 +1.4mV 1 -5.2mV 3 2 -3.5mV 1 -14.5mV 4 2 -14.4mV 1 -3.2mV 6 2 +7.2mV 1 +5.2mV 7 2 -5.9mV 1 -10.1mV 8 2 5mV 1 -2.9mV 9 2 +16.4mV 1 -3.6mV 10 2 -7.6mV 1 +3.3mV 11 2 -16mV

7. Common mode output offset.

The common mode output offset characterizes self-biasing performance of the circuit. The performance is sensitive to the shift and spread of the transistors parameters. The testing shows that for all the chips the common mode bias is shifted down to ≈ 1.227V (instead

of 1.25V) (see Table 3). Besides, we notice spread the values in range ±7mV.

Table3. Common mode output offsets.

Chip number Channel number Differential offset value

1 1.228V 1 2 1.224V 1 1.227V 2 2 1.235V 1 1.225V 3 2 1.224V 1 1.223V 4 2 1.222V 1 1.228V 6 2 1.232V 1 1.229V 7 2 1.229V 1 1.221V 8 2 1.234V 1 1.221V 9 2 1.222V 1 1.212V 10 2 1.221V 1 1.229V 11 2 1.226V

8. Testing of the control circuit.

As it was already described above in this report, the ALABUF chip has a set of functionalities which are to be controlled.

Figure 29 demonstrates how Enable-Disable function works. The chip does not show up outputs when BufEnable control goes to ground level. Transition time is less that 100ns.

Fig.29. Testing of Enable-Disable functionality of the ALABUF chip.

Disabling Enabling

BufEnable

OutP

OutN

13 Operation of the channel selection functionality is

shown in Fig.30. The output signal are there if the Sel2A is ON (the Sel2A signal is AC-coupled to the chip). Transition takes less than 100ns.

Fig.30. Testing of the channel selection functionality of

the ALABUF chip. Figure 31 shows selection functionality when both

Sel2A and Sel2B signals are coming simultaneously. Transition takes less than 100ns.

Fig.31. Testing of the channel selection functionality of

the ALABUF chip. Sel2A and Sel2B are coming simultaneously.

The _ResetAC signal sets the signal at the Sel2A

pad of the chip to certain state (OFF). This functionality allows to ensure the state right after switching power on the chip. Transition occurs within 100ns (see Fig.32).

Fig.32. Testing of the _ResetAC functionality of the ALABUF chip.

Out2P

Out2N

_ResetAC

Sel2A

The channel is selected

The channel is unselected

Out2P

Out2N

The channel is selected

The channel is reset

_ResetAC

Sel2A outside the chip

Sel2A inside the chip

Out2P

Out2N

The channel is selected

The channel is unselected

Sel2A

Sel2B

14

Conclusion We have designed and successfully tested analog

buffer chip (ALABUF) with multiplexing, disabling and reset functionalities for the ALICE SSD detector. The chip is implemented in 0.25µ CMOS process. Testing results show good agreement with simulations. The following specifications have been disclosed (see Table 4).

Table4. Specifications.

Number of channels 2 Nominal readout rate 10MHz

Current consumption from power supply

91ma (ON state) 10.4ma (OFF state)

Current consumption from reference voltage source

140uA

Single power supply (VDD) 2.5V Output dynamic range (at 1%

nonlinearity level) ±1.85V

Differential gain 5.66 Input referred noise 60e

Nonlinearity (within the specified dynamic range)

<1%

Settling time 20ns Common mode suppression

factor <0.7%

Differential offsets ±7mV Common mode offsets -23mV±7mV

Enable-to-disable transition time

<100ns

Selected-to-unselected transition time

<100ns

Reset transition time <100ns In the forthcoming submission we foresee to design

on-chip reference source and modify schematics of the enabling functionality with the purpose to diminish the leakage current (140 uA).

References. [1] D. Bonnet et al, The Hal25 Front-End Chip for

the ALICE Silicon Strip Detectors, 7th Workshop on Electronics for LHC Experiments, CERN 2001-005, CERN/LHCC/2001-034, pp. 76-80, 22 Oktober 2001.

[2] R. Kluit et al, Design of ladder EndCap

electronics for the ALICE ITS SSD, 7th Workshop on Electronics for LHC Experiments, CERN 2001-005, CERN/LHCC/2001-034, pp. 47-51, 22 Oktober 2001.

[3] ALICE collaboration, Technical Design Report

of the Inner Tracking System (ITS), CERN/LHCC 99-12, ALICE TDR 4 , pp.175-199, 18 June 1999.

[4] P.Jarron, A.Paccagnella, 3rd RD49 Status Report

Study of the Radiation Tolerance of ICs for LHC, LEB Status Report/RD49, CERN/LHCC 2000-003, 13 January 2000.

[5] Johan H.Huijsing, OPERATIONAL

AMPLIFIERS. Theory and Design, KLUWER ACADEMIC PUBLISHERS, 2 Oktober 2000.

15

Appendix 1. Top schematic of the ALABUF chip.

16

Appendix 2.

Schematics of the CMOS_AC_ In block.

Appendix 3.

Schematics of the IB1 block (digital input pad).

.

17

Appendix 4.

Schematics of the oiinv block (inverter).

Appendix 5. Schematics of the E_INV2 (inverter).

Appendix 5. Schematics of the AnaPadProt block (analoque input/output pad).

18

Appendix 6. Schematics of the Half_of_the_new_buffer block.

19

Appendix 7. Schematics of the new_buffer_connected block.

20

Appendix 8. Schematics of the switches block (analog multiplexer).

Appendix 9.

Schematics of the S2Dtx_0 block (singl- to-differential converter).

Appendix 10.

Schematics of the invtx_0 block (inverter).

21

Appendix 11. Layout of the ALABUF chip .

22

Appendix 12. Bond scheme of the ALABUF chip

23

Appendix 13. Table5.

Bond pads assignment and applied signal specification of the ALABUF chip . Number

of the pad Name of the

pad Type Function Way of

coupling Nominal

value/tolerance 1 Vref analog reference voltage DC 1.25V/±50mV 2 In2BN analog negative input of channel#2

(controlled by analog switch B) AC

3 In2BP analog positive input of channel#2 (controlled by analog switch B)

AC

differentially (In2BP-In2BN) ±360mv (linear

range). Operating

point=1.25V 4 In2AN analog negative input of channel#2

(controlled by analog switch A) AC

5 In2AP analog positive input of channel#2 (controlled by analog switch A)

AC

differentially (In2AP-In2AN) ±360mv (linear

range) Operating

point=1.25V 6 vdd! analog supply voltage DC 2.5V±100mV 7 gnd! analog ground DC 0V 8 Sel2A digital control of analog switch A of

channel #2 AC leading edge of

transition from 2.5V to 0V

9 Sel2B digital control of analog switch B of channel #2

AC leading edge of transition from

2.5V to 0V 10 Out2N analog Negative output of channel #2 DC/AC Operating

point=1.25V 11 Out2P analog Positive output of channel #2 DC/AC Operating

point=1.25V 12 BufEnable digital enable control DC 2.5V 13 _ResetAC digital reset of the controls of all the

analog switches DC 2.5V

14 Out1P analog Positive output of channel #1 DC/AC Operating point=1.25V

15 Out1N analog Negative output of channel #1 DC/AC Operating point=1.25V

16 Sel1B digital control of analog switch B of channel #1

AC leading edge of transition from

2.5V to 0V 17 Sel1A digital control of analog switch A of

channel #1 AC leading edge of

transition from 2.5V to 0V

18 gnd analog ground DC 0V 19 vdd analog supply voltage DC 2.5V±100mV 20 In1AP analog positive input of channel#1

(controlled by analog switch A) AC differentially

(In1AP-In1AN)

24

21 In1AN analog negative input of channel#1 (controlled by analog switch A)

AC ±360mv (linear range)

Operating point=1.25V

22 In1BP analog positive input of channel#1 (controlled by analog switch B

AC

23 In1BN analog negative input of channel#1 (controlled by analog switch B

AC

differentially (In1BP-In1BN) ±360mv (linear

range) Operating

point=1.25V 24 gnd analog ground DC 0V