Alcatel-Lucent OmniPCX EnterpriseCommunication Server

UA32/eUA32

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Alcatel, Lucent, Alcatel-Lucent and the Alcatel-Lucent logo are trademarks ofAlcatel-Lucent. All other trademarks are the property of their respectiveowners.

The information presented is subject to change without notice.

Alcatel-Lucent assumes no responsibility for inaccuracies contained herein.

Copyright © 2012 Alcatel-Lucent. All rights reserved.

The CE mark indicates that this product conforms to the following CouncilDirectives:- 2004/108/EC (concerning electro-magnetic compatibility)- 2006/95/EC (concerning electrical safety)- 1999/5/EC (R&TTE)

Chapter 1Hardware description

The UA 32 board, overview ................................................................. 1.1

The eUA32 board, overview ................................................................ 1.1

Environment ............................................................................................. 1.1

Functional units ...................................................................................... 1.2

Functional units ............................................................................................. 1.3

UA modules ................................................................................................... 1.4

Common part ................................................................................................. 1.6

Power supply ................................................................................................. 1.7

Maximum transmission range ........................................................................ 1.8

Chapter 2Hardware configuration

Reference .................................................................................................. 2.1

Overview .................................................................................................... 2.1

Meaning of LEDs on UA32 and eUA32 boards ............................ 2.1

Meaning ......................................................................................................... 2.2

Cadence (rate) ............................................................................................... 2.2

0-1

Chapter 3External connections

Connection ............................................................................................... 3.1

Board output pins .................................................................................. 3.1

0-2

1.1 The UA 32 board, overview

The new version of the UA32 board can be used as from R4.2, and is used to connect 32 setsand UA terminals such as:

- UA Reflexes sets, with or without an S0/V24/PC option.

- FBC attendant console.

- IBS.

- V24, S0, CTI or analog Terminal Adapters (TAs).

The new UA32 board has been upgraded as follows:

- A new transmitter/receiver called OSIRIS (Octal UA transmitter/receiver).

- A new UA interface based on QUAD UA line transformers and from the Octal E.M.Cfiltering system.

- A new common C1NV part.

- A new CB8 power supply.

UA32 board configuration is described in the UA32/eUA32 - Hardware configuration .

UA32 board connection is described in the UA32/eUA32 - External connections .

1.2 The eUA32 board, overview

The eUA32 board can be used as from R5.1. It has the same basic characteristics as theUA32 board.

However, whereas the UA32 board requires a specific license, the less costly eUA32 boardrequires none, but all sets attached to it must have a license.

In other words, you can use:

- Either, a UA32 board with no set licenses,

- Or, an eUA32 board with a license for each set declared on the board.

The two boards are not interchangeable. The board must be declared as a UA32 or eUA32board in management.

Note:

In the rest of this document, all sections are applicable both to the UA32 board and the eUA32 board.

1.3 Environment

1-1

Figure 1.1: Input/Output diagram - UA32 board

1.4 Functional units

Chapter 1

1-2

Figure 1.2: Functional block diagram - UA32 board

1.4.1 Functional units

The board consists of the following different units:

1-3

- 4 UA modules.

- 1 common C1NV part.

- 1 CB8 power supply converter.

1.4.2 UA modules

These modules provide the interface between the UA and PCM links of the board.

Figure 1.3: UA module

Each UA module consists of:

- 1 OSIRIS circuit (Octal UA transmitter/receiver) that, for transmission, has the samefunction as the two CATS (UA quad transmitter/receiver) used for UA16/32 boards.

Chapter 1

1-4

- 4 power supply commands.

- 2 UA quad transformers.

- 8 E.M.C circuits.

The OSIRIS interface

This transmitter/receiver simultaneously controls eight UA lines UA in ping-pong mode. Itprovides eight transparent transmissions (8x64 Kbits/s) in full duplex. In ping-pong mode, thefour UA interface bytes are directly integrated in the frame without any modification to itscontents.

The UA link presents a 125 µs frame with the following format:

Channels B1, B2 and B3 carry both voice and data from the UA terminal or from the S0 busconnected to the set.

The SIG channel carries signalling from the dedicated UA set and, where appropriated, the Dchannel of the the S0 bus connected to the UA terminal.

The transmission of four 64 Kbits/s channels (B1, B2, SIG and B3) is followed by reception offour 64 Kbits/s channels. A hold time (TG = 9.3 µs approx.) and of propagation in the crossedpair (TP= 7µs approx.) separates the two phases, each beginning with an SYNsynchronization bit.

Four registers, addressed by the processor of the common C1NV part via the series port,synchronize data between the UA links and the PCM link.

Clock signal control is included in the OSIRIS interface.

Power supply commands

A current limiter controls the intensity of current to UA lines. Each limiter supplies 2 UA lineswith a maximum current of 300 mA for the two lines.

When the coupler is installed, a command from the common C1NV part via the OSIRISinterface commands the sequential establishment of the two-line currect in 2 lines. Thisfunction is used to limit the current of the -48V power supply during the coupler startup phase.

UA quad line transformers

Each quad transformer converts the 0V/3.3V signal into a -2.5V/2.5V signal, that is sent on theUA line.

Two UA quad line transformers connect on a PCM link, each quad handles 4 UA lines.

E.M.C

The purpose of the E.M.C circuit is to minimize the disturbance caused by cablingelectromagnetic fields and also to render UA interfaces insensitive to:

1-5

- Rapid transition disturbance signals.

- Electrostatic discharges.

The board and its line interfaces are protected against short-circuits and overvoltages.

1.4.3 Common part

The common C1NV part interfaces the UA board with other system boards.

The main parts are:

- a C1 like unit, which ensures:• Switching.• Generation of clock signals.• Signaling for CPU and line busy state.• Tone generation.

- A CPU, comprising:• An ARM microprocessor running at 32.768 MHz.• RAM (external to C1NV).• A FLASH EEPROM (external to C1NV).

- A DSP microprocessor, ensuring digital signal processing.

- Input/Output ports.

Figure 1.5: Common part

The common C1NV part:

- Generates the following clock signals:• 8 kHz for frame synchronization.• 4 MHz and 16 MHz signals for the OSIRIS interface.

Chapter 1

1-6

• 512kHz (from the 16 MHz signal) for CB8 power supply synchronization.

Note:If there is no main clock signal, these clock signals are maintained.

- Communicates with the OSIRIS interface, via the synchronous serial port (SSI), at a speedof 4 MHz.

The asynchronous serial port (ASP) is used to test the board by the UART connection via anRS232 converter external to the board.

The four PCMs have the same configuration.

PCM 0 frame

PCM 1, PCM 2, and PCM 3 have the same type of frame.

Each PCM is connected to two UA quad line transformers and thus carries the four TSs (B1,B2, SIG, B3) of each of the 8 UA links.

In addition to the system interface function, the ARM processor processes level 2 of the UAlink.

1.4.4 Power supply

Board power supply

1-7

Figure 1.7: CB8 power supply

From the -48V power supply, the CB8 converter, which is synchronized by the 512kHz signalfrom C1NV, provides the 3.3 V (OSIRIS) and 5 V (C1NV crystal) voltages required for theboard to function.

The board supplies -48V to the UA lines, via the line interfaces. When the board is installed,the microprocessor commands the current limiters so that the line power supplies startsequentially.

A 5 A fuse, installed on the -48V input, protects all limiting circuits.

The DEMx signal determines startup delay.

1.4.5 Maximum transmission range

The maximum transmission range depends on the type of cable used and is given in thefollowing table:

Cable type Country Maximum range

SYT0.5 France 800 m

SYT0.6 France 800 m

278 France 1,200 m

ITT 26626 BBEB DEBE Belgium 1,200 m

TsR-R Italy 1,200 m

Chapter 1

1-8

2.1 Reference

UA32 board reference: 3BA23242AA

eUA32 board reference: 3BA23266AA

2.2 Overview

Figure 2.1: View of the UA32 board

There are no straps on the board.

2.3 Meaning of LEDs on UA32 and eUA32 boards

2-1

2.3.1 Meaning

table 2.1: Summary tableLED Meaning

CPU (green LED) Processor activity indicator

BSY (orange LED) UA line activity indicator

2.3.2 Cadence (rate)

For the CPU LED:

table 2.2: CPU LEDCadence (rate) Meaning

On and steady Initialization in progress

100 ms (on)/ 1 s (off) Loading in progress

10 ms (on)/ 10 ms (off) Boot flash update

300 ms (on)/ 300 ms (off) CPU standby

8 x (900 ms (on)/ 600 ms (off)/1 s (off) RAM test error

8 x (300 ms (on)/ 600 ms (off)/1 s (off) Checksum error

Chapter 2

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3.1 Connection

The UA32 board is positioned on an interface position in the ACT shelf.

Figure 3.1: connecting UA32 boards

If the connection is:

- by cable: when connecting to the splitter, use Type 1 cables with or without a distributionmodule (see TY1 64PTSDIN cable - Cable without Module or TY1 64PTSDIN cable -Cable with Module),

- per patch panel (VH cabinet only): in this case the connection is made directly by using the32 ports patch panel (see Patch Panel - 32 ports module - 32 ports module).

3.2 Board output pins

3-1

C B A

1 b 1 GND a 1

2 b 2 GND a 2

3 b 3 GND a 3

4 b 4 GND a 4

5 b 5 GND a 5

6 b 6 GND a 6

7 b 7 GND a 7

8 b 8 GND a 8

9 b 9 GND a 9

10 b 10 GND a 10

11 b 11 GND a 11

12 b 12 GND a 12

13 b 13 GND a 13

14 b 14 GND a 14

15 b 15 GND a 15

16 b 16 GND a 16

17 b 17 GND a 17

18 b 18 GND a 18

19 b 19 GND a 19

20 b 20 GND a 20

21 b 21 GND a 21

22 b 22 RTS* a 22

23 b 23 GND a 23

24 b 24 GND a 24

25 b 25 GND a 25

26 b 26 GND a 26

27 b 27 GND a 27

28 b 28 TX* a 28

29 b 29 RX* a 29

30 b 30 GND a 30

31 b 31 GND a 31

32 b 32 GND a 32

* reserved for factory tests.

Chapter 3

3-2