all program

7/25/2019 All Program

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B.1 FSM (Finite State Machine) sortir benda

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity fsm_mesinsortir is

port

( clk: in std_logic; t_start, t_reset : in std_logic; s_utama : in std_logic; s_kabin : in std_logic; stoper_low, stoper_med, stoper_high : in std_logic;

!"#$ : in std_logic; s_limit : in std_logic_%ector (& downto '; m_kon%eutama : out std_logic_%ector (1 downto '; m_kon%elow : out std_logic_%ector (1 downto ';

m_kon%emed : out std_logic_%ector (1 downto '; m_kon%ehigh : out std_logic_%ector (1 downto '; m_lifter : out std_logic_%ector (1 downto '; m_kabin : out std_logic_%ector (1 downto ';end fsm_mesinsortir;

architecture beha%ioral of fsm_mesinsortir is

type state is ( state_' , state_1, state_&, state_), state_4, state_*, state_6, state_+, state_, state_-,state_1', state_11, state_1& ;signal current_state, net_state : state;

beginprocess (clk isbegin

if ( clk/e%ent and clk 0 /1/ thencurrent_state 0 net_state ;

end if ;end process ;

process (current_state, t_start, s_utama, s_limit, s_kabin, stoper_low, stoper_med, stoper_high, !"#$isbegincase (current_state is

when state_' 02 m_kon%eutama 03''3; m_kabin 03''3; m_lifter 03''3; m_kon%elow 03''3; m_kon%emed 03''3; m_kon%ehigh 03''3; if stoper_low 0 /'/ then

net_state 0 state_&; elsif stoper_low 0 /1/ then

net_state 0 state_1; else


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net_state 0 state_'; end if;

when state_1 02 if stoper_low 0 /'/ thennet_state 0 state_';

elsenet_state 0 state_1;

end if; m_lifter 03'13; lift turun

when state_& 02 if (t_start 0 /'/ and s_utama 0 /'/ thennet_state 0 state_);

elsif t_reset 0 /'/ thennet_state 0 state_1;

elsenet_state 0 state_&;

end if; m_lifter 03''3;

when state_) 02 if s_limit 0 3'''3 then 11' ( limit high 0 1 , limit med 0 1, limit low 0 '

net_state 0 state_4; benda high

elsif s_limit 0 31''3 then 1'' ( limit high 0 1, limit med 0 ', limit low 0 'net_state 0 state_*; benda medium

elsif s_limit 0 311'3 then ''' ( semua limit sensor nyalanet_state 0 state_6; benda low

elsenet_state 0 state_);

end if; m_kon%eutama031'3;

( state_) 0 proses sortir berlangsung

when state_4 02 if s_kabin 0 /'/ then benda high

net_state 0 state_+; else

net_state 0 state_4;

end if; m_kon%eutama031'3; m_kabin031'3;

when state_* 02 m_kabin031'3;

if s_kabin 0 /'/ then benda mediumnet_state 0 state_;

elsenet_state 0 state_*;


when state_6 02 m_kabin031'3;

if s_kabin 0 /'/ then benda low

net_state 0 state_1'; elsenet_state 0 state_6;


when state_+ 02 if !"#$ 0 /1/ thennet_state 0 state_1&; benda high

elsenet_state 0 state_+;

end if;


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m_kabin031'3;m_kon%elow031'3;

m_kon%eutama03''3;

when state_ 02 if stoper_med 0 /'/ thennet_state 0 state_-; benda medium

else

net_state 0 state_; end if; m_lifter031'3; lift naik ke lt & m_kon%eutama03''3; m_kabin03''3;

when state_- 02 m_lifter03''3; lift berhenti

if !"#$ 0 /1/ then benda mediumnet_state0 state_1&;

elsenet_state0 state_-;

end if; m_kabin031'3;

m_kon%emed031'3;

when state_1' 02 if stoper_high 0 /'/ then

net_state0 state_11; benda high else

net_state0 state_1'; end if; m_lifter031'3; lift naik ke lt ) m_kon%eutama03''3 m_kabin03''3;

when state_11 02 m_lifter03''3;

if !"#$ 0 /1/ then benda highnet_state 0 state_1&;

else

net_state 0 state_11; end if; m_kabin031'3;

m_kon%ehigh031'3;

when state_1& 02 net_state 0state_'; end of the line

end case ;end process ;

end beha%ioral ;

B.2 Clock Divider


entity clock_di%ider is port ( clockin : in std_logic;

clockout_1s : out std_logic;


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clockout_setengah_s : out std_logic ;end clock_di%ider;

architecture beha%ioral of clock_di%ider is

signal clk1, clk&: std_logic;

signal satu_detik :std_logic_%ector(&* downto ';signal setengah_detik :std_logic_%ector(1* downto ';

begin

process(clockin, satu_detik, setengah_detik begin

if clockin/e%ent and clockin0/1/ then

satu_detik 0 satu_detik 5 1; setengah_detik 0 setengah_detik 5 1;

end if;

clk1 0 satu_detik(&*; clk& 0 setengah_detik(1*;

clockout_1s 0 clk1; clockout_setengah_s 0 clk&;

end process;end beha%ioral;

B.3 Seven Segment

library !###;use !###.7_89!_1164.all;use !###.7_89!_?!?#7.all;

entity se%en_segm isport (

clock,clk+, t_reset, s_utama_rst : in std_logic;_9>?_89@, _9>?_"#7, _9>?_=!= : in std_logic;7_out_< : out std_logic_%ector() downto '7_out_A : out std_logic_%ector() downto ';7_out_ : out std_logic_%ector() downto ';com : out std_logic_%ector(& downto ';

end se%en_segm;

architecture beha%ioral of se%en_segm issignal cnt1 : integer range ' to &;signal satuan, puluhan, ratusan : integer range ' to -;

beginprocess (clock, _9>?_89@, _9>?_"#7, _9>?_=!=, t_reset isbegin


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if(clock/ e%ent and clock 0 /1/ thenif(_9>?_89@ 0 /'/ then

if satuan 0 -then

satuan 0 -;else

satuan 0 satuan51;end if;

elsif(_9>?_"#7 0 /'/ thenif puluhan 0 - then puluhan 0 -;else

puluhan 0 puluhan51;end if;

elsif(_9>?_=!= 0 /'/ then

if ratusan 0 - then ratusan 0 -;else ratusan 0 ratusan51;end if;

elsif (satuan 0 - and s_utama_rst 0/'/ thensatuan 0 ';

elsif (puluhan 0 - and s_utama_rst 0/'/ thenpuluhan 0 ';

elsif (ratusan 0 - and s_utama_rst 0/'/ thenratusan 0 ';

elsif(t_reset 0/'/ thensatuan 0 ';

puluhan 0 ';ratusan 0 ';

end if;end if;

end process;

process(clk+beginif clk+ /e%ent and clk+ 0 /1/ then

if cnt1 0 & then cnt1 0 ';else cnt1 0 cnt1 5 1;

end if;

end if;end process;

process(cnt1beginif cnt1 0 ' then

com 0 3'113;if satuan 0 ' then 7_out_< 0 3''''3;elsif satuan 0 1 then 7_out_< 0 3'''13;


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elsif satuan 0 & then 7_out_< 0 3''1'3;elsif satuan 0 ) then 7_out_< 0 3''113;elsif satuan 0 4 then 7_out_< 0 3'1''3;elsif satuan 0 * then 7_out_< 0 3'1'13;elsif satuan 0 6 then 7_out_< 0 3'11'3;elsif satuan 0 + then 7_out_< 0 3'1113;elsif satuan 0 then 7_out_< 0 31'''3;

elsif satuan 0 - then 7_out_< 0 31''13;end if;

elsif cnt1 0 1 thencom 0 31'13;if puluhan 0 ' then 7_out_A 0 3''''3;elsif puluhan 0 1 then 7_out_A 0 3'''13;elsif puluhan 0 & then 7_out_A 0 3''1'3;elsif puluhan 0 ) then 7_out_A 0 3''113;elsif puluhan 0 4 then 7_out_A 0 3'1''3;elsif puluhan 0 * then 7_out_A 0 3'1'13;elsif puluhan 0 6 then 7_out_A 0 3'11'3;elsif puluhan 0 + then 7_out_A 0 3'1113;elsif puluhan 0 then 7_out_A 0 31'''3;elsif puluhan 0 - then 7_out_A 0 31''13;

end if;

elsif cnt1 0 & thencom 0 311'3;if ratusan 0 ' then 7_out_ 0 3''''3;elsif ratusan 0 1 then 7_out_ 0 3'''13;elsif ratusan 0 & then 7_out_ 0 3''1'3;elsif ratusan 0 ) then 7_out_ 0 3''113;elsif ratusan 0 4 then 7_out_ 0 3'1''3;elsif ratusan 0 * then 7_out_ 0 3'1'13;elsif ratusan 0 6 then 7_out_ 0 3'11'3;elsif ratusan 0 + then 7_out_ 0 3'1113;elsif ratusan 0 then 7_out_ 0 31'''3;elsif ratusan 0 - then 7_out_ 0 31''13;

end if;

end if;


B.4 Counter Timer


entity ?_!"#$ isport ( clk,input_&s : in std_logic; output_&s : out std_logic

;end ?_!"#$;

architecture beha%ioral of ?_!"#$ is


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signal count_&s : integer range ' to &;

begin

process (input_&s, clk, count_&s isbegin

if (input_&s 0 /1/ then

if (clk/ e%ent and clk 0 /1/ thenif (count_&s 0 &thencount_&s 0 ';output_&s 0 /1/;elsecount_&s 0 count_&s51;output_&s 0 /'/;end if;

end if;elseoutput_&s 0 /'/;

end if;end process;

end beha%ioral;

B.5 FSMHolding

library ieee ;use ieee.std_logic_1164.all ;

entity B"_=987!? isport

( 8C, $## : !? 7_89!;_9>?_89@, _9>?_"#7, _9>?_=!= : !? 7_89!;9>_!"#$1, 9>_!"#$&, 9>_!"#$) : 9> 7_89!

;end B"_=987!? ;

architecture beha%ioral of B"_=987!? is

type state1 is ( state1_' , state1_1 ;type state& is ( state&_' , state&_1 ;type state) is ( state)_' , state)_1 ;

signal present_state1 , net_state1 : state1 ;signal present_state& , net_state& : state& ;signal present_state) , net_state) : state) ;

beginprocess ( 8C, present_state1, present_state&, present_state) isbegin

if ( 8C /e%ent and 8C 0 /1/ then

present_state1 0 net_state1 ;present_state& 0 net_state& ;present_state) 0 net_state) ;

end if ;

end process ;


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process (present_state1 , _9>?_89@, $## isbegin

case (present_state1 iswhen state1_' 02 9>_!"#$1 0 /'/;

if _9>?_89@ 0 /'/ then

net_state1 0 state1_1 ;else net_state1 0 state1_' ;end if ;

when state1_1 02 9>_!"#$1 0 /1/;if $## 0/1/ then

net_state1 0 state1_' ;

elsenet_state1 0 state1_1 ;

end if ;


process (present_state&, _9>?_"#7, $## isbegin

case (present_state& iswhen state&_' 02 9>_!"#$& 0 /'/;

if _9>?_"#7 0 /'/ thennet_state& 0 state&_1 ;

else net_state& 0 state&_' ; end if ;

when state&_1 02 9>_!"#$& 0 /1/; if $## 0/1/ then

net_state& 0 state&_' ; else

net_state& 0 state&_1 ; end if ;


process (present_state) , _9>?_=!=, $## isbegin

case (present_state) iswhen state)_' 02 9>_!"#$) 0 /'/;

if _9>?_=!= 0 /'/ thennet_state) 0 state)_1 ; else net_state) 0 state)_' ; end if ;

when state)_1 02 9>_!"#$) 0 /1/; if $## 0/1/ then

net_state) 0 state)_' ; else

net_state) 0 state)_1 ;


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end if ;end case ;end process ;end beha%ioral ;

B.6 F_DIF


entity B_7!B is port ( clk : in std_logic;

perdetik : out std_logic; lk+seg : out 7_89!;

;end B_7!B;

architecture beha%ioral of B_7!B is

signal clk1, clk&: std_logic;signal satu_detik :std_logic_%ector(&4 downto ';signal setengah_detik :std_logic_%ector(1* downto ';

begin

process(clk, satu_detik, setengah_detik begin

if clk/e%ent and clk 0/1/ thensatu_detik 0 satu_detik 5 1;setengah_detik 0 setengah_detik 5 1;

end if; clk1 0 satu_detik(&4;

clk& 0 setengah_detik(1*;

perdetik 0 clk1;lk+seg 0 clk&;


B.7 BCD A

library ieee;use !###.7_89!_1164.


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if 7_in_< 0 3''''3 then 7_out_< 0 3''''''13; 'elsif 7_in_< 0 3'''13 then 7_out_< 0 3'11'1113; 1elsif 7_in_< 0 3''1'3 then 7_out_< 0 31''''1'3; &elsif 7_in_< 0 3''113 then 7_out_< 0 3''1''1'3; )elsif 7_in_< 0 3'1''3 then 7_out_< 0 3'11'1''3; 4elsif 7_in_< 0 3'1'13 then 7_out_< 0 3''11'''3; *

elsif 7_in_< 0 3'11'3 then 7_out_< 0 3'''1'''3; 6elsif 7_in_< 0 3'1113 then 7_out_< 0 3'11''113; +elsif 7_in_< 0 31'''3 then 7_out_< 0 3'''''''3; elsif 7_in_< 0 31''13 then 7_out_< 0 3''1''''3; -

else 7_out_< 0 311111113;

end if;end process;end beha%ioral;

B. BCD B

library ieee;use !###.7_89!_1164.


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entity A7_ isport (

7_in_ : in std_logic_%ector() downto ';7_out_ : out std_logic_%ector(6 downto '

;end A7_;

architecture beha%ioral of A7_ isbegin

Drocess (7_in_begin

if 7_in_ 0 3''''3 then 7_out_ 0 3''''''13; 'elsif 7_in_ 0 3'''13 then 7_out_ 0 3'11'1113; 1elsif 7_in_ 0 3''1'3 then 7_out_ 0 31''''1'3; &elsif 7_in_ 0 3''113 then 7_out_ 0 3''1''1'3; )elsif 7_in_ 0 3'1''3 then 7_out_ 0 3'11'1''3; 4elsif 7_in_ 0 3'1'13 then 7_out_ 0 3''11'''3; *elsif 7_in_ 0 3'11'3 then 7_out_ 0 3'''1'''3; 6elsif 7_in_ 0 3'1113 then 7_out_ 0 3'11''113; +

elsif 7_in_ 0 31'''3 then 7_out_ 0 3'''''''3; elsif 7_in_ 0 31''13 then 7_out_ 0 3''1''''3; -

else 7_out_ 0 311111113;

end if;end process;end beha%ioral;

all program

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