am011 (v1.1) november 30, 2020 versal acap - xilinx...r e v i s i o n h i s t o r y the following...

Versal ACAP

Technical Reference Manual

AM011 (v1.1) November 30, 2020

https://www.xilinx.com

Revision HistoryThe following table shows the revision history for this document.

Section Revision Summary11/30/2020 Version 1.1

General updates. Revised nomenclature for CPM to adhere to the PCIe®trademark. Changed Encrypt Only (EO) terminology toSymmetric Hardware Root of Trust (S-HWRoT), andHardware Root of Trust (HWRoT) to Asymmetric HardwareRoot of Trust (A-HWRoT). Changed the name of the securedebug feature to authenticated JTAG.

Introduction

General updates. Renamed chapters and reorganized content throughout.

Figure 1: System Processors Block Diagram Added system block diagram.

Links to Platform Management Resources Changed name from PMC Hardware Perspective andremoved I/O peripherals as boot devices.

Device Implementation Changed name from Versal™ Device Variations, addedProcessing System Support Hardware, Integrated HardwareOptions, and Comparison to Previous Generation Xilinx®Devices.

Hardware Architecture

Device Components Reorganized sections.

Standard Hardware Added section.

Example Physical Layout Updated to clarify the layout as an example.

Full-power Domain Removed APU Interconnect section.

Block Diagram Corrected and clarified MIO pin connections.

Comparison to Previous Generation Xilinx Devices Changed secure debug to authenticated JTAG.

Device I/O Connectivity Added debug paths to this chapter.

Figure 11: I/O Connectivity Diagram Revised XPIPE area and enhanced the PSIO and EMIOrepresentation.

PSIO Banks Added section.

XPIPE GTY Transceiver Channels Added section.

Figure 4: PS Interconnect Diagram Revised the CPM block and removed performance monitor.

Figure 4: PS Interconnect Diagram, Figure 6: LPD BlockDiagram, and Figure 9: PMC Interconnect

Removed performance monitor.

XPIO Banks Revised for clarity and renamed from DDR XPIO TransceiverBanks.

Platform Boot, Control, and Status

Secure Boot Flow Changed secure debug to authenticated JTAG.

Boot Image Revised chapter name, added information for theprogrammable device image, and clarified the figure.

PDI Size Estimation Added new section.

Revision History

AM011 (v1.1) November 30, 2020 www.xilinx.comVersal ACAP TRM 2Send Feedback

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Section Revision SummaryBoot Modes Updated QSPI entry in primary boot modes table, added the

visual boot pin usage guide table, and added eMMC1 (raw)information to the boot mode search limit table.

Quad SPI Signals Added details for BootROM MIO setup.

SD Signals Revised the descriptions of WP, DETECT, and bus power.Added details for BootROM MIO setup.

SD2.0 Interface Specified WP, DETECT, and BUSPWR signals are optional.Added external voltage level translator information andadded note to figure.

SD3.0 Interface Specified WP, DETECT, and BUSPWR signals are optional.Added external voltage level translator information andadded note to figure.

eMMC1 Boot Mode Added information on the raw partition support for boot.

Table 28: BootROM Error Codes Revised description for 0x301, 0x302, 0x31D, 0x320,0x517, 0x518, 0x51A, and 0x51B error codes.

I/O Configuration Detection Added new section.

SelectMAP Boot Mode Added SelectMAP wait time and recommendation for JTAGduring early phases and debug.

eMMC1 Signals Added details for BootROM MIO setup.

SelectMAP Signals Added details for BootROM MIO setup.

Octal SPI Signals Added details for BootROM MIO setup.

BootROM Error Codes Revised error codes and added new error codes.

Address Maps and Programming Interfaces

4 GB Address Space Added new section and updated address maps.

Detailed 4 GB Address Maps Renamed from Detailed Address Map and reorganizedsection.

IOP SLCR Registers for PMC and LPD Added new chapter.

NPI Programming Interface Clarified introductory paragraph.

Signals, Interfaces, and Pins

Power Pins and PMC Dedicated Pins Combined Power Pins chapter with PMC Dedicated Pinschapter.

PMC Dedicated Pins Removed DXP/DXN pins from the table.

Power Pins Reorganized power pins table.

Engines

Operating Modes Renamed from Operating States and clarified information.

Configuration Registers Renamed from Hardware Configuration and reviseddescriptions.

Power States Renamed from Power Modes.

CPU Local Memory Maps Clarified lock-step cache entries.

Memory Map Diagram Clarified 0xF900_0000 address information.

FPD Block Diagram Renamed from Block Diagram.

APU MPCore Functional Units Renamed from Functional Units.

Embedded Processor, Configuration, and Security Units

Section VII: Embedded Processor, Configuration, andSecurity Units

Renamed from Platform Processor, Configuration, andSecurity Units, as well as reorganized chapter content.

Revision History



Section Revision SummaryPMC Global Register Set Completed register descriptions.

Clock Monitor Added this chapter.

Interconnect

Overview Extensive additions and revisions throughout this chapter.

List of Interconnect Diagrams Added new section.

LPD Interconnect Port Diagram Added new section.

Interconnect Hardware Added new chapter.

Table 79: Interconnect Switch Functionality Removed performance module probe.

Figure 58: PS Memory Address Translation Significant updates, including added new pathways, as wellas added and removed masters.

Transaction Routing Added Transaction Routing Options Through CCI table.

Striping Added new section.

Instances Removed base address information.

Address Map Added new section.

Interrupts and Errors

PMC Error Status 1 and PMC Error Status 2 Added SSI technology to table.

Error Containment Added new chapter.

Timers, Counters, and RTC

Table 119: TTC Register Overview Added address offset and access type, as well as clarifiedcontent.

I/O Peripheral Controllers

Control and Status Revised register names.

Message Space Data Revised register names.

Modes and States Revised modes and options.

Programming Model Added two functional anomalies.

Comparison to Previous Generation Xilinx Devices Clarified device comparison.

Interrupts Added new chapter.

Flash Memory Controller

Start-up Sequences Clarified idle status bit section.

Voltage Level Shifter Interface Added note and added bus power to figure.

Figure 103: External Voltage Level Shifter Wiring Revised figure to add bus power.

SD Command Response Registers Added new section.

Clocks, Resets, and Power

Resets Extensive additions and updates throughout this chapter.

Table 241: PMC System Reference Clock Registers Added footnote.

Test and Debug

Figure 112: Debug Interface Block Changed HSDP Link Layer Options to DPC Link LayerOptions. Added HSDP to CPM PCIe® and Aurora (Hard IP).

JTAG and Boundary-Scan Added information on JTAG interface protections.

JTAG Register Reference Added to the JTAG_CONFIG register description.

TAP Instructions Changed SEC_DBG to AUTH_JTAG and updated description.Updated STATUS to JTAG_STATUS.

Revision History



Section Revision SummaryCoreSight Debug Added more information for bandwidth calculations and

reorganized content.

Arm DAP Controller Added link to Arm® Debug Interface ArchitectureSpecification.

High-Speed Debug Port Removed reserved from the PCIe connector. Added HSDP toAurora and PCIe connections and added debug host to PCIeconnection. Added DPC link layer options table.

Debug Packet Controller Clarified HSDP defined protocol and added non-HSDP linklayer information.

CoreSight Register Reference Added new section.

07/16/2020 Version 1.0

Initial release. N/A

Revision History



Table of ContentsRevision History...............................................................................................................2

Section I: Introduction...............................................................................................20

Chapter 1: Introduction to Versal ACAP......................................................21

Chapter 2: Navigating Content by Design Process............................... 23

Chapter 3: Versal Device...................................................................................... 25System Block Diagram.........................................................................................................27System Software...................................................................................................................27RPU and APU Multiprocessor Cores.................................................................................. 28System Performance............................................................................................................29Platform Management Controller......................................................................................31Software Programming Interfaces.................................................................................... 33

Chapter 4: Technical Reference Manual Outline....................................34Additional Versal™ ACAP Documents................................................................................ 35

Section II: Hardware Architecture...................................................................... 36

Chapter 5: Device Components........................................................................37Device-Level Interconnect Diagram...................................................................................38Standard Hardware..............................................................................................................40Integrated Hardware Options............................................................................................ 42Integrated Peripheral Options........................................................................................... 44Example Physical Layout..................................................................................................... 46

Chapter 6: Processing System Architecture............................................. 48PS Interconnect Diagram.................................................................................................... 48Full-power Domain...............................................................................................................50Low-power Domain..............................................................................................................53



Chapter 7: Platform Management Controller......................................... 57Block Diagram...................................................................................................................... 60Functionality......................................................................................................................... 61I/O Signals.............................................................................................................................63PMC Interconnect.................................................................................................................64Comparison to Previous Generation Xilinx Devices.........................................................66

Chapter 8: PS and PMC I/O Peripherals.......................................................68

Chapter 9: Programmable Logic......................................................................70Block Diagram...................................................................................................................... 71Adaptable Engines in PL......................................................................................................73

Chapter 10: Device I/O Connectivity............................................................. 75Device-Level Diagram.......................................................................................................... 76PSIO Banks............................................................................................................................77XPIPE GTY Transceiver Channels........................................................................................77PL HDIO Banks......................................................................................................................78XPIO Banks............................................................................................................................79

Chapter 11: Device Implementation............................................................. 81IP Versions............................................................................................................................ 82Comparison to Previous Generation Xilinx Devices.........................................................83

Section III: Platform Boot, Control, and Status...........................................85

Chapter 12: Overview............................................................................................ 86

Chapter 13: Non-Secure Boot Flow................................................................ 88

Chapter 14: Secure Boot Flow........................................................................... 92Asymmetric Hardware Root of Trust Secure Boot........................................................... 94Symmetric Hardware Root of Trust Secure Boot............................................................. 97

Chapter 15: Boot Image......................................................................................100PDI Size Estimation............................................................................................................ 101Boot Header........................................................................................................................104

Chapter 16: Boot Modes..................................................................................... 106



JTAG Boot Mode..................................................................................................................109Quad SPI Boot Mode......................................................................................................... 110SD Boot Modes................................................................................................................... 115eMMC1 Boot Mode............................................................................................................ 119Octal SPI Boot Mode.......................................................................................................... 121SelectMAP Boot Mode....................................................................................................... 124

Chapter 17: BootROM Error Codes............................................................... 131

Chapter 18: Platform Management.............................................................141Functional Safety Management....................................................................................... 141Dynamic Function eXchange ........................................................................................... 144Power Management.......................................................................................................... 144Security Management....................................................................................................... 147Soft Error Mitigation.......................................................................................................... 154

Section IV: Address Maps and Programming Interfaces......................155

Chapter 19: Address Maps.................................................................................156Global Address Map...........................................................................................................1564 GB Address Space........................................................................................................... 157

Chapter 20: Programming Interfaces.........................................................179APB, AXI Programming Interface.....................................................................................179NPI Programming Interface............................................................................................. 180Configuration Frame Programming Interface............................................................... 181

Section V: Signals, Interfaces, Pins, and Controls.................................... 182

Chapter 21: Power Pins and PMC Dedicated Pins................................ 183PMC Dedicated Pins...........................................................................................................183Power Pins...........................................................................................................................184

Chapter 22: Multiplexed I/O Pins.................................................................. 186I/O Pinout Considerations................................................................................................ 186MIO-at-a-Glance................................................................................................................. 187Special MIO Clock Routing................................................................................................ 191MIO-EMIO Interface Options............................................................................................192MIO-EMIO Wiring...............................................................................................................193



MIO Pin Configuration.......................................................................................................194PCIe Reset on MIO............................................................................................................. 197

Chapter 23: IOP SLCR Registers for PMC and LPD................................198PMC_IOP_SLCR Registers...................................................................................................198LPD_IOP_SLCR Registers....................................................................................................200

Chapter 24: Boundary Interface Signals................................................... 202PS-PL Boundary.................................................................................................................. 202PMC-PL Boundary.............................................................................................................. 203

Section VI: Engines.....................................................................................................204

Chapter 25: Overview.......................................................................................... 205Scalar Engines.....................................................................................................................205Intelligent Engines............................................................................................................. 206Adaptable Engines............................................................................................................. 207DMA Units........................................................................................................................... 207

Chapter 26: Real-time Processing Unit...................................................... 208Features...............................................................................................................................208System Perspective............................................................................................................ 209Implementation..................................................................................................................210Operating Modes............................................................................................................... 210Power States....................................................................................................................... 212Address Maps..................................................................................................................... 213Processor Memory Datapaths..........................................................................................216Tightly Coupled Memories................................................................................................217Memory Error Detection and Correction........................................................................ 218RPU Memory Protection Unit............................................................................................218Interrupts............................................................................................................................ 219GIC Interrupt Controller.................................................................................................... 220System Errors Generated by RPU.....................................................................................223Test and Debug.................................................................................................................. 223Register Reference.............................................................................................................224

Chapter 27: Application Processing Unit.................................................. 226Features...............................................................................................................................227System Perspective............................................................................................................ 228



Memory Space....................................................................................................................230Execution Pipelines............................................................................................................ 231APU Address Model........................................................................................................... 232Virtualization.......................................................................................................................233Server Architecture............................................................................................................ 233Processor Counters............................................................................................................234Interrupts............................................................................................................................ 237GIC Interrupt Controller.................................................................................................... 239Test and Debug.................................................................................................................. 239Register Reference.............................................................................................................239

Chapter 28: LPD DMA........................................................................................... 241Functional Description.......................................................................................................241Features...............................................................................................................................242System Perspective............................................................................................................ 243Channel Block Diagram.....................................................................................................246Modes and States...............................................................................................................246Simple Mode Programming..............................................................................................247Descriptor Mode Programming....................................................................................... 249Done Interrupt Accounting...............................................................................................259Over Fetch........................................................................................................................... 259Transaction Control........................................................................................................... 262Flow-Control Interface.......................................................................................................263Error Conditions................................................................................................................. 267Security................................................................................................................................269Channel Paused..................................................................................................................269Programming Model for Changing DMA Channel States............................................. 270Register Reference.............................................................................................................271I/O Flow Control Signals....................................................................................................272

Section VII: Embedded Processor, Configuration, and SecurityUnits...............................................................................................................................273

Chapter 29: Overview.......................................................................................... 274

Chapter 30: Platform Processing Unit........................................................276Features...............................................................................................................................276System Perspective............................................................................................................ 276Programming Model......................................................................................................... 278



PMC Register Reference....................................................................................................278

Chapter 31: Processing System Manager................................................. 286Features...............................................................................................................................286System Perspective............................................................................................................ 286

Chapter 32: PL Configuration.......................................................................... 288Configuration Frame Unit................................................................................................. 288Configuration Frame Interface.........................................................................................289

Chapter 33: Slave Boot Interface.................................................................. 290

Chapter 34: Streaming Interconnect Module........................................ 291Secure Stream Switch........................................................................................................ 291PMC DMAs...........................................................................................................................291AES-GCM..............................................................................................................................292SHA3-384............................................................................................................................. 293

Chapter 35: RSA/ECDSA.......................................................................................294

Chapter 36: True Random Number Generator...................................... 295

Chapter 37: Physically Unclonable Function.......................................... 296

Chapter 38: Battery-Backed RAM..................................................................297

Chapter 39: eFUSE Controller.......................................................................... 299

Section VIII: Interconnect......................................................................................300

Chapter 40: Overview.......................................................................................... 301Features...............................................................................................................................302System Perspective............................................................................................................ 305

Chapter 41: Interconnect Hardware........................................................... 308Channel Diagram............................................................................................................... 309Ingress Ports.......................................................................................................................310Egress Ports........................................................................................................................ 311FPD Switches and Ports.....................................................................................................313LPD Switches and Ports.....................................................................................................313



PMC Switches and Ports....................................................................................................316

Chapter 42: PS-PL Interfaces........................................................................... 318PL to PS Interfaces............................................................................................................. 318PS to PL Interfaces............................................................................................................. 321Address Map....................................................................................................................... 321

Chapter 43: Memory Virtualization............................................................. 323System Perspective............................................................................................................ 324APU Virtualization.............................................................................................................. 325Interrupt Virtualization......................................................................................................328

Chapter 44: System Memory Management Unit..................................329TBU Instances.....................................................................................................................329Address Translation Examples......................................................................................... 330Memory Protection Functionality.....................................................................................331

Chapter 45: Cache Coherent Interconnect.............................................. 332Port Interfaces....................................................................................................................332Master Port Interfaces.......................................................................................................333Transaction Routing...........................................................................................................333Striping................................................................................................................................ 334

Chapter 46: Memory Protection.................................................................... 335Functional Units..................................................................................................................335Use Case Examples............................................................................................................ 336TrustZone Security............................................................................................................. 336

Chapter 47: Xilinx Memory Protection Unit............................................337Features...............................................................................................................................338System Perspective............................................................................................................ 339Memory Regions................................................................................................................ 339Access Checking Operations.............................................................................................340Error Handling.................................................................................................................... 341Transaction Signals............................................................................................................ 342Configuration......................................................................................................................343

Chapter 48: Xilinx Peripheral Protection Unit....................................... 344Features...............................................................................................................................344



System Perspective............................................................................................................ 345Access Checking Operation.............................................................................................. 346Aperture Permissions........................................................................................................ 346Permission Checking......................................................................................................... 349Error Handling.................................................................................................................... 350Configuration......................................................................................................................351Master ID Validation.......................................................................................................... 351

Chapter 49: PS Traffic Control......................................................................... 352

Chapter 50: AXI Transaction Attributes.................................................... 353Attribute Types................................................................................................................... 353TrustZone Security............................................................................................................. 355System Management ID....................................................................................................359

Section IX: Interrupts and Errors.......................................................................363

Chapter 51: System Interrupts....................................................................... 364System Interrupt Controllers............................................................................................364IRQ System Interrupts.......................................................................................................365Register Reference.............................................................................................................368

Chapter 52: Inter-Processor Interrupts.....................................................370Features...............................................................................................................................370System Perspective............................................................................................................ 371Agent Communications.....................................................................................................372Interrupt Architecture....................................................................................................... 373Message Passing Architecture......................................................................................... 375Register Reference and Address Map............................................................................. 376Programming Examples....................................................................................................380

Chapter 53: System Errors.................................................................................382System Error Accumulators.............................................................................................. 383Functional Safety Errors.................................................................................................... 385Security Errors.................................................................................................................... 385Programming Model......................................................................................................... 385Error Accumulator Registers.............................................................................................386

Chapter 54: Error Containment......................................................................393



Section X: Timers, Counters, and RTC............................................................. 394

Chapter 55: Summary of Counters and Timers..................................... 395

Chapter 56: Real-Time Clock............................................................................ 396Features...............................................................................................................................397Counter Module................................................................................................................. 398Calibration...........................................................................................................................398RTC Accuracy.......................................................................................................................399Interfaces and Signals....................................................................................................... 400Registers..............................................................................................................................400

Chapter 57: System Counter............................................................................ 402

Chapter 58: Triple-Timer Counter................................................................. 404Features...............................................................................................................................404Block Diagram ................................................................................................................... 405Overflow Detection Functional Model.............................................................................407Interval Timing Functional Model.................................................................................... 408Event Timer Functional Model..........................................................................................408Register Reference.............................................................................................................409TTC I/O Signals................................................................................................................... 410

Chapter 59: System Watchdog Timer ........................................................ 411Features...............................................................................................................................412System Perspective............................................................................................................ 413Modes and States ..............................................................................................................415Programming Sequences..................................................................................................417Register Reference.............................................................................................................420SWDT I/O Signals .............................................................................................................. 421

Section XI: Memory................................................................................................... 423

Chapter 60: Overview.......................................................................................... 424

Chapter 61: On-Chip Memory..........................................................................426Features...............................................................................................................................426System Perspective............................................................................................................ 427



States................................................................................................................................... 427Address Map....................................................................................................................... 428Memory Address Protection............................................................................................. 428ECC Protection.................................................................................................................... 429ECC Operations...................................................................................................................429

Chapter 62: XRAM Memory...............................................................................431Features...............................................................................................................................431System Perspective............................................................................................................ 432Address Map....................................................................................................................... 433Memory Address Protection............................................................................................. 433ECC Protection.................................................................................................................... 434

Chapter 63: External Memory......................................................................... 435

Chapter 64: Embedded Memory.................................................................... 436

Chapter 65: Small Storage Elements........................................................... 437

Section XII: I/O Peripheral Controllers.......................................................... 438

Chapter 66: CAN FD Controller....................................................................... 439Features...............................................................................................................................439System Perspective............................................................................................................ 441Modes and States...............................................................................................................444Configuration Sequence....................................................................................................451Message Transmission...................................................................................................... 452Message Reception............................................................................................................455Register Reference.............................................................................................................458I/O Signal Reference..........................................................................................................461

Chapter 67: Gigabit Ethernet MAC............................................................... 462Features...............................................................................................................................463System Perspective............................................................................................................ 465Modes and States...............................................................................................................472Memory Packet Descriptors..............................................................................................472DMA AXI Master................................................................................................................. 473Transmit Dataflow..............................................................................................................475MAC Transmitter................................................................................................................ 479



Receive Dataflow................................................................................................................ 482MAC Receiver...................................................................................................................... 487Precision Timestamp Unit................................................................................................. 494MAC Pause Frames............................................................................................................ 496Checksum Hardware......................................................................................................... 499Register Reference.............................................................................................................501I/O Signal Reference..........................................................................................................507

Chapter 68: GPIO Controller............................................................................ 510Features...............................................................................................................................510System Perspective............................................................................................................ 512Channel Block Diagram.....................................................................................................515Input Programming Model............................................................................................... 516Interrupt Programming Model........................................................................................ 517Output Programming Model............................................................................................ 518Registers..............................................................................................................................518GPIO I/O Signals.................................................................................................................521

Chapter 69: I2C Controller.................................................................................523Features...............................................................................................................................524System Perspective............................................................................................................ 525Programming Model......................................................................................................... 526Programming Sequences..................................................................................................532Software Routines.............................................................................................................. 534Register Reference.............................................................................................................545I2C I/O Interface.................................................................................................................547

Chapter 70: SPI Controller.................................................................................549Features...............................................................................................................................549System Perspective............................................................................................................ 550Modes and States...............................................................................................................552Clocking............................................................................................................................... 554Functional Diagram........................................................................................................... 555Data Transfer...................................................................................................................... 556Register Reference.............................................................................................................558I/O Interface....................................................................................................................... 559

Chapter 71: UART SBSA Controller................................................................560Features...............................................................................................................................560



System Perspective............................................................................................................ 561Modes and States...............................................................................................................563UART Functionality............................................................................................................. 564IrDA Functionality...............................................................................................................570Interrupts............................................................................................................................ 572Registers..............................................................................................................................574UART I/O Signals................................................................................................................ 576

Chapter 72: USB 2.0 Controller........................................................................577Features ..............................................................................................................................578System Perspective............................................................................................................ 578Host Mode Data Structures.............................................................................................. 583Register Reference.............................................................................................................585USB I/O Signals...................................................................................................................592

Section XIII: Flash Memory Controllers......................................................... 593

Chapter 73: Octal SPI Controller....................................................................594Features...............................................................................................................................595System Perspective............................................................................................................ 595Access Modes..................................................................................................................... 599DMA Programming Model................................................................................................ 601Interrupts............................................................................................................................ 605Register Reference.............................................................................................................606OSPI I/O Interface..............................................................................................................609

Chapter 74: Quad SPI Controller....................................................................611Features...............................................................................................................................612System Perspective............................................................................................................ 612Modes and States...............................................................................................................617I/O Functionality.................................................................................................................619Command Words............................................................................................................... 622Programming..................................................................................................................... 623PIO Mode Programming Model....................................................................................... 625DMA Programming Model................................................................................................ 626Polling Programming Model............................................................................................ 626Register Reference.............................................................................................................627QSPI I/O Interface..............................................................................................................628



Chapter 75: SD/eMMC Controller.................................................................. 632Features...............................................................................................................................633System Perspective............................................................................................................ 634Modes and States...............................................................................................................638Main Functionality..............................................................................................................639I/O Functionality.................................................................................................................641Clock Functionality............................................................................................................. 643I/O Clocks............................................................................................................................ 648SD Commands.................................................................................................................... 651PIO Data Port Programming Model................................................................................ 654SDMA Programming Model.............................................................................................. 654ADMA2 Programming Model............................................................................................655Software Routines.............................................................................................................. 655Register Reference.............................................................................................................655I/O Signals...........................................................................................................................659

Section XIV: Clocks, Resets, and Power..........................................................662

Chapter 76: Clocks................................................................................................. 663Clock Distribution Diagram...............................................................................................664PMC Source Clocks.............................................................................................................666PLL Clock Generators.........................................................................................................667Reference Clock Frequency Dividers............................................................................... 668Registers..............................................................................................................................669

Chapter 77: Clock Monitor................................................................................ 674Base Time Period............................................................................................................... 674Calculate Threshold Counts.............................................................................................. 675Monitored Clocks............................................................................................................... 676Interrupts............................................................................................................................ 676Register Reference.............................................................................................................677

Chapter 78: Resets................................................................................................. 678Features...............................................................................................................................679System Perspective............................................................................................................ 680Device-level Reset Table.................................................................................................... 682PMC Start-up From POR Reset......................................................................................... 683System Monitoring.............................................................................................................685



Reset Software Management........................................................................................... 686Reset Reason Register....................................................................................................... 688Persistent Register Groups............................................................................................... 689Resets Control and Status Registers................................................................................693Reset I/O Signals................................................................................................................ 697

Chapter 79: Power..................................................................................................698Power Diagram...................................................................................................................700Power Domains.................................................................................................................. 702Power Islands..................................................................................................................... 702

Section XV: Test and Debug.................................................................................. 703

Chapter 80: Integrated Debug........................................................................704JTAG and Boundary-Scan...................................................................................................705Arm DAP Controller............................................................................................................715High-Speed Debug Port.................................................................................................... 716

Chapter 81: Device Identification................................................................. 718

Chapter 82: CoreSight Debug.......................................................................... 720Trace Port Interface Unit...................................................................................................720CoreSight Register Reference...........................................................................................721

Appendix A: Additional Resources and Legal Notices........................... 722Xilinx Resources.......................................................................................................................722Documentation Navigator and Design Hubs...................................................................... 722References................................................................................................................................722Arm References....................................................................................................................... 723Please Read: Important Legal Notices................................................................................. 724



Section I

IntroductionThis section includes these chapters:

• Introduction to Versal ACAP

• Navigating Content by Design Process

• Versal Device

• Technical Reference Manual Outline

Section I: Introduction



Chapter 1

Introduction to Versal ACAPVersal™ adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, AdaptableEngines, and Intelligent Engines with leading-edge memory and interfacing technologies todeliver powerful heterogeneous acceleration for any application. Most importantly, Versal ACAPhardware and software are targeted for programming and optimization by data scientists andsoftware and hardware developers. Versal ACAPs are enabled by a host of tools, software,libraries, IP, middleware, and frameworks to enable all industry-standard design flows.

Built on the TSMC 7 nm FinFET process technology, the Versal portfolio is the first platform tocombine software programmability and domain-specific hardware acceleration with theadaptability necessary to meet today's rapid pace of innovation. The portfolio includes six seriesof devices uniquely architected to deliver scalability and AI inference capabilities for a host ofapplications across different markets—from cloud—to networking—to wireless communications—to edge computing and endpoints.

The Versal architecture combines different engine types with a wealth of connectivity andcommunication capability and a network on chip (NoC) to enable seamless memory-mappedaccess to the full height and width of the device. Intelligent Engines are SIMD VLIW AI Enginesfor adaptive inference and advanced signal processing compute, and DSP Engines for fixed point,floating point, and complex MAC operations. Adaptable Engines are a combination ofprogrammable logic blocks and memory, architected for high-compute density. Scalar Engines,including Arm® Cortex™-A72 and Cortex-R5F processors, allow for intensive compute tasks.

The Versal AI Core series delivers breakthrough AI inference acceleration with AI Engines thatdeliver over 100x greater compute performance than current server-class of CPUs. This series isdesigned for a breadth of applications, including cloud for dynamic workloads and network formassive bandwidth, all while delivering advanced safety and security features. AI and datascientists, as well as software and hardware developers, can all take advantage of the high-compute density to accelerate the performance of any application.

The Versal Prime series is the foundation and the mid-range of the Versal platform, serving thebroadest range of uses across multiple markets. These applications include 100G to 200Gnetworking equipment, network and storage acceleration in the Data Center, communicationstest equipment, broadcast, and aerospace & defense. The series integrates mainstream 58Gtransceivers and optimized I/O and DDR connectivity, achieving low-latency acceleration andperformance across diverse workloads.

Section I: IntroductionChapter 1: Introduction to Versal ACAP



The Versal Premium series provides breakthrough heterogeneous integration, very high-performance compute, connectivity, and security in an adaptable platform with a minimizedpower and area footprint. The series is designed to exceed the demands of high-bandwidth,compute-intensive applications in wired communications, data center, test & measurement, andother applications. Versal Premium series ACAPs include 112G PAM4 transceivers and integratedblocks for 600G Ethernet, 600G Interlaken, PCI Express® Gen5, and high-speed cryptography.

The Versal architecture documentation suite is available at: https://www.xilinx.com/versal.

Section I: IntroductionChapter 1: Introduction to Versal ACAP


https://www.xilinx.com/versalhttps://www.xilinx.comhttps://www.xilinx.com/about/feedback/document-feedback.html?docType=Architecture_Manual&docId=AM011&Title=Versal%20ACAP&releaseVersion=1.1&docPage=22

Chapter 2

Navigating Content by DesignProcess

Xilinx® documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. This document covers the following designprocesses:

• System and Solution Planning: Identifying the components, performance, I/O, and datatransfer requirements at a system level. Includes application mapping for the solution to PS,PL, and AI Engine.

The technical reference manual (TRM) describes the overall hardware architecture of theVersal™ ACAP and provides details on the blocks in the platform management controller(PMC) and in the processing system (PS).

• High-level chip description: Section II: Hardware Architecture

• PS architecture: Processing System Architecture

• PMC architecture: Platform Management Controller

• AMBA® Interconnect: Section VIII: Interconnect

• I/O connectivity architecture (buffers and transceivers): Device I/O Connectivity

• Clock, reset, and power architectures and controls: Section XIV: Clocks, Resets, and Power

There are several device families with different options. The device-specific options are listedin the Versal Architecture and Product Data Sheet: Overview (DS950).

• Embedded Software Development: Creating the software platform from the hardwareplatform and developing the application code using the embedded CPU. Also covers XRT andGraph APIs.

Embedded software can run on one or both of the Arm® Cortex™ scalar engines in the PS:

• Real-time Processing Unit (dual-core Cortex-R5F)

• Application Processing Unit (dual-core Cortex-A72)

The PMC and PS functional units require device drivers as part of the embedded softwarestack. Several TRM reference sections primarily focus on content for device driverdevelopment. Major peripherals are listed in the following sections:

Section I: IntroductionChapter 2: Navigating Content by Design Process


https://www.xilinx.com/cgi-bin/docs/ndoc?t=data_sheets;d=ds950-versal-overview.pdfhttps://www.xilinx.comhttps://www.xilinx.com/about/feedback/document-feedback.html?docType=Architecture_Manual&docId=AM011&Title=Versal%20ACAP&releaseVersion=1.1&docPage=23

• Section VII: Embedded Processor, Configuration, and Security Units

• Section XII: I/O Peripheral Controllers

• Section XIII: Flash Memory Controllers

Additional TRM sections and chapters describe the interconnect, timers, counters, clocks,resets, and power.

The system software boot up and operating system environments are described in the VersalACAP System Software Developers Guide (UG1304).

• Board System Design: Designing a PCB through schematics and board layout. Also involvespower, thermal, and signal integrity considerations.

The TRM includes some important information to help with board design planning anddevelopment:

• Boot device interfaces: Boot Modes

• Pin planning for I/O peripherals: Multiplexed I/O Pins

• Power controls: Power Diagram

• JTAG interface: JTAG and Boundary-Scan

For package and pin information, see the Versal ACAP Packaging and Pinouts ArchitectureManual (AM013).

The electrical specifications are provide in the Versal Prime Series Data Sheet: DC and ACSwitching Characteristics (DS956) and the Versal AI Core Series Data Sheet: DC and AC SwitchingCharacteristics (DS957).

Section I: IntroductionChapter 2: Navigating Content by Design Process


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Chapter 3

Versal DeviceThe Versal ACAP includes several processors, each with different computation capabilities tomeet application needs. All devices include the processing system (PS) and the platformmanagement controller (PMC). All devices also include the network on chip (NoC) interconnect toenable all processors to reach the DDR memory controllers, and other resources within thedevice. All Versal devices include programmable logic (PL). The size of the PL and thecomposition of a programmable region varies. Each device has one or more DDR memorycontrollers. There are also several types of I/O banks to connect to external devices. The size ofthe NoC and the PL, and the number of memory controllers varies by device.

The Versal ACAP Technical Reference Manual (AM011) describes the overall hardware architectureof the Versal ACAP and the technical details of both the processing system (PS) and the platformmanagement controller (PMC). The control and status registers for the PS and PMC are describedin the Versal ACAP Register Reference (AM012). There are approximately 135 different registermodule types included in the register reference. Most functional units include one registermodule. Some functional units have multiple register modules (e.g., PPU, interconnect). Someregister modules are associated with multiple functional units which includes the system-levelcontrol registers (SLCR). All PS and PMC register modules are accessed by software using 32-bitread and write transactions to APB programming interfaces.

Processing System

The Processing System includes two Arm-based multiprocessors:

• Arm Cortex-A72 dual-core processor with the system memory management unit (SMMU) andthe cache coherent interface (CCI) unit.

• Arm Cortex-R5F dual-core processor for applications requiring safety and deterministicexecution times.

The PS also includes:

• DMA unit, clocks, timers, access protection units, and local memories.

• Error detection, system and clock monitoring, and security features.

Section I: IntroductionChapter 3: Versal Device


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Platform Management Controller

The Versal ACAP also includes the PMC. The PMC is responsible for boot, configuration, partial-reconfiguration, and life cycle management tasks, such as security. The PMC includes the deeplyembedded ROM code unit (RCU) for device boot and platform processing unit (PPU) thatexecutes the platform loader and management (PLM) software code. The PLM also manages theprocessing system manager (PSM) firmware downloads.

NoC and Main Memory

The NoC interconnect is pervasive across the device and includes one or more DDR memorycontrollers.

PL Hardware Acceleration-and Microprocessors

The PL includes adaptable components to create all types of functionality. The functions includecustom data manipulation and transport protocol, non-vector-based computational units, andinterfacing to the PS, integrated hardware, and integrated peripherls. The Programmable Logicchapter introduces the PL and has links to additional documentation.

AI Engine

The AI Engine is available in select devices in the Versal™ AI Core series. The AI Engine istypically used for compute-intensive functions in vector implementations. See the IntegratedHardware Options AI Engine section for more information about the AI Engine and links to itsdocumentation.

Coherent Module with PCIe

The coherent module with PCIe® (CPM) is available in select devices in the Versal Prime andPremium series. The CPM in the Prime series includes the CCIX coherency protocol and isreferred to as CPM4. The Premium series includes the CXL coherency protocol and is referred toas CPM5. The CPM with its L2 cache connects functionality in the PL with external devices. Seethe Integrated Hardware Options or the Coherency for PCIe Module section for moreinformation about the CPM and links to its documentation.

Integrated Hardware and Peripheral Options

The are a variety of hardware and peripheral options attached to the PL:

• Integrated Hardware Options include accelerator RAM (XRAM), AI Engine, and CPM.

• Integrated Peripheral Options include high-speed Ethernet MACs, Interlaken, and high-speedcrypto engine.




System Block DiagramThe processors and related system functionality are shown in the following figure.

Figure 1: System Processors Block Diagram

NoC Interconnect

ROM Code Unit (RCU): * Runs BootROM code to load boot image * Provides system monitoring functions * Deeply embedded 32-bit MicroBlaze

Platform Management Controller (PMC)PMC Processing Unit (PPU): * Runs platform loader and manager (PLM) * 32-bit MicroBlaze

PSM Firmware: * Runs firmware downloaded by PLM * 32-bit MicroBlaze

PS Manager (PSM)

Real-time Processing Unit (RPU): * Dual Cortex-R5F processor cores * TCMs and on-chip memories* LPD

Application Processing Unit (APU): * Dual Cortex-A72 processor cores * 1 MB L2-cache, Coherent Interface (CCI) * FPD

Arm MPCore Processors

* DDR4 with ECC* 32 or 64-bit data interface* Interleaveable controllers

DDR Memory Controller(s)

PL

Cache Coherent Interface (FPD_CCI) * ACE, ACE_Lite ports * Four NoC Ingress Ports * Ports to LPD and CPM

System MMU (FPD_SMMU) * Seven translation buffer units (TBU)

FPD Interconnect Building Blocks* Digital Signal Processors (DSP)* Logic Blocks, RAM, and I/O pins

Integrated Peripherals * Ethernet MACs, Interlaken * High-speed Cryptography

Instantiated Blocks * MicroBlaze, interconnect * Pipeline Slices * Functional Units

Programmable Logic* Execution Units* Interconnect Units* Interface Units

AI Engine

* PCIe, DMA* Coherent Cache

CPM

PL

PL

NoC Interconnect

PLSPDFPD/LPDPMCPL or LPD

Power Domains

L2 Cache

I/O

Processing System (PS)

L2 Cache

PL

128-bitTransactionRequest

Bus Type

Multiple Channels

Stream

X24789-112120

System SoftwareKey software components include the following.

• System software running in:

○ Arm Cortex™-A72 and Cortex-R5F processors.

○ Platform processing unit (PPU) MicroBlaze triple-redundant processor.

○ MicroBlaze processors instantiated in the PL.




• PMC and PS peripherals, and optional PL peripherals.

• Bare-metal software stack with standard C libraries: libc and libm, based on the open sourceNewlib library.

• Middleware libraries that provide networking, file system, and encryption support.

• Application examples include test applications.

• Linux-based tools and operating system software including:

○ PetaLinux to quickly build an embedded OS.

○ U-Boot and Yocto-based tools.

• PLM firmware generated by the design tools to program the PL using the configuration frameunit (CFU).

• PLM firmware to configure the device and provide power management.

• Xilinx system debugger (XSDB) in coordination with Arm CoreSight™.

• Debug packet controller and HSDP Aurora I/O

The complete system software environment is described in the Versal ACAP System SoftwareDevelopers Guide (UG1304).

RPU and APU Multiprocessor CoresThe processing system (PS) two multi-processing cores include:

• Application Processing Unit

• Real-time Processing Unit

Application Processing UnitThe application processing unit (APU) is based on an Arm Cortex-A72 dual-core processor withthe system memory management unit (SMMU), cache coherent interface (CCI) unit, interfacechannels to the rest of the system, and system peripherals. The SMMU and CCI work together toprovide a shared memory environment with the PS, PMC, and PL processors that can be tied tothe APU 1 MB L2 cache.

The APU can be used for control-plane applications, operating systems, communicationsinterfaces, and lower level or complex computations. The TRM describes the architecture and theprogramming model for the controllers and other functional units. Linux and bare-metal softwarestacks execute in the APU and RPU in a homogeneous or a heterogeneous environment. TheAPU software environment is described in the Versal ACAP System Software Developers Guide(UG1304).



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The APU is located in the PS full-power domain (FPD).

Real-time Processing UnitThe real-time processing unit (RPU) is based on an Arm Cortex-R5F dual-core processor with L1caches and tightly coupled memories (TCM) dedicated to the RPU cores. The RPU can beconfigured into a dual-processor mode for greatest performance or into a lock-step mode forgreatest safety.

The RPU can provide deterministic execution times for real-time applications. The TRMdescribes the architecture and the programming model for the controllers and other functionalunits. Linux and bare-metal software stacks execute in the APU and RPU in a homogeneous or aheterogeneous environment. The RPU software environment is described in the Versal ACAPSystem Software Developers Guide (UG1304).

The RPU is located in the PS low-power domain (LPD).

System PerformanceThere are inherent performance features in the system and several performance relatedconfiguration options. The TRM describes the inherent performance features and thefunctionality that can be used to obtain an optimal configuration.

• Inherent NoC interconnect design features with configurable, multichannel structures

• Multiple interconnect traffic types to control quality of service (QoS)

○ Isochronous for video and other time-sensitive transactions

○ Low latency for communications and other applications

○ Best effort, bulk traffic for large data sets without critical timing needs

• Intelligent DDR memory controller scheduler

• Hardware acceleration in PL instantiated functions

Performance Tuning

Performance tuning builds on the inherent features. This includes properly routing NoC traffic,optimizing the use of the DDR memory controller, and using the QoS traffic types. Performancetuning is not covered in the TRM.



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Interconnect FeaturesThe interconnect has dedicated 128-bit AXI channel connections between the subsystems.These include low-latency datapaths and high-throughput datapaths with buffering. There arealso noteworthy datapaths.

The interconnect optimizes the performance of the RPU and APU. The interconnect portconnections are shown in PS Interconnect Diagram and listed in this section.

Low-latency Datapaths

• APU to NoC: CCI connections to the NoC

• RPU to NoC: AXI master on OCM switch

• RPU to OCM: AXI master on OCM switch

• RPU to its TCMs: two cycle access with deterministic execution

High-throughput Datapaths

Popular high-throughput datapaths:

• APU to NoC with four CCI master ports

• RPU to NoC with main switch master port

• LPD DMA to FPD main switch

Noteworthy Datapaths

• APU to CCI to FPD main switch to OCM switch to OCM and XRAM (if available)

Transaction Quality of ServiceEach transaction includes a quality of service (QoS) traffic attribute.

• Low-latency

• Isochronous

• Bulk transfer

The QoS attribute is recognized by the AMBA® switches and DDR memory controller. Systemperformance can be obtained by setting the QoS attributes appropriately. Each master cangenerate one or more QoS values. The traffic types are detailed in Quality of Service.

Section