© h. heck 2008section 1.31 module 1:introduction topic 3:interconnect technology ogi ee564 howard...

© H. Heck 2008 Section 1.3 1

Module 1: IntroductionTopic 3: Interconnect Technology

OGI EE564

Howard Heck

© H. Heck 2008 Section 1.3 2

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Where Are We?

1. Introduction1. Overview

2. Trends & Challenges

3. Interconnect Technology

2. Transmission Line Basics

3. Analysis Tools

4. Metrics & Methodology

5. Advanced Transmission Lines

6. Multi-Gb/s Signaling

7. Special Topics

© H. Heck 2008 Section 1.3 3

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Contents

Component PackagingPassive ComponentsConnectorsPrinted Circuit Boards

© H. Heck 2008 Section 1.3 4

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Overview

Components(Chip + Pkg)

PCB(Motherboard)

PCB(add-in card)

Connector

Source: Intel Corp.

© H. Heck 2008 Section 1.3 5

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Overview – SOA Desktop Motherboard

Microprocessor

Memory Slots

Chipset

Graphics Connector

© H. Heck 2008 Section 1.3 6

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Overview – SOA Desktop Motherboard

Microprocessor

Memory ConnectorsChipset

Graphics Connector

X48 chipset motherboard

© H. Heck 2008 Section 1.3 7

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Component Packaging

Packages house the silicon chips. They provide:Mechanical supportHeat removalEnvironmental protectionElectrical signal & power connections (chip to PCB).

SiliconPackage

PCB

Soldered Connections

Heat Spreader

© H. Heck 2008 Section 1.3 8

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Component Packaging

© H. Heck 2008 Section 1.3 9

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Component Packaging

Source: Intel Corp.

© H. Heck 2008 Section 1.3 10

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Example: Flip Chip Pinned Grid Array

Bottom Top

Cross-section

© H. Heck 2008 Section 1.3 11

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Medium Speed Package Electrical Models

Bond Wire Trace Pin / Land

Tie Bar

Lbw Rbw Lpin Rpin

Z0, d

Rtb , Ltb , Ctb

Die

Bo

ard

Source: Packaging Databook, Intel Corp

Today’s speeds demand that we use fully coupled 3D package models.

© H. Heck 2008 Section 1.3 12

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Passive Components

Resistors Uses: termination for interconnect, pull up/down for static

features Variability: 5%, 2%, 1% Chip resistors – 1 resistor per component R-Packs – up to 4 resistors per small outline component Resistor networks – more resistors per component Lead inductance and package crosstalk can be important

effects for high frequency applications. Capacitors Variability: 20%, 10% Chip capacitors – used for high frequency (local) decoupling of

power suppliers Tantalum capacitors – used for bulk decoupling At high frequencies, resistance and inductance of the packages

must be included in the models.

© H. Heck 2008 Section 1.3 13

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Sockets & Connectors

Sockets connect packages to PCBs. Connectors connect PCBs to PCBs. Connection is mechanical between two metal surfaces.

LGA775 Socket

DIMM connector

PCI® Express

© H. Heck 2008 Section 1.3 14

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Socket/Connector Electrical Models

R con L con

C con

These are simple models. Coupled models are frequently used for high performance applications.

Rcon Z0con, dcon

Today’s speeds demand that we use fully coupled 3D connector models.

© H. Heck 2008 Section 1.3 15

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Printed Circuit Boards Function: provide electrical signal connections

between components & deliver power to the components.

Material Set:Function Material

Signal Conductors (traces) Copper (foil & plated)

Power (layers & traces) Copper (foil)

Vias (layer-layer connection) Copper (plated)

Dielectric (insulator) FR-4 (epoxy resin/fiberglass)?

Component connection Eutectic Sn/Pb solder

Solder Mask Typically polyimide based.

Construction: Typically 4 to 6 layers (always an even number). 4 layer board: 2 signal, 2 power ($0.09/in2) 6 layer board: 4 signal, 2 power ($0.18-$0.24/in2) Higher layer counts are available at higher cost.

© H. Heck 2008 Section 1.3 16

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

PCB Construction

Power Plane

Signal Trace

Solder Mask

Via Barrel

Surface Mount Pad

Via Land

Laminate (Dielectric)

Laminate (Resin)

Laminate (Glass)

Signal Trace

Power Plane

Solder Mask

© H. Heck 2008 Section 1.3 17

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

PCB Signal Layer

0.0

50

"

G0.005"

W

0.024"D2

0.005"S1

0.006"S2

0.012"D1

W Signal trace width G Via grid spacing

D1 Via diameter S1 Pad-trace spacing

D2 Via capture pad diameter S2 Trace-trace spacing

© H. Heck 2008 Section 1.3 18

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

PCB Vias

Vias make layer-layer connections by drilling holes and filling them with conductor material (copper).

They are used in chips, package, and boards.

SiliconPackage

PCB

Soldered Connections

Heat Spreader

© H. Heck 2008 Section 1.3 19

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

PCB Design Goals

Function: All signals connected Performance: Maximum operating frequency Cost

Minimized technology requirements• Layer count

• Board size

• Relaxed width & spacing

• Relaxed via size

Design for manufacturability• Component selection

• Component placement

• Trade routing

© H. Heck 2008 Section 1.3 20

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Summary

Package electrical parameters are typically modeled with lumped circuit elements and transmission lines.

We will examine the effects of lumped elements later, and will account for them in our design project. We will also consider when transmission line models are required.

For high volume PCs, system designers use pervasive, low cost PCB solutions: FR-4 material set 4 layer boards 5/5 or 6/6 mil trace/space wiring 4 boards per panel for motherboards

PCBs are used for motherboards, add-in cards, and CPU packages.

PCBs provide interconnect for high speed buses operating as high as 400 MHz/800 MT/s and beyond.

© H. Heck 2008 Section 1.3 21

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

References

Intel Packaging Databook, Intel Corporation, 2002, http://developer.intel.com/design/packtech/packbook.htm.

Component Types Used for SMT, IBM Microelectronics Division, January 1994.

Surface Mount Design and Land Pattern Standard, IPC-SM-782, IPC, Revision A – August 1993.

R.R. Tummala, E.J. Rymaszewski (ed.), Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989.

© H. Heck 2008 Section 1.3 22

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Appendix: More Packages

Celeron® Processor PackageCeleron® Processor Package Celeron® Processor CartridgeCeleron® Processor Cartridge

Pentium® Processor w/ MMX™ PackagePentium® Processor w/ MMX™ Package850 Chipset 850 Chipset PackagePackage

© H. Heck 2008 Section 1.3 23

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Appendix: More Connectors

ISA PCI

Memory DIMM

SLOT1

AGP

© H. Heck 2008 Section 1.3 24

Inte

rco

nn

ect

Tec

hn

olo

gy

EE 5

64

Appendix: CPU Sockets

PGA370