1. digital cmos.2 10/15 figure 10.1 digital ic technologies and logic-circuit families. digital ic...

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Figure 10.1 Digital IC technologies and logic-circuit families.

Digital IC TechnologiesCMOS & Pass Transistor Logic dominate

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Why CMOS

• Advantages• Virtually, no DC power consumed• No DC path between power and ground• Excellent noise margins (VOL=0, VOH=VDD)• Inverter has sharp transfer curve

• Drawbacks• Requires more transistors• Process is more complicated• pMOS size larger to achieve electrical

symmetry

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Figure 4.53 The CMOS inverter.

Digital CMOS Inverter

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Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating point; (c) equivalent circuit.

CMOS InverterOperation; Vin = Hi

Equivalent circuit

Hi Lo

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Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical construction to determine the operating point; (c) equivalent circuit.

CMOS Inverter Operation;Vin = Lo

HiLo

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Figure 4.56 The voltage transfer characteristic of the CMOS inverter.

CMOS Inverter

Transfer characteristic

VIL= highest input voltage still interpreted as an input low (resulting in out = Hi) VIH= lowest input voltage still interpreted as an input Hi (resulting in out = lo)NMH = VOH – VIH

NML = VIL - VOL

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Figure 10.8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.

CMOS Logic gates ?

Pullup(s) &

pulldown(s)

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Figure 10.9 Examples of pull-down networks.

CMOS Logic gate pulldownExamples

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Figure 10.10 Examples of pull-up networks.

CMOS Logic gate pullupExamples

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Figure 10.11 Usual and alternative circuit symbols for MOSFETs.

CMOS Transistor Symbols

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CMOS Logic gate Example 1 ?

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CMOS Logic gate Example 2 ?

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CMOS Logic gate Example 3

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CMOS Logic gate Example 4

Y = ?

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Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion.

CMOS Inverter Representation

Can be represented as

Simple switch

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Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the capacitor discharge.

CMOS InverterDynamicOperation

Input

Output

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Figure 4.58 The current in the CMOS inverter versus the input voltage.

CMOS InverterCurrent VS voltage

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Figure 10.3 Definitions of propagation delays and switching times of the logic inverter.

CMOS Inverter - Propagation delaystPHL = Hi to lotPLH = lo to Hi

Inputtr = rise time tf = fall time

Output

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Figure 10.6 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving an identical inverter formed by Q3 and Q4.

CMOS Inverter

Source of prop. delays

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Figure 10.7 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.

CMOS Inverter

Hi to Lo

prop. Delay analysis

tPHL

tPLH

Lo to Hi

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Music for your ears

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Musique 101

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Figure 10.23 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C).

Pass Transistor Logic PTL

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Figure 10.24 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.

PTLSwitch

NMOS switchCMOS switchAka transmission gate

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Figure 10.25 A basic design requirement of PTL circuits is that every node have, at all times, a low-resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in (b) through switch S2.

PTL – Need path to groundOr VDD For proper logic voltage levels

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Figure 10.26 Operation of the NMOS transistor as a switch in the implementation of PTL circuits. This analysis is for the case with the switch closed (vC is high) and the input going high (vI = VDD).

PTLSwitch closed

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Figure 10.27 Operation of the NMOS switch as the input goes low (vI = 0 V). Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles comparison to the circuit in Fig. 10.26.

PTLSwitch Open

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Figure 10.29 Operation of the transmission gate as a switch in PTL circuits with (a) vI high and (b) vI low.

Transmission gate in action

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Figure 10.30 Realization of a ……??????………….multiplexer using pass-transistor logic.

Transmission gate in actionMultiplexer ?

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Figure 10.31 Realization of the ……. function using pass-transistor logic.

Transmission gate in actionGate ?

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Figure 10.32 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic or CPL. Note that both the output function and its complement are generated.

Transmission gate in actionGate ?

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Figure 10.28 The use of transistor QR, connected in a feedback loop around the CMOS inverter, to restore the VOH level, produced by Q1, to VDD.

Transmission gate (NMOS) drops VtAcross switchPMOS pullup can be used to restore V

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Barrel Shifter, used in ICsShift ……???…. using one transistor per switch

D3

D2

D1

D0

A6

A5

A4

A3 A2 A1 A0

SR0SR1SR2SR3

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Barrel Shifter, used in ICsShift ……???…. using one transistor per switch

D3

D2

D1

D0

A6

A5

A4

A3 A2 A1 A0

SR0SR1SR2SR3

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Barrel Shifter, used in ICsShift ……Left ???…. Exercise

D3

D2

D1

D0

A6

A5

A4

A3 A2 A1 A0

SR0SR1SR2SR3 SL ? SL ?

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Barrel Shifter, used in ICsShift ……Left ???…. Exercise

D3

D2

D1

D0

A5

A4

A3

A2 A1 A0

SR0SR1SR2 SL ? SL ? SL?

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Figure P10.36

How many transistors in each gate implementation ?

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Figure 10.19 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load NMOS inverter.

Other Inverter ImplementationsAll NMOS - Not very popular -- FYI

(a) pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter.

© The depletion-load NMOS inverter.

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Figure 10.38 Capture schematic of the CMOS inverter in Example 10.5.

Pspice Simulation example …. later

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CMOS Inverter Netlistgenerating inverter transfer curve

* here's the inverter netlist declaration* mosfet: mxx drain gate source substrate model length widthm1 OUT IN VDD VDD CMOSP l=.5u w=2um2 OUT IN GND GND CMOSN l=.5u w=2u

* constant voltage source: vxx node1 node2 voltageVDD VDD GND 5

* Define a voltage source connected to Vin and initialize voltage to 0Vin IN Gnd 0

* Sweep Vin from 0 to 5 volts in increments of .1 volt.DC Vin 0 5 .1

* Print the voltage at OUT.print dc v(OUT)

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