chapter 5 fundamental parameters the cmos inverter for ... · the cmos inverter digital ic-design...

1

Digital IC-Design

Chapter 5

The CMOS Inverter

Digital IC-Design

Fundamental parameters

for digital gates

Goal With This Chapter

Analyze Fundamental ParametersA general understanding of the inverter behavior is useful to understand more complex behavior is useful to understand more complex functions

OutlineNoiseReliabilityP fPerformancePower Consumption

Robustness

Noise - “unwanted variations of voltages and currents in logical nodes”g

Classical noise such as thermal and flicker noise are not critical in digital design

Noise sources in digital circuits areCapacitive couplingCapacitive couplingInductive couplingPower and ground noise

2

Capacitive and Inductive Coupling

C

V A voltage or a current change may influence th i l ll l CCoupling V

IMutual

the signal on a parallel wire, especially when:

Long wiresSub micron tech.Many metal layersMutual

Inductance

I

Power and Ground Noise

VDD

A big problem on large

ISwitch

VDD

V

VDDRWirelarge synchronously clocked chips

On chip decoupling capacitors helps

Conclusion: The world is not digital. We need to know the limitations

p p(≈ 1/10 of the switched C)

Definitions

DC OperationNoise MarginsFan OUT - Fan IN

DC Operation

Voltage Transfer Characteristic (VTC)

V5 VOUTVIN

Switching Threshold VM when VIN = VOUT

Balanced if VM = VDD/2V OU

T

VOH

2

3

4

VM

Vout = VIN

Logical “1” at VOHLogical “0” at VOL

1 2 3 4 5

VIN

1

VOL

3

Analog versus Digital Signals

VOH, VOL = nominal t t lt

VOUTVOH

5

output voltage

VIH, VIL = acceptable input voltage

VOH

2

3

4

Slope = -1

1 2 3 4 VIN

1

VOL

VIHVIL

The noise margins

AcceptebleInput Levels

NominalOutput Levels

Analog versus Digital Signals

The noise margins are defined as the difference between VOH/VOLand VIH/VIL

NM = V - VO

VOH

UndefinedRegion

VIH

NMH

NML = VIL VOLNMH = VOH - VIH

VOL

VILNML

Fan-In and Fan-Out

Fan-in = M Fan-out = N

Fan-in = The Fan-out = The number of inputs to the gate

number of gates that loads the gate

The Ideal Gate

R =∞

VOUT

Rin=∞Rout=0Noise Margin=VDD/2Gain = ∞

VIN

4

5NML = VIL - VOL = 0.75 - 0.50 = 0.25V

A Real Gate

V OU

T

2

3

4VOH

VM

VIL

NMH = VOH - VIH = 3.50 - 2.25 = 1.25V

VM = 1.75VVDD

1 2 3 4 5

VOL

VIN

1 VIH

GND

Dynamic Definitions

Propagation delayPropagation delayRise and fall timePower consumption

Delay Definitions

VIN

2tt

t pLHpHLp

+=

VOUT

t

50%

tpLHtpHL

90%

t

50%

tf tr

10%

Ring Oscillator – minimum tp

Odd # of V5V4V3V2V1

Odd # of inverters

“De-facto Standard” for performance

V1

V3

V2

Fan-out = 1

t

V5

2 N tp

V2

5

Ring Oscillator

Do tp = 100ps mean 10 GHz chip?

Good Custom Design ≈ 1/10

Synthesized design ≈ 1/50 - 1/100

Why?Low load

V5V4V3V2V1

Low loadShort WiresFan-out = 1Low complexity

Power Dissipation

Two measures are importantPeak power (Sets wire dimensions)Peak power (Sets wire dimensions)

Average power (Battery and cooling)

maxpeak DD DDP V i= ×

0

( )T

DDav DD

VP i t dtT

= ∫

Power-Delay Product

( ) PDP t P J

Energy per operation

( ) p avPDP t P J= ×

Energy per switching event

Digital IC-Design

The CMOS Inverter

6

Inverters

On-chip resistors are largeSt ti ti

VDD

Static power consumptionVOL ≠ 0Large tpLH

VDD

GND

Extra process step

GND

Extra process step Static power consumptionVOL ≠ 0Large tpLH

The CMOS Inverter

+ Lower static power

tiVDD

consumption

+ VOH = VDD; VOL = 0

+ tpLH = tpHL If properly designed

+ Low Impedance connection

to ground and VDD

- More fab. stages

- Lower hole mobilityGND

The CMOS Inverter

VDD

Shared power and ground

GND

VDD VDD

Cascaded Abuted cells

Out

GND

In Out

GND

In

The CMOS Inverter

VDD Wider PMOS to compensate for lower mobility

GND

lower mobility

VDD

VDD

Out

GND

In Out

GND

In

7

CMOS Inverter - Model

Complementary i.e. output have always a low impedance R

VDDy p

connection to GND or VDD

VOH = VDD

VOL = 0CL

R

Req-p

VM = f(Req-n, Req-p)

VM = VDD/2 if Req-n = Req-p

Req-n

CMOS Static Behavior

Load characteristicsLoad characteristicsVTCSwitching thresholdNoise marging

Load Lines

N-channel P-channel

ID VGS=5V

VGS=4V

VDS

ID

VGS=-4V

VGS=-3V

VDS

VGS=3V

GS

VGS=-5V

Inverter Load Characteristics

IDIDn = -IDp

V V VVGS=5V

The VTC can be determined graphically

IDn VGS=5VVin=0V - IDp

VDS

Vin = VDD-VGSp

VGS=3V

VGS=4V

VGS=-3V Vout= VDD-VDSp

VDS

VGS=3V

VGS=4V

Vin=2V

Vin=1V

VGS=-5V

VGS=-4V

Vin =VDD-VGSp

Vout =VDD-VDSp

out DD DSp

8

Inverter Load Characteristics

IVin=5VVin=0V

Vin=3V

in

Vin=4V

in

Vin=2V

Vin=1V

Vout

Vin=2VVin=3VVM

Region: Linear - Saturation

V5

N off N sat

IVin=5VVin=0V

VOUT

2

3

4

N satP sat

N offP lin

N satP lin

Vout

Vin=3V

Vin=4V

Vin=2V

Vin=1V

Vin=2VVin=3VVM

1 2 3 4 5VIN

1N linP off

N linP sat

CMOS Inverter VTC

VTC graphically extracted from the l d li

5

load lines

High noise margin NMH=VOH-VIH ≈ 5-2.9 = 2.1VNML =VIL-VOL ≈ 2.1-0 = 2.1V

VOUT VOH= VDD

2

3

4

VM= VDD/2

1 2 3 4 5VIN

1

VOL= 0

Switching Threshold

Both transistors are saturated

Long Channel Transistors

2 2( ) ( ( ) )2 2

( )

( )

pnM Tn M DD Tp

pM Tn M DD Tp

n

kk V V V V V

kV V V V V

kV V V V V

− = − − − − ⇒

− = − − + + ⇒

( )

( )1

M M Tn DD Tp

Tn DD Tp pM

n

V r V V r V V

V r V V kV with r

r k

+ × = + × + ⇒

+ + −⇒ = =

+

9

Switching Threshold

( )1

DD Tp Tn pM

n

r V V V kV with r

r k+ + −

= =+

(VTn = -VTp = 0.5 V)


VM

2

3

4

5

VM

2

3

4

5

1 64 8 10kp/kn

1

2

1

0.1 10.32 3.2 10kp/kn

Wp≈3Wn

Switching Threshold

5

( )1

DD Tp Tn pM

n

r V V V kV with r

r k+ + −

= =+

VM

2

3

4

Moderate deviation from kp/kn = 1 gives only small changes in VM

W 2W t 1

0.1 10.32 3.2 10kp/kn

Wp = 2Wn common to save area, since the change in VM is small

Switching Threshold: Example

Inverter with W/L = 0.6 μ / 0.35 μVTn = 0.50, kn = 300 μ, VTp = - 0.65, kp = -103 μ

103 0.59300

p

n

kr

kμμ

−= = =

( )1

DD Tp TnM

r V V VV

r+ +

= =+

VDD = 3V

1

0.59 (3 0.65) 0.5 1.181 0.59

r

V

+

− +=

+ GND

2.5

Balanced 0.25μm inverter

Simulated VTC: Short Channel

1

1.5

2

Vou

t(V)

0 0.5 1 1.5 2 2.50

0.5

Vin

(V)

10

Minimum sized 0.25μm transistors

VTC: Short Channel

V = 2 5ID (mA)0.25

0.3750.25

p

p

WL

=

0.3750.25

n

n

WL

=

VGS 2.5

V = 1 0

VGS = 1.25

VGS = 1.875

ID (mA)0.20

0.15

0.10

0.05 PMOS

VGS = -1.875VGS = -1.5

VGS = 1.0

VGS = 0.625VGS = -0.625

VGS = -2.5

-2.5 -0.5-2.0 0-1.5 -1.0 2.50.5 2.01.51.0

0

-0.05

-0.10VDS (V)

VGS = -1.25

NMOS

VTC: Short Channel

0.25

0.20VIN = 2.5

ID (mA)

0 25

VIN = 0.625

VIN = 00.10

VIN = 1.25

VIN = 1.875

V = 1 0V = 1 0

VGS = 2.5

VGS = 1.0

VGS = 0.625

VGS = 1.25

VGS = 1.875

VGS = -0.625

ID (mA)0.25

0.20

0.15

0.10

0.05

0VGS = -1.25

Move the PMOS part to the first quadrant

VOUT (V)0 2.50.5 2.01.51.0

VIN = 0.625VIN = 1.875

VIN = 1.25VIN = 1.0VIN = 1.0

VGS = -1.875VGS = -1.5VGS = -2.5

-2.5 -0.5-2.0 0-1.5 -1.0 2.50.5 2.01.51.0

-0.05

-0.10VDS (V)

Vout (V)

2.5

2 0

VTC: Short Channel - Graphically 0.25

0.20VIN = 2.5

ID (mA)

0.5

2.0

1.5

1.0

VTC

VIN = 00.10

VIN = 1.875

Vin (V)

0 2.50.5 2.01.51.0

VIN = 0.625

VOUT (V)0 2.50.5 2.01.51.0

VIN = 0.625

VIN = 1.25

VIN = 1.875

VIN = 1.25VIN = 1.0VIN = 1.0

Switching Threshold: Short Channel

Vout (V)

2.5

The threshold VM is when VIN=VOUT

2.0

1.5

1.0

VM =1 V

Vin (V)

0 2.50.5 2.01.51.0

0.5

11

Both NMOS and PMOS are velocity saturated

Switching Threshold: Short Channel

22

(( ) ) (( ) )2 2

Solving yields

DSATpDSATnn M Tn DSATn p DD M Tp DSATp

M

VVk V V V k V V V V

V

− − = − + +

2 2 where

1

DSATpDSATnTn DD Tp

p DSATpM

n DSATn

VVV r V Vk V

V rr k V

⎛ ⎞+ + + +⎜ ⎟

⎝ ⎠= =+

Minimum transistor dimensions

0.63; 1; 0.43; 0.4;DSATn DSATp Tn TpV V V V= =− = =−

Example 0.25 μm technology

Parameters from the inside back 0.375 0.375115 172.5; ( 30) 45

0.25 0.25

45 ( 1) 0.41172.5 0.63

n p

p DSATp

n DSATn

k k

k Vr

k V

= × = = × − =−

− × −= = =

×

the inside back cover in the book

0.63 10.43 0.41 2.5 0.42 2 2 21 1

DSATpDSATnTn DD Tp

M

VVV r V VV

r

⎛ ⎞ ⎛ ⎞+ + + + + + − −⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠= =+

1.0 V0.41

=+

IF VDD >> VDSAT and VT

⎛ ⎞

Example 0.25 μm technology

2 2 0.41 2.5 0.73 V1 1 1 0.41

DSATpDSATnTn DD Tp

DDM

VVV r V Vr VV

r r

⎛ ⎞+ + + +⎜ ⎟ ×⎝ ⎠= ≈ = =

+ + +

V not high enough in this caseVDD not high enough in this case

It is desirable to have VM around VDD/2

22 W VW V

Balancing the inverter

2' '

2

(( ) ) (( ) )2 2

Assuming = yields

p DSATpn DSATnn M Tn DSATn p DD M Tp DSATp

n p

n p

W VW Vk V V V k V V V VL L

L L

− − = − + +

2'

2'

(( ) )2

(( ) )2

DSATnn M Tn DSATnp

DSATpnp DD M Tp DSATp

Vk V V VWVW

k V V V V

− −=

− + +

12

Example using the same data

2 2


2 2'

2'

0.63(( ) ) 115 ((1.25 0.43) 0.63 )2 2 3.5130 ( 2.5 1.25 ( 0.4) )(( ) ) 22

DSATnn M Tn DSATn

p

DSATpnp DD M Tp DSATp

Vk V V VWVW

k V V V V

− − × − × −= = =

−− × − + − − −− + − +

To be balanced, The PMOS should be 3.5times wider than the NMOStimes wider than the NMOS

For the minimal NMOS with Wn=0.375 μm, the corresponding PMOS has Wp=1.3 μm


1 5

1.6

1.7

1.8

0 8

0.9

1

1.1

1.2

1.3

1.4

1.5

MV(V

)

VM is rather insensitive to changes in the device ratioA ratio decrease from 3.5 to 2 yields VM = 1.13 V which often is acceptableSaves area

100

1010.8

W p/W n

2

Determining VIH and VIL

VIH and VIL when the slope is -1

1OUT

in

VV

∂⇒ =−

∂

1.5

2

2.5

Vou

t(V)

in

A reasonable approximation is

to use the gain (g) around VM

0 0.5 1 1.5 2 2.50

0.5

1

Vin

(V)

V

OUT

in

VgV

Δ=

Δ


A simplified piecewise linear VTC

Vout (V)

2.5 VIL

p2.0

1.5

1.0 VM

OUT

in

VgV

Δ=

Δ

Vin (V)

0 2.50.5 2.01.51.0

0.5

VIH

13


DD M

IL M

V VgV V

−=

−Vout (V)

2.5 VIL

OUT

in

VgV

Δ=

Δ

IL M

DD MIL M

V VV Vg

V

−= +2.0

1.5

1.0 VM

IL

V -V

VDD-VM

M

M IH

MIH M

VgV V

VV Vg

=−

= −Vin (V)

0 2.50.5 2.01.51.0

0.5

VIH

VM-VIL

The Inverter Gain (g)

1 1( ) ( )( )

n DSATn p DSATp

DSAT

k V k V rg VI V λ λ λ λ

+ += − ≈ −

−

Derived at page 189

( ) ( )( )2

DSATnD M n pM Tn n p

VI V V Vλ λ λ λ− − −

-8

-6

-4

-2

0

Note that the gain is very sensitive to the

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

8

Vin (V)

gain

ychannel-length

modulation

Noise Margins

Vout (V)

2.5 VIL

DD MIL M

V VV Vg−

= +

2.0

1.5

1.0 VM

IL

V -V

VDD-VM

;

MIH M

gVV Vg

NM V V NM V

= −

= − =

Vin (V)

0 2.50.5 2.01.51.0

0.5

VIH

VM-VIL ;H DD IH L ILNM V V NM V= =

Example (Minimum sized transistors)

Vout (V)

2.5 VIL

1

( )( )2

DSATnM Tn n p

rg VV V λ λ

+≈ − =

− − −

2.0

1.5

1.0 VM

IL

V -V

VDD-VM

( )( )2

1 0.410.63(1 0.43 )(0.06 0.1)

2

M Tn n p

+= − =

− − +

Vin (V)

0 2.50.5 2.01.51.0

0.5

VIH

VM-VIL

34.6= −

14

Example (Minimum size transistors)

Vout (V)

2.5 VIL

2.5 11 0.96 V34.6

DD MIL M

V VV Vg− −

= + = + =−

2.0

1.5

1.0 VM

IL

V -V

VDD-VM

11 1.03V34.6

2.5 0.96 1.54 V1 03V

MIH M

H DD IH

VV Vg

NM V VNM V

= − = − =−

= − = − == =

Vin (V)

0 2.50.5 2.01.51.0

0.5

VIH

VM-VIL 1.03VL ILNM V= =

Slightly to large values due to the

approximation

CMOS Dynamic Behavior

CapacitorsPropagation delayPower consumption

Inverter Load

CL

Vin Vout

Capacitance model for propagation

d l l l ti

Cdb2 C 4C d2Vi V t

VDD

V t2

delay calculations

Cdb1

Cdb2 Cg4

Cg3Cw

Cgd2Vin Vout

Cgd1

Vout2

Inverter Load

Overlap Capacitance

Junction CapacitanceWi C i

gd

db

C

CC

=

=

Wire CapacitanceOverlap & Gate Capacitance

w

g

CC

=

=VDD

Cdb1

Cdb2 Cg4

Cg3Cw

Cgd2Vin Vout

Cgd1

Vout2

15

Cgd - Overlap Capacitance

Assumed to be in Cut-off or Saturation- No Channel Capacitance (at output side)

Only Overlap Capacitance

VDD

- Only Overlap Capacitance

Cdb1

Cdb2 Cg4

Cg3Cw

Cgd2Vin Vout

Cgd1

Vout2

The Miller Effect

If Cgd is modeled from Vout to GND the value shall be doubledGND, the value shall be doubled

Cgd

VΔΔV

2C dVΔ

ΔV

2Cgd

Cgd = 2 Cgd0 W

Cdb - Junction Capacitance

0 db eq jC K C= ×

VDD

Depends on grading coefficientDiode area and perimeter

Cdb1

Cdb2 Cg4

Cg3Cw

Cgd2Vin Vout

Cgd1

Vout2

Cw - Wire Capacitance

Neglected on short distancesI d i t i t h l i

VDD

Increased importance in new technologies

Cdb1

Cdb2 Cg4

Cg3Cw

Cgd2Vin Vout

Cgd1

Vout2

16

Channel Capacitance

Region C g C gs C gd

Cut off C WL 0 0Cut off C OX WL eff 0 0

Linear 0 (1/2)C OX WL eff (1/2)C OX WL eff

Saturation 0 (2/3)C OX WL eff 0

Cut off: No channel ⇒ CG = CGB

Linear: Channel ⇒ Divide channel in two parts

Saturation: ≈ 2/3 Channel connected to source

Cg - Gate Capacitance

Overlap – Cgs (Not Cgd)

Ch l WLC

VDD

Channel – WLCox

Cdb1

Cdb2 Cg4

Cg3Cw

Cgd2Vin Vout

Cgd1

Vout2

Inverter Load Model

Capacitor Expression

C d 2C d0W

Vin VoutCL

ModelCgd 2Cgd0W

Cdb Keq(ACj+PCjsw)

Cg Cgs0W+CoxWL

Cw Area + Fringe Cap.w g p

The values differ for n- and p-channel

The values differ for L to H / H to L

Se table 5-2

Inverter - Transient Response

-

90 10(1- ) ; -t

RCout rV e V t t t= =

10 10t t− −

VDD

10

0.1 (1 ) 0.9ln(0.9)

RC RCDD DDV e V e

t RC= − ⇔ = ⇔

= −

90 ln(0.1)

( l ( ) l ( ))

t RC= −CL

Req-p

90 10 ( ln(0.1) ln(0.9)) 2.2r rt t t RC t RC= − = − + = =

50 ln(0.5) 0.69pHL pHLt t RC t RC= = − = =

Req-n

17

Req in Short Channel Transistors

( ) ( / 2)V V V VR R+( ) ( / 2)-

( ) ( / 2)

2OUT DD OUT DDn V V n V V

eq n

DS DS

D DV V V V

R RR

V VI I

= =

= =

+= =

⎡ ⎤ ⎡ ⎤+⎢ ⎥ ⎢ ⎥

⎣ ⎦ ⎣ ⎦( ) ( / 2)- 2

OUT DD OUT DDD DV V V Veq nR = =⎣ ⎦ ⎣ ⎦

=

Chapter 5

Digital IC-Design

The CMOS Inverter

Cont.


Graphical Method

0 15

(mA)DI2 VV

In Velocity Saturation 0 5

0.1

0.15 2 VGSV =

/ 2 145 AD VDDI μ=

153 AD VDDI μ=

Saturation

(V)DSV0

0.5

0 1 20.63 V


/ 2 145 A; 153 A; DVDD D VDDI Iμ μ= =

Graphical Method

/ 2

( ) ( / 2)OUT DD OUT DD

DVDD D VDD

DS DS

D DV V V V

V VI I

R

μ μ

= =

⎡ ⎤ ⎡ ⎤+⎢ ⎥ ⎢ ⎥

⎣ ⎦ ⎣ ⎦= =-

6 6

-

22 1

153 10 145 10 10 k2

eq n

eq n

R

R− −+

× ×= = Ω

18


Model Based Method

1 3 52 12 (1 ) 4 6(1 )

2

DD

DD DDeq DD

DDDSAT DD DSATDSAT

VV VR VVI V II

λλ λ

⎛ ⎞⎜ ⎟ ⎛ ⎞= + ≈ −⎜ ⎟ ⎜ ⎟+ ⎝ ⎠⎜ ⎟+⎝ ⎠

2

with ( )2DSAT

DSAT DD T DSAT

VI k V V V

⎛ ⎞= − −⎜ ⎟⎜ ⎟

⎝ ⎠

In Velocity Saturation

Req for Short Channel NMOS

Find IDSAT0.1

0.15

(mA)DI

2 VGSV =

' 2

2

2 V; 0.43 V;

0.63 V; 115 mA/V0.375 m; 0.25 m

DD T

DSAT n

V V

V kW

VW

μ μ

= =

= == =

⎛ ⎞

(V)DSV0

0.5

0 1 20.63 V

DSATI

IDSAT = ID whenV = 0'

2

( )2

0.375 0.63115 (2 0.43)0.63 136 A0.25 2

DSATDSAT n DD T DSAT

DSAT

VWI k V V VL

I μ

⎛ ⎞= − − =⎜ ⎟⎜ ⎟

⎝ ⎠⎛ ⎞

= − − =⎜ ⎟⎝ ⎠

VDS = 0(extrapolated)


136 A; =0.06 VDSATI μ λ=

1 3 52 12 (1 ) 4 6(1 )

2

21 2 3 2 52 1 0 06 2

DD

DD DDeq DD

DDDSAT DD DSATDSAT

VV VR VVI V II

R

λλ λ

⎛ ⎞⎜ ⎟ ⎛ ⎞= + ≈ −⎜ ⎟ ⎜ ⎟+ ⎝ ⎠⎜ ⎟+⎝ ⎠

⎛ ⎞⎜ ⎟ ⎛ ⎞= + ≈ − ×⎜ ⎟ ⎜ ⎟6 6

61 0.06 222 136 10 (1 0.06 2) 4 136 10 6136 10 (1 0.06 )

2

10.0 k 9

eq

eq

R

R

− −−

+ ≈ ×⎜ ⎟ ⎜ ⎟× + × × ⎝ ⎠⎜ ⎟× + ×⎝ ⎠

= Ω ≈ .9 k (1 % error)Ω

Inverter - Transient Response

VDD

3 15

3 15

2 ; 10

2.2 2.2 10 10 2 10 44

0 69 0 69 10 10 2 10 14

L eq n

r

C fF R k

t RC ps

RC

−

−

= = Ω

= = × × × × =

CL

Req-p

3 150.69 0.69 10 10 2 10 14pHLt RC ps−= = × × × × =Req-n

19

Inverter - Propagation Delay

2 2

( - ) / 2 / 2

( ) ( )

L OH OL L DD

n n

Q C U C V V C Vk kQ I t V V t V V t

= ×Δ = =


V

2 2

2

( - ) ( - )2 2

( - )1 1( )

n nGS T pHL DD T pHL

L DD LpHL

n DD T n DD

L

Q I t V V t V V t

C V Ctk V V k V

C

= × = × = ×

= ≈

CL

1 1( )2

Lp

DD n p

CtV k k

= +

Ideal Vin (Step)

Propagation Delay (page 202)

Short Channel

Transistors

V

30.694

0.52( )

2

L DDpHL

DSAT

L DD

DSATnn DSATn DD Tn

C VtI

C VVk V V V

= =

=− −

Transistors

CL

Ideal Vin (Step)

Propagation Delay Simulation

5x 10

-11

Short Channel Transistors

pLHtpHLt Fan-Out = 1

CL

V

3.5

4

4.5

t p(sec

)

( )pt spt

1 1.5 2 2.5 3 3.5 4 4.5 53

ββ = Wp/Wn

A ratio around 2 is close to optimum

What Ratio Should be Chosen?Short-channel

Transistors

Fan-Out = 1pW

Wβ =

V pW

β=3.5 balance the inverter (VM=VDD/2)

β=2 (or 2.4) for equal delays (tpLH=tpHL)

nW

CLnWHowever, β=2 might be acceptable (VM≈0.45 VDD)

20

Effect of Input Rise Time

tpHL Increase linearly with the

0 35

tpHL [ns] Note the gain

input rise time trise

0.30

0.35

0.25 22

( ) ( ) 4r

pHL actual pHL steptt t= +

gain

0.60.4 0.8 1.0

trise [ns]0.2

0.20

0.15

Digital IC-Design

Driving a Large Fan-out

Inverter Chain

OutIn

If CL is given:- How many stages are needed to minimize the delay?

CL

How many stages are needed to minimize the delay?- How to size the inverters?

Driving a Large Fan-Out

Typical examples:

Busses

Driving a large capacitance

Clock network

Control wires (e.g. set and reset signals)

Memories (driving many storage cells)

VDD

Worst case:

Off chip signalsCL

21

Inverter with Load (External only)

Delay

Load (Cext)

Cext

Req

Req

tp = 0.69 Req Cext

Internal (intrinsic) load is neglectedNot the case in modern technologies

Inverter with Internal Load

Delay

External Load

Cint Cext

tp = 0.69 Req (Cint + Cext)

Self-loading if Cint dominateShould be avoided

3.6

3.8x 10

-11

Device Sizing (W scaled with S)

(for fixed load) External load

2.6

2.8

3

3.2

3.4

t p(sec

)

Self-loading effect:Intrinsic capacitancesdominate (W is to

capacitancesdominate

2 4 6 8 10 12 142

2.2

2.4

S

(wide compared to the load)

Driving Large Capacitances

Cint = Intrinsic capacitance

Cext = Extrinsic capacitance

Req

Req = Resistance in channel

VDD

Cint = Cdb+Cgd

Req

ext w gC C C= +

Cw = Wire capacitance

Cg = Gate C in next stage

Cint

DD

Cext

Req

Req

22

Scaling to Increase Driving Capability

Scaling W with a factor S:Req

Cint = Cdb+Cgd

Req

int iref

refeq

C C

RS

R

S= ×

=VDD

Cint

DD

Cext

Req

Req

Scaling to increase driving capability

Delay RC-model

0.69 ( ) 0.69 (1 )extp eq int ext eq int

Ct R C C R C= + = +

0

0.69 ( ) 0.69 (1 )

0.69 (1 ) (1 )

p eq int ext eq intint

ref ext extp iref p

iref iref

t R C C R CC

R C Ct SS

C tCS S C

+ +

= + = +

Scaling with a factor S

tp0 = intrinsic delay

Independent of S

Scaling Example (page 206)

0 19.3 ; 3.15 ; 3.0

1p ext ireft ps C fF C fF

C

= = =

01(1 ) 19.3 (1 )

1.05ext

p piref

Ct tS

psC S

= + = +×

C CCiref Cext

Scaling Example (page 206)

119.3 (1 )1.05p p

St s= × +

×

30

40tp (ps) S =5, Substantial improvement

S >10, ”No more gain”

0S

5 10 15

10

20

23

Sizing a Chain of Inverters

int, jC=

Cγγ = Capacitive proportionality

factor for each inverterg, jC

2 N1

- Technology Dependent

- Independent of the size (W)

- Close to 1 in Submicron

The in- and output

capacitive ratio

Cg,N+1= CLCg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N


, 1

,

g j

g j

Cf =

C+

2 N1

f = The loading capacitive ratio in two following stages



int, j g, jC = Cγ , 1

,

g j

g j

Cf =

C+

, , 1, 0 0 0

, ,

(1 ) (1 ) (1 )ext j g j jp j p p p

int j g j

C C ft t t t

C Cγ γ+= + = + = +

2 N1



,2 ,3 , , 1

,2, , ,1 , 1

g g g j Lg j

g g j g j g Ng

C C C Cf =

C C CC

C C+

−

= = = =

Total Delay:

Known

2 N1

01(1 )

Nj

p pj

ft t

γ=

= +∑

Total Delay:

If each stage is scaled with the same factor f


24


,2

,1g

gCf =

C

C NLNf = CC

F=Known

2 N1

,3

,

,1

2

1g

g

N L

gCf =

f =

C

CC

F F= ( =overall effective fan-out)

,1gCKnown


Sizing a Chain of Inverters Nf F=

0 01(1 ) (1 )

NNj

p p pj

f Ft t N tγ γ=

= + = × + =∑

(1 )fefγ

+

=

Optimum is found by setting the derivative to 0

Cg,N+1= CL

2 N

Cg,1

1

Cint,1 Cg,2 Cint,2 Cg,N Cint,N


(1 )fefγ

+

=Has no closed form

solution except for γ=0f so u o p o γ 0

γ=0 when intrinsic capacitance is neglected

f e= Otherwise: f is solved numerically

Cg,N+1= CL

2 N

Cg,1

1

Cint,1 Cg,2 Cint,2 Cg,N Cint,N

6


Too many stages

p

popt

tt

Normalized delay

, 1

,

g j

g j

Cf =

C+

6

4 Common Practice Around 4

f

2

1 2 543

1(1 ) fef

+=for

25

Buffer Design

1 64

N f tp

1 64 65

1

1

8

64

64

644 16

1 64 65

2 8 18

3 4 15

1 642.8 8

16

22.6 4 2.8 15.3

Inverter Chain

Common practice:

O tI1

Optimum fan-out around f=4

4 16OutIn

CL

Digital IC-Design

Power Consumption

Dynamic Power Consumption

VDD22

Energy charged in a capacitor

L DDC VC VCharge

2

2 2

Energy is also discharged, i.e.

L DDC

C

tot L DD

C VC VE

E

E C V

= =

=

Discharge2

Power consumption L DDP f C V=

26

Note: The power is dissipated in the transistor

VDD

Dynamic Power Consumption

dissipated in the transistor resistance, Req

However: the power consumption is independent of the value of Req

Charge

of the value of Req

P = CL VDD2 f

Discharge

Current Spikes – Direct Path

Current peak when both N-and PMOS are 2 2 2

peak r peak f r fdp DD DD DD peak

I t I t t tE V V V I

× × ×= + =

open

2r f

dp DD peak

t tP V I f

×=

VDD-VT

VT

N openP open

Ipeak

Static Power Consumption

Ileakage increases with decreasing VT

VPstat =Ileakage × VDD

Drain leakageto bulk &

VDD

0to bulk &drain-sourcesubthresholdcurrent

Dynamic vs. Static Power

The dynamic and static power is aboutequal in the 65 nm Technology

ized

pow

er 1

0.01

100

65 nm

Dynamic power

Nor

mal

1990 20200.0000001

0.0001

20102000

Static powerYear

Source: ITRS

27

Digital IC-Design

Power Delay Product

(PDP)(PDP)

Power-Delay Product

Helps to measure the quality of different circuit topologies


For static CMOS

22 2 ( )

2 2 p L DD

p L DD max p L DDp

t C VPDP P t C V f t C V Jt

×= × = × × × = × × =

Independent of operating frequency

Power-Delay Product


2L DDC VPDP P ×

If we lower the supply, the

Energy and performance

2L DD

pPDP P t= × =

2C V×

PDP will be reduced, but also the performance

Some claims that EDP is a 2

2L DD

p pC VEDP P t t×

= × = × Some claims that EDP is a better measure since it includes the delay

Some Examples - Cascaded Inverters

Minimal Design Compensated to Decrease tpLH

Out

VDD

In Out2 fF

10 kΩ

30 kΩ

10 kΩ

15 kΩ

10 ; 30 ;

4eq n eq p

Min

R k R k

C fF− −= Ω = Ω

=

GND

1 fF + 2 fF 3 fF1 fF +

10 ; 15 ;

6

eq n eq Comp

Comp

R k R k

C fF− −= Ω = Ω

=

28

Propagation Delay

10 ; 30 ; 15 ;

4 ; 6 ; 2eq n eq p eq Comp

Min Comp DD

R k R k R k

C fF C fF V V− − −= Ω = Ω = Ω

= = =

Not much faster but

0.69 28

0.69 83

0.69 41

0.69 62

pHL Min Min eq n

pLH Min Min eq p

pHL Comp Comp eq n

pLH Comp Comp eq Comp

t C R ps

t C R ps

t C R ps

t C R ps

− −

− −

− −

− −

= × × =

= × × =

= × × =

= × × =

VDD

55

52

2

2

pHL Min pLH Minp Min

pHL Comp pLH Compp Comp

t tt ps

t tt ps

− −−

− −−

+= =

+= =

more symmetric

Out

VDD

GND

In OutIn

Power Consumption at Max Speed

4 ; 6 ; 2

1 19 1 9 7

Min Comp DDC fF C fF V V

f GH f GH

= = =

Compensating

2 2

2 2

9.1 ; 9.72 2

1 1402

1 2302

Max Min Max Compp p

Min Min DD Max Min L DDp Min

Comp Comp DD Max Comp L DDp Comp

f GHz f GHzt t

P C V f C V Wt

P C V f C V Wt

μ

μ

− −

−−

−−

= = = =

= × × = × × =

= × × = × × =

VDD

gives higher power

consumption

Out

VDD

GND

In OutIn

Power-Delay Product

22 2 ( )

2 2 p L DD

p L DD max p L DDp

t C VPDP P t C V f t C V Jt

×= × = × × × = × × =

2

2

82

122

Min DDMin

Comp DDComp

C VPDP fJ

C VPDP fJ

×= =

×= =

VDD

Compensating gives higher energy per

switching event

Out

VDD

GND

In OutIn

Total Power Consumption and PDP

tot dyn dp statP P P P= + + =

2

2r f

L DD DD peak leakage DD

t tC V f V I f I V

+= + +

2

( )2

L DDp

C VPDP P t J×= × =

chapter 5 fundamental parameters the cmos inverter for ... · the cmos inverter digital ic-design...

Documents