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Al-Daloo M, Yakovlev A, Halak B.

Energy Efficient Bootstrapped CMOS Inverter for Ultra-Low Power

Applications.

In: 23rd IEEE International Conference on Electronics Circuits and Systems.

2016, Monte Carlo, Monaco: IEEE

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Date deposited:

21/12/2016

Energy Efficient Bootstrapped CMOS Inverterfor Ultra-Low Power Applications

Mohammed Al-daloo and Alex YakovlevSchool of Electrical and Electronic Engineering

Newcastle UniversityNewcastle upon Tyne, UK

Email: m.i.t.tawfeeq, Alex.Yakovlev@ncl.ac.uk

Basel HalakSchool of Electronics and Computer Science

University of SouthamptonSouthampton, UK

Email: bh9@ecs.soton.ac.uk

Abstract—This paper describes an energy efficient boot-strapped CMOS inverter for ultra-low power applications. Theproposed design is achieved by internally boosting the gatevoltage of the transistors (via the charge pumping technique),and the operating region is shifted from the sub-threshold to ahigher region, enhancing performance and improving toleranceto PVT variations. The proposed bootstrapped driver uses fewertransistors operating in the sub-threshold region, and consistsof two stages. The first stage is a normal driver with PMOSand NMOS transistors that are driven by the enhancing voltagecircuit (stage 2) which generates voltage levels theoreticallybetween -VDD for pulling up to 2VDD for pulling down. Ouranalysis shows that the proposed implementation achieves around20% reduction in energy consumption compared to conventionaldesigns under a supply voltage of 0.15V VDD .

Index Terms—ultra-low power (ULP); interconnect; chargepump; driver; boosting.

I. INTRODUCTION

The rapid development of energy-constrained applicationshas made low power design, a primary concern. This isa paradigm shift from traditional performance-led designto emerging energy-constrained system development. Novelapplications such as IoT devices, wearable computing andsmart grids mainly require longer energy source life and smallsilicon costs; on the other hand, their performance is typicallyconsidered a secondary concern.

Recently, scaling the power supply has become an effectiveway to reduce energy consumption in digital systems. Supplyvoltages less than the threshold voltage of the CMOS (com-plementary metal-oxide semiconductor) circuits have emergedshowing the ability to meet the requirements of ultra-lowpower regime (ULP). This approach is called the sub-thresholdlogic circuit. However, since CMOS scaling reaching its limits,the issue of global and long interconnects has become animportant consideration for circuits in high speed systems dueto the problem of capacitance [1].

At sub-threshold this effect is even worse, for instance,when the conventional CMOS driver needs to be as large aspossible to deal with the leak of driving efficiency associatedwith a scaled power supply [2]; in addition, it requires to bearwith a static current Ioff issue which is increasing at thisregion, particularly, in the nanometre regime [3].

In this paper, the bootstrap method is proposed because ofits capability to improve the driving ability without increasingthe circuit power consumed, as shown below in the resultssection. The bootstrapped CMOS inverter provides betterperformance and reduces leakage current by producing avoltage swing nearly of 2VDD to -VDD and driving the Vgs(gate to source transistor voltage) of the NMOS and PMOSrespectively. Hence, according to the formula for I-V in a sub-threshold regoin [4], [5], Ioff will be reduced exponentially.

The rest of the paper is organized as follows. Section IIintroduces the operation of the circuit and its structure. SectionIII describes implementation considerations and presents thecircuit design and initial simulation results for this circuitand compares it with previous designs [2] and [6], as wellas with a conventional driver from the point of view ofenergy consumption and delay. In addition, the conclusionsare presented in section IV.

II. PROPOSED CMOS INVERTERA. Charge pump technique

In our approach, the bootstrap has been used based on acharge pump that is a type of DC-to-DC converter, whichutilities a capacitor as charge holder to generate a voltagehigher than the power source voltage [7]. Although the designof this technique is electrically a simple circuit, it is able toachieve a level of efficiency reaching 90-95% [8]. To see howthis is possible, consider a simple 4-stages Dickson chargepump as shown in figure 1. When the signal φ1 is low, D1 willcharge C1 to Vin. When φ1 goes high, the top plate of C1 ispushed up to 2Vin. D1 is then turned off and D2 turned on andC2 begins to charge to 2Vin. On the next clock cycle, φ1 againgoes low and now φ2 goes high, the top plate of C2 is pushedto 3Vin. D2 switches off and D3 switches on, charging C3 to3Vin and so on with charge passing up the chain hence, thename ’charge pump’. The final diode-capacitor cell representsa peak detector and not a multiplier in the cascade [8].

However, this technique increases the supply voltage effi-ciently, and this only includes the positive part of the voltage;that is, Vo will swing just from 0 to 2 or 3 Vin. So wehave modified the cross-coupled MOSFET voltage doubler togive a full swing from -VDD to 2VDD. The schematic of ourapproach is highlighted in figure 2.

Fig. 1. Four-stages Dickson charge pump [8].

Fig. 2. Circuit of the proposed driver.

The ideal operation of the circuit is divided into two states.The first state is when Vin goes low, that pushes PM1, PM3and NM2 on, and thus CbootN is charged to -VDD. At the sametime, the supply voltage VDD together with CbootP voltage ispulling up to 2VDD the voltage of the output, where stronglyswitch off the PM2 and any PMOS connected to this terminal(Out). A similar but opposite process takes place in the secondstate when Vin goes high; hence, NM1, NM3 and PM2 willbe on, so CbootP is charging to VDD and inversely CbootN

charges to -VDD which will appear on the output (Out) whereyields PM2 switches on strongly and any PMOS connectedto the circuit’s output (Out). The size (W/L) of transistors(PM1, PM3, NM1 and NM3) is 200 nm/160 nm and (PM3and NM3) is 120 nm/80 nm.

We have used this approach to improve the driving capa-bility of the CMOS circuits due to the increase in the sub-threshold swing which increases the driving current exponen-tially. In this report the charge pumper is used in the stagejust before the interconnect driver, which means that its effectwill be implicit; in other words, it will be used as a booster(bootstrap) for the final stage.

B. Circuit design

The bootstrap driver consists of two combinations. Ingeneral, the first one is a pre-driver that has the ability

to theoretically provide a voltage swing between -VDD and2VDD to enhance the driving capability of the next stage.The second stage is a normal buffer (inverter) with PMOSand NMOS transistors that are driven by the boosting voltagecircuit. Figure 2 shows the circuit scheme of the proposeddriver and its stages, where the pre-driver is the circuit in themiddle which uses the capacitors to boost the voltage. Thenthe buffer, which is the circuit on the right, is used to drive theinterconnect with a sub-threshold voltage swing from GND toVDD.

C. Boosting efficiency

The capacity of the boost capacitance (Cboost) together withparasitic capacitance (Cnode) of the transistors (PM2, PM3,NM2 and NM3) connected to the relevant node determinesthe efficiency of the boosting as in the following equations:

B =Cboost

Cboost + Cnode(1)

Vgsn(pulldown) = B · 2VDD (2)

Vgsp(pullup) = B · − VDD (3)

where the B is the booster efficiency factor, Vgsn is the gate-to-source of the N-type transistor, and Vgsp is the gate-to-source of the P-type transistor. Therefore, the efficiency of theboosting depends on the parasitic capacitance of the relevanttransistors as well as the boosting capacitance which shouldbe designed to be as large as possible to give better efficiency.Consequently, the ultimate stage of the driver circuit is pushedto a higher region owing to the boosted voltage, where thedischarge current In in the components exposed to this voltageis:

In = µCdepW

L

((B · 2VDD − Vth)VDD − 0.5V 2

DD

)(4)

where µ denotes the effective mobility, Cdep is the depletioncapacitance, W and L are the device width and length, andVth is the threshold voltage. As a result, the boosted voltageincreases the current driving capability. Moreover, not only isthe discharge current affected but also the equivalent resistance(Req) of the MOS transistor will improve according to thefollowing equation:

Req =VDS

I=

Vt

βe−B ·VDD

Vt

(5)

where β is the transistor strength, and Vt is the thermal voltage.So, depending on the above expression, the leakage currentwill decrease exponentially.

III. IMPLEMENTATION AND RESULTS

The driver circuit has been implemented using Cadence soft-ware in 90nm technology to measure the performance of thedesign. The circuit in figure 2 employs SPRVT transistor, 25 fFboost capacitors (Cboost and Cnode), and 200 fF capacitanceconnected to the driver output (CL) to emulate the 10 mminterconnect. The simulation was executed under a 150 mV

TABLE ITHE ACHIEVED VOLTAGE SWING AND BOOSTED COMPONENTS

Driver Voltageswing

No. of boostedcomponents

Conventional normal (GND – VDD) 0Proposed full-swing (-VDD – 2VDD) 4[2] full-swing (-VDD – 2VDD) 2[6] half-swing (GND –2VDD) 2

supply voltage and 5 MHz frequency as the input frequencyof the driver to imitate the worst case transition activity.

For ten clock cycles, the driver achieves average power andenergy consumed of 24 nW and 47.9 fJ/10cycle respectively,with 85.5 pW leakage power and 10.5 ns/cycle input to outputdelay. In another study, the estimated results were 1 µWaverage power and 0.1 pJ/cycle with leakage power 107 nWand operating frequency reaching 10 MHz [2]. Furthermore,the results of [6] were 1.7 µW and 0.34 pJ for total averagepower and energy respectively, and 833 nW leakage powerwhere, from the point of view of power leakage, this wasthe worst results so far among tested drivers. Even thoughthe proposed driver achieves the best results for power savingand energy efficiency, it has not achieved the best recordeddelay time which is normal as going deeper in sub-thresholdvoltage area. Owing to the number of components operatingin the boosted voltage as shown in table I, the proposed designscheme performs better than other previous works.

Moreover, an investigation has been conducted to find thetrade-off between the conventional buffer and the proposeddesign from the point of view of energy consumption andcircuit delay. Thus, to run this comparison, we repeated thesame experiments under the same circumstances except thatthe boosting technique was not used, in order to design thenormal buffer in such a way as to be close to a bootstrap driverdesign. The results were as predicted, where the conventionalbuffer, with the same proposed circuit’s transistors size wherePMOS (NMOS) W/L is 800 nm/100 nm (650 nm/100 nm),does not have the capability to drive the same load (200 fF)with 150 mV as the supply voltage to obtain the same transientresponse as the design with boosting. The transient responseresults for the two drivers are demonstrated in figure 3.

So the solutions are either splitting the load into 8 partsand using repeaters for each part with 25 fF, or increasing thesize of the normal buffer transistors so as to have the abilityto drive this load. Regardless of which solution is chosen, theboth situations lead to a power consumption increase. A largetransistors buffer, which its transistors approximately 12 timeslarger than these in proposal design, where PMOS (NMOS)W/L is 12.5 µm/100 nm, has been implemented so as to givea fair comparison with the bootstrapped design, where thetwo drivers have been designed to have the same rise andfall output waveform response.

The results of the experiments have been obtained byimplementing the UMC 90nm technology using the CadenceSpectre simulation toolkit.

The bootstrapped driver shows an improvement in energy

Time (s) ×10-60 0.5 1 1.5 2

Vol

tage

(V

)

0

0.05

0.1

0.15

output w/ boostinginputoutput w/o boosting

Fig. 3. Transient response waveform of drivers with same transistor size andcircumstances.

TABLE IISUMMARY OF COMPARISON RESULTS.

Item Buffer withoutboosting

Buffer withboosting

Averge power (W) 31.45 n 25.37 nTotal energy (J/10cycle) 62.9 f 49.97 fChip area estimated (µm2) 142.803 164.609Load (CL) (F) 200 fSupply voltage VDD (V) 150 m

consumption which is 20% less than the conventional driver.Moreover, the driver without boosting consumes by 24% morepower than the driver with boosting. This saving is due to thereduced leakage current which has a main role in the powerdissipation of sub-threshold circuits. Table II lists the resultsof this comparison when the supply voltage is 150 mV, theload is 200 fF and the frequency is 5 MHz.

However, the improvements in power and energy consump-tion of the proposed driver are accompanied by greater chiparea and circuit delay. Table II shows that the estimatedchip area of the proposed driver is 164.609 µm2 versus142.803 µm2 for the normal driver, which also gives lowerinput to output delay than the proposed design as shown infigure 4.

Supply voltage VDD

(V)0 0.2 0.4 0.6 0.8 1 1.2

Tim

e (s

)

10-10

10-9

10-8

10-7

Delay w boostingDelay wo boosting

Fig. 4. Drivers with/without boosting delay with 200 fF load and 5 MHzfrequency.

These results are normal from the area and delay pointof view if it has realized that the bootstrapped driver hasthree stages practically, which are an embedded inverter inthe booster stage, the pre-driver (booster) and the driver,in addition to the use of capacitors as shown in figure 2.Meanwhile the conventional driver is designed to have twostages, which are an inverter and a driver which require fewerbut larger transistors. Despite that, the main consideration inthis report is not the delay but the energy savings which havebeen achieved by using a boosting technique.

Another perspective is that of the buffer’s consumption ofenergy, which is shown in figure 5. Generally, the figureprovides the outcome of these experiments where the supplyvoltage has been changed from deep sub-threshold to nearsuper-threshold voltage, which obviously shows the advantageof the buffer with boosting compared to the one withoutboosting.

Furthermore, figures 6 and 7 show the improvements ofthe bootstrapped driver compared to the normal driver fromthe points of view of leakage power and energy efficiencywhich is, in this paper, the ratio of the useful energy to thetotal energy, where the leakage energy is considered a wastedenergy.

Supply voltage VDD

(V)0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Ene

rgy

(J/1

0cyc

le)

10-15

10-14

10-13

10-12

Consumption with boostingConsumption without boosting

Fig. 5. Energy power consumption of buffers under scaling of supply voltage.

Supply voltage VDD

(V)0 0.2 0.4 0.6 0.8 1 1.2

Pow

er (

W)

×10-8

0

2

4

6

8

leakage power w/o boostingleakage power w boosting

Fig. 6. Power leakage of the drivers.

Supply voltage VDD

(V)0 0.2 0.4 0.6 0.8 1 1.2

Ene

rgy

effic

ienc

y %

90

95

100

efficiency w boostingefficiency w/o boosting

Fig. 7. Energy efficiency of the drivers.

IV. CONCLUSION

Interconnect drivers used in ultra-low power regime forclock distribution networks and on-chip buses suffer fromconsiderable degradation in performance due to the fact thatwire capacitance has not been scaled as the supply voltageis scaled down. Added to that, there is an issue of perfor-mance variability at sub-threshold region. So our approach hasproposed using buffers with a charge pump booster, and thishas met the expectations of improvements in performance byreducing power consumption and increasing energy efficiency.The reason for this is that the current driving is improved dueto the exponential relationship between the transistor drain-to-source current and the gate-to-source voltage. The proposeddriver shows an improvement in energy consumption whichis 20% less than that of a conventional driver, and moreoverthe driver without boosting consumes 24% more power thanour driver which shows improvements compared to otherpreviously reported boosted drivers as well.

REFERENCES

[1] W. M. Arden, “The international technology roadmap for semiconduc-torsperspectives and challenges for the next 15 years,” Current Opinionin Solid State and Materials Science, vol. 6, no. 5, pp. 371–377, 2002.

[2] Y. Ho, C. Chang, and C. Su, “Design of a subthreshold-supply boot-strapped cmos inverter based on an active leakage-current reductiontechnique,” IEEE Transactions on Circuits and Systems II: Express Briefs,vol. 59, no. 1, pp. 55–59, Jan 2012.

[3] J. Kil, J. Gu, and C. H. Kim, “A high-speed variation-tolerant interconnecttechnique for sub-threshold circuits using capacitive boosting,” IEEETransactions on Very Large Scale Integration (VLSI) Systems, vol. 16,no. 4, pp. 456–465, April 2008.

[4] R. Dhiman and R. Chandel, Compact Models and Performance Investi-gations for Subthreshold Interconnects, ser. Energy Systems in ElectricalEngineering. Springer India, 2014.

[5] A. Tajalli and Y. Leblebici, “Design trade-offs in ultra-low-power digitalnanoscale cmos,” IEEE Transactions on Circuits and Systems I: RegularPapers, vol. 58, no. 9, pp. 2189–2200, Sept 2011.

[6] J. H. Lou and J. B. Kuo, “A 1.5-v full-swing bootstrapped cmos largecapacitive-load driver circuit suitable for low-voltage cmos vlsi,” IEEEJournal of Solid-State Circuits, vol. 32, no. 1, pp. 119–121, Jan 1997.

[7] B. Sklar, Digital communications: fundamentals and applications, ser.Prentice Hall Communications Engineering and Emerging TechnologiesSeries. Prentice-Hall PTR, 2001.

[8] W. J. Dally and J. W. Poulton, Digital Systems Engineering. CambridgeUniversity Press, 1998.