10kw three-phase sic pfc rectifier...10kw three-phase sic pfc rectifier semicon® europa, nov 13-18,...

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10kW Three-phase SiC PFC Rectifier

SEMICON® EUROPA, Nov 13-18, 2018, Munich, Germany

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Contents

• General PFC Concept

• 3 Phase System and PFC Control

• Simulation

• Understanding the losses

• 3 Phase PFC Implementation

• Results

2/2/20182

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General PFC Concept

2/2/20183

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DIODE BRIDGE

• DISTORTION FACTOR = 0.61• DISPLAC. FACTOR = 0.96• PF = 0.59

Definition of Power Factor

1,1 cos

(VA) PowerApparent

(W) Power Real

RMS

RMS

RMSRMS

avg

I

I

IV

PPF

DISPLACEMENT

FACTOR

DISTORTION

FACTOR

Real Power (W)

Reactive

Power

(VAR)φ1

VI

cos(1)

VI

• DISTORTION FACTOR = 1• DISPLACEMENT FACTOR < 1• PF < 1

• DISTORTION FACTOR < 1• DISPLACEMENT FACTOR = 1• PF < 1

POWER

FACTOR

V

I

• DISTORTION FACTOR = 1• DISPLACEMENT FACTOR = 1• PF = 1

PFC TARGET

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3 Phase System and PFC Control

2/2/20185

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3-phase PFC: Selected Topology

The 3-phase PFC control concept works as an inverter for motor application. Only the control strategy changes. This

configuration would allow to control the reactive power because of “Q” axis availability.

• 3 Half Bridges.

• Each half bridge connected to a input

phase voltage.

• Input voltages form a unique system.

Power Flow

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Goal of the PFC is to control the voltage across the inductors.

3 Phase PFC: Voltage Relationship, ABC Model

σ𝑖=𝐴,𝐵,𝐶 𝐸𝑖𝑀=0

𝐸𝐴𝑀 = ത𝐸 ∙ cos(𝜔𝑡)

𝐸𝐵𝑀 = ത𝐸 ∙ cos(𝜔𝑡 − 23𝜋)

𝐸𝐶𝑀 = ത𝐸 ∙ cos(𝜔𝑡 − 43𝜋)

-400

-300

-200

-100

0

100

200

300

400

0 0.005 0.01 0.015 0.02 A

B

C

EA,(t1)

EC,(t1)

EB,(t1)

ES

EB(t1)

EC(t1)

EA(t1)

SUPPLY VOLTAGE TIME

VECTOR SPACE

CS

C

SCNCNCL

BS

B

SBNBNBL

AS

A

SANANAL

iRdt

diLVuev

iRdt

diLVuev

iRdt

diLVuev

00,

00,

00,

VDC

A

B

C

N

0VN0

EAN

VA0

d1 d2 d3

VLA

SYSTEM VOLTAGE EQUATIONS IN „ABC“ DOMAIN

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Bus Voltage Limitation and Driving Capability

VOLTAGE SOURCE INVERTER

VDC

SAH

SAL

SBH

SBL

SCH

SCL

• When FETs are left “OPEN”, the HW is operating

as a diode bridge because of the FWD.

• The target DC BUS voltage has to be higher

than the line to line voltage amplitude:

𝑽𝑫𝑪 = 𝟔𝑬𝑹𝑴𝑺,𝑷𝑯𝑨𝑺𝑬

When the switches are modulating, the following vectors

can be provided in the vector space domain.

ES,MAX = 0.57 VDC

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System Reference: From 3φ Stationary To 2φ Rotating

A

B

C

EA,(t1)

EC,(t1)

EB,(t1)

ES

(αβ) = [T0]·(ABC)

A

B

C

α

β

φ

ES

CLARKE

α

β

𝜗

D

Q

ES

GE

OM

ETR

ICTIM

E

(DQ) = [T 𝜗𝑆 ]·(αβ)

PARK

Φ = 0

ϑ [rad]

EAM

EBM

ECM

-400

-300

-200

-100

0

100

200

300

400

ϑ [rad]

Eα

Eβ

ϑ [rad]

ED

EQ

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3 Phase PFC: (DQ) Model

2/2/201810

• Input quantities are transformed by means of

Clarke/Park matrix.

• ED EQ are the supply voltages expressed in the DQ

domain.

• iD, iQ are the phase currents in the DQ domain.

• ω is the fundamental frequency of the input

voltage.

• VD and VQ are the voltage generated by the control

in the DQ domain that will be used for the PWM

generation.ELECTRICAL QUANTITIES ON DQ

DOMAIN ARE CONSTANT VALUES

L

DC

QQDD

DC

QDSQS

Q

SQ

DQSDS

D

SD

R

usisi

dt

duC

ViLiRdt

diLe

ViLiRdt

diLe

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3 Phase PFC Control Scheme on DQ Domain

SPECIFICATION

Input voltage:

230V RMS 3-Phase voltage, 50Hz.

Output Voltage:

700V

Switching Frequency:

70kHz

Control Frequency:

20kHz

Source Inductance:

300uH

Output capacitance:

470uF

Ref. Fig 11.23 “Control in power electronics” Author. M.P. Kazmierkowski et al. 2002

DQ SYSTEM

MAKES PI

REGULATION

POSSIBLE!

CONTROL ALGORITHM

FIXED DURING TEST

CONDITIONS

3 MODULATION

STRATEGIES TESTED

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3 Phase PFC: Applied Modulation Strategies

2/2/201812

• A modification into the zero sequence voltage doesn’t affect the voltage applied to the inverter phases, however it

will affect noise between DC output and PE.

• An impact on the input filter should be expected, even if in this presentation EMI FILTER was not considered.

PWM Adaptive

Modulator

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Simulations

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3 Phase PFC Simulink Model, Behavioral

ADC & PWM

Peripherals

Control Strategy

(C-code)ANALOG INPUTS

PWM

OUTPUT

PARAMETERS

• FCLK = 84 Mhz

• FPWM = 70 Khz

• FCNTR = 20 Khz

• DEAD TIME = 1.1%

HARDWARE

• LS = 300 uH

• RS = 0,04 Ohm

• RHL = 72 Ohm

• RFL = 36 Ohm

70kh pwm freq

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3 Phase PFC SPICE Model, Quantitative

INPUTSSENSINGCONTROL STRATEGY POWER

STAGE

THE PARAMETERS SELECTED FOR RUNNING SPICE SIMULATION WERE ALIGNED WITH THE SIMULINK ONES.

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Understanding the Losses

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Choke Inductor Losses (simplified)

𝑃𝐿,𝐶𝑂𝑅𝐸 = 𝑘 ∙ 𝑓𝑎 ∙ 𝐵𝑃𝐾𝑐

• k, a and c are core material dependent.

• f is the high switching frequency

• BPK is half the flux density ripple calculated considering

the current ripple introduced by the inductance selected

𝐵𝑃𝐾 = 𝜇0𝜇𝑅𝑁∆𝐼

2.

𝑃𝐿,𝐽𝑂𝑈𝐿𝐸 = 𝑅𝑊·I 2RMS

• Where RW is the winding resistance.

• IRMS is the circulating current for a certain power level

with a known input voltage.

700V

EXN(t)

IX

XLX

VX0

VLX

0

N

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FETs Losses in Space Vector Modulation (1/2)

iA

iB

iC

dA

d'A

dB

d'B

dC

d'C

M1

M2

M3

M4

M5

M6

A

B

C

Notes

• During tDT both switches on each leg are fully OFF.

• FETs are bidirectional when turned ON and current flows according source and drain voltage potential.

• vA is depending on phase voltage and star voltage when low side FET OFF and current into the node.

tDT

dA

dB

dC

TPWM

M2 D1

D4

M1 M2D1

M3 D4

D6 M5 D6

iA

iB

iC

HARD

ON – OFF

HARD

OFF – ON

SOFT

ON - OFF

SOFT

OFF – ON

LEG A M2 - [1] M2 - [4] M1 - [3] M1 - [2]

LEG B M3 – [3] M3 – [2] M4 – [1] M4 – [4]

LEG C (as B) M5 – [3] M4 – [2] M6 – [1] M4 – [4]

1 2 3 4

1 2 3 4

1 2 3 4

SWITCHING LOSSESPL,SW → fPWM

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FETs Losses in Space Vector Modulation (2/2)

•Since all the FETs are equal we simplify the calculation with the following formula

𝑃𝐽 = 3 ∙ 𝑅𝐷𝑆,𝑂𝑁 𝑇 ∙ 𝐼𝑅𝑀𝑆2

𝑃𝑆𝑊 = 3 ∙ 𝐸𝑂𝐹𝐹 + 𝐸𝑂𝑁 ∙ 𝑓𝑃𝑊𝑀

NoteBy designing a different modulation strategy, the number of transitions could be decreased by 33% and together with an appropriate timing based on current amplitude, a switching loss minimization can be achieved

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3 Phase PFC Implementation

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3 Phase PFC – Power Board Concept (1/2)

Digital

Analog INP

Note

Note:

VBUS,MIN = 265·√6 = 650V

CURR SEN.

CURR. SEN.

CURR. SEN.

700V

vA

vB

vC

iA

iB

iC

24V

vBUS

24V

Inrush OFF

ISO-GATE DRIVER

15V

PWM

EN

FAULT

3V3

ISO-GATE DRIVER

15V

PWM

EN

FAULT

3V3

ISO-GATE DRIVER

15V

PWM

EN

FAULT

3V3

ISO-GATE DRIVER

15V

PWM

EN

FAULT

3V3

ISO-GATE DRIVER

15V

PWM

EN

FAULT

3V3

ISO-GATE DRIVER

15V

PWM

EN

FAULT

3V3

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3 Phase PFC – Power Board Concept (2/2)

Digital

Analog INP

Note

SIGNAL

CONDITIONING

FOR 3V3 uC

DCDC CONVERTER[390-850]/24V

390 V 24VDIGITAL

ISOLATORGATE

DRIVER

5V

REF.

IN+IN-XEN

ISODCDC

20V

ISO-GATE DRIVER

3V3

RSRC

RSINK

DESAT

15V

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3 Phase PFC Power Board

TOP VIEW BOTTOM VIEW

SIZE

375 x 240mm

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Results

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SiC Switching Behavior

INPUT VOLT: 230 Vrms

OUTPUT POWER: 10kW

EFFICIENCY: 97.6%

FPWM: 80kHz

DC OUT: 719.44V

DC RIPPLE: 29.4V

RG,ON: 22 Ohm

RG,OFF: 4.7 Ohm

L(Is = 0, F = 1kHz): 600 uH

TURN OFF ≈ 65 Vns-1 TURN ON ≈ 38 Vns-1

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Overview of the Experiment

INDUCTOR [μH]FA

CT

OR

S SWITCH. FREQUENCY [kHz]

MODULATION [type]

450

70

DIS1 FBM SVM

120

DIS1 FBM SVM

OUTPUT POWER [kW] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10]

70

DIS1 FBM SVM

120

DIS1 FBM SVM

[3..10] [3..10] [3..10] [3..10] [3..10] [3..10]

EFFICIENCY [η]

Ideally 100%

TOTAL HARMONIC DISTORTION [THD]

IEEE STD 519

7.0 3.5 2.5 1.0 0.5 8

POWER FACTOR [PF]

Ideally „1"

PHASE DELAY [φ]

Ideally „0°"

330M

ETR

ICS

Testing conditions

Input voltage:

230VRMS @ 50Hz

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Current Shape @ 10 kW 7

0 k

Hz

12

0 k

Hz

DISCONTINOUOS 1 FLAT BOTTOM SPACE VECTOR

THD1: 4.7%THD2: 5.8%THD3: 4.4%

THD1: 5.1%THD2: 6.5%THD3: 6.2%

THD1: 4.9%THD2: 5.6%THD3: 5.0%

THD1: 8.1%THD2: 8.3%THD3: 8.0%

THD1: 3.7%THD2: 4.2%THD3: 3.7%

THD1: 3.6%THD2: 3.5%THD3: 3.0%

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Efficiency Result

Note

Thermal steady state reached @ 10kW.

Power Supply: Chroma 61511, DC Load: ELR-91500-30, Power Analyzer:

Zimmer LMG500 Oscilloscope: Yokogawa DLM6054

.

• Factor with the highest impact is the output power at

which the board is working.

• Efficiency is affected by the modulation strategy

selected, a variation in average of 0.5% can be

considered which, in turn, affects switching losses.

• Modulation frequency and inductor selection have a

smaller influence on efficiency result. Most likely

they are compensating each other.

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Power Factor & THD

Public Information2/2/201830

Thank you