minimum active switch requirements for single- phase pfc ......converter input load ppb t fig. 1...

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Abstract—Active pulsating power buffering (PPB) function can effectively reduce the twice-line frequency energy storage

requirement in a single-phase rectifier. Existing circuit topologies with active PPB must utilize more than two active

switches in their circuits. Compared with conventional single-active-switch solutions without active PPB (e.g. a boost PFC

rectifier), the cost of additional semiconductor switches and gate drive circuitry in an active PPB-based rectifier may not

be justified for low power applications. This paper presents a family of single-switch single-phase rectifier with active PPB.

Taking advantage of the on-time and off-time of a single switch, the proposed rectifiers are formulated by merging two

converters which are respectively duty and frequency controlled. The steady-state characteristics of these converters are

analyzed. A step-by-step design procedure is provided, and an active control method for limiting the maximum switching

frequency for wide-load-range operation is presented. A 100-W prototype is built for demonstration of the proposed single-

switch rectifier concept. It is envisaged that this concept, when combined with other circuit formulation techniques, e.g.,

partial power processing, dc-voltage feedback, may lead to new derivation of single-switch rectifiers with more advanced

features.

Index Terms—Single-phase, electrolytic capacitor, pulsating power buffering, single-switch.

I. INTRODUCTION

Single-Phase PFC rectifiers with active pulsating power buffering (PPB) function have received much

attention in recent years due to their potential of achieving high power density, high conversion efficiency,

and high reliability (H3) [1]–[5]. The H3 features are expected to offer significant economic benefits as they

are particularly desirable for many emerging applications such as LED lighting which requires long operating

lifetime [6]–[9] and quick charging of mobile phones which requires a high-power-density design [10]–[12].

Conventional single-phase converters with a dc port and an ac port require substantial energy storage to

buffer the inherent twice-line frequency power flow at the ac port. As shown in Fig. 1, the basic principle of

active PPB is to (i) construct a third ripple port to which an energy storage Cb is connected and (ii) allow a

Minimum Active Switch Requirements for Single-Phase PFC Rectifiers Without Electrolytic Capacitors

Sinan Li, Member, IEEE, Wenlong Qi, Student Member, IEEE, Jiayang Wu, Student Member,

IEEE, Siew-Chong Tan, Senior Member, IEEE, S. Y. Ron Hui, Fellow, IEEE


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large voltage ripple Δvc across Cb. As the power absorbed by Cb is proportional to Δvc, a small Cb is sufficient

to buffer the twice-line power flow given a large Δvc. With active PPB, bulky and unreliable electrolytic

capacitors (E-caps) commonly employed in the dc-link of conventional single-phase rectifiers can be

eliminated and replaced by more compact and reliable non-E-caps, such as film or ceramic capacitors, thereby

achieving high compactness and long lifetime.

AC/DC

converter

Input Load

PPB

t

Fig. 1 Power conversion architecture of a single-phase PFC rectifier with active pulsating power buffering.

The accomplishment of active PPB function generally requires the addition of extra power electronics,

which seems to work against the principles of volume and cost reduction. For instance, active PPB can be

achieved by configuring a bidirectional dc active filter in parallel or series with the dc-link of a front-end

PFC rectifier. Consequently, two extra active switches and one extra inductor are needed in the case of a

buck-type dc active filter [13], [14]. In [15]–[22], a concept called switch integration is proposed. It is

demonstrated that an integrated solution without adding extra active switches can be obtained, by sharing the

use of one phase leg of a front-end full-bridge PFC rectifier with that of a half-bridge-type dc active filter. A

comprehensive review of this concept can be found in [23]–[26]. Following this concept, however, a

minimum of three active switches and two inductors are still needed. To further reduce the number of active

and passive components, an alternative concept of PPB embedded switching is recently explored [27]–[29].

Based on this concept, extra switching states, deliberately embedded into each switching cycle of the original

single-phase converter, are utilized to perform active PPB function. Therefore, the need for an extra dc active

filter is discarded. New single-phase topologies featuring only two active switches and a single inductor have


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been developed. A bridgeless version of this rectifier with an improved power conversion efficiency is also

proposed [30]. To date, among all the reported single-phase topologies with active PPB function, those

employing PPB embedded switching seem to have achieved the minimum number of active switches and

passive components used. Nevertheless, such solutions are still less competitive in terms of cost to

conventional single-switch single-phase rectifiers (e.g. a boost PFC). It is therefore natural to ask the question

of whether the number of active switches can be further reduced in an active PPB-based rectifier and how

such rectifiers can be realized.

This paper attempts to answer these questions from a control’s perspective under the framework of network

theory. It is shown that single-phase PFC rectifiers with active PPB function can theoretically be constructed

using a single active switch. A simple idea of how to formulate single-switch single-stage PFC rectifiers

without electrolytic capacitors is presented, and a family of such PFC rectifiers based on PWM integrated

converters is proposed and analyzed as examples. The feasibility of the converter is confirmed through a 100

W laboratory prototype, and the performance of the rectifier is examined in detail.

II. ACTIVE PPB-BASED SINGLE-PHASE CONVERTER AS A THREE-PORT NETWORK

A. Minimum Control Input Requirements

u1 y1

u2 y2

three-port network

ac port dc port

ripple port

three-port network

(a) (b)

Fig. 2 (a) Active PPB-based single-phase converter as a three-port network and (b) its mathematical model from the control’s

perspective.

An active PPB-based single-phase converter is essentially a three-port network, comprising an ac port, a


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dc port, and a ripple port (see Fig. 2(a)), interfacing with an ac source (load), a dc load (source), and a PPB

energy storage. The ac, dc, and ripple ports are expected to perform input current shaping control for attaining

a unity power factor (PF), output voltage/current control for dc voltage regulation, and active PPB control

for achieving a large voltage ripple Δvc, respectively. The control can be accomplished by (i) setting their

respective references, e.g., iac*, vdc

*, and vc*, and (ii) designing a proper controller to ensure perfect reference

tracking.

It is, however, impossible to set the three references independently. According to the principle of

conservation of energy, the instantaneous power flowing into the three ports must satisfy

0,ac dc rp p p+ + = (1)

where pac, pdc and pr represent the power flowing into the ac port, the dc port, and the ripple port, respectively.

Equation (1) indicates that the power at any port is indirectly determined (and controlled) by the power at the

other two ports and will not follow the reference set for that port. This suggests the power of only two out of

the three ports can be directly and independently controlled, leading to three possible control strategies,

namely [28], [31],

Strategy A: direct control of ac- and ripple-port power;

Strategy B: direct control of dc- and ripple-port power;

Strategy C: direct control of ac- and dc-port power.

Whichever one of the control strategies is utilized, there are always two control objectives (or control

outputs) to be regulated (i.e., iac and vc for Strategy A, vdc

and vc for Strategy B, and iac and vdc for Strategy C).

Therefore, a minimum of two control inputs is required such that the two control outputs are controllable.

Mathematically, controllability means that

( )( )

1 1 1 2

2 2 1 2

, ,

, ,

y f u u

y f u u

=

=

x

x (2)

has a solution of u = {u1 u2} given any set references for y = {y1, y2}, where y are the control outputs, u are


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the control inputs, x are the state variables, f1(⋅) and f2(⋅) are topology-depended functions. It should be

emphasized that the terms control inputs/outputs are control terminologies which should be distinguished

from the power inputs/outputs concept that is determined by the power flow direction.

The discussions above suggest that an active PPB-based single-phase converter is essentially a two-inputs-

two-outputs (TITO) system from the control’s perspective (see Fig. 2(b)). This is indeed the case for all the

active PPB-based single-phase converters reported thus far. For instance, in the configurations with a dc

active filter, there is one duty cycle command (as one control input) in the PFC stage, and a second duty cycle

(or phase-shift angle) command (as a second control input) in the dc active filter stage [32], [33]. In another

configurations reported in [34], there is one duty cycle command in the PFC stage and a frequency command

in the cascaded dc/dc stage . As a total of two control inputs are required and each is physically realized by

one or more active switching devices, it appears that a minimum of two active switches is needed to construct

an active PPB-based single-phase converter.

B. Single-Active-Switch Realization

A single switch has two switching states, i.e., ON and OFF state. A single switch can thus provide two

degrees of operation freedom (or two control inputs) by varying the on-time and off-time, respectively (see

Fig. 3). It is thus theoretically viable to construct an active PPB-based single-phase converter using a single

active switch with ton and toff as the two control inputs.

ton toff

(a) (b)

Fig. 3 (a) A single active switch with its (b) on-time and off-time as two independent control inputs.

A simple approach to achieving variable on-time and off-time control is to implement simultaneous duty

cycle and switching frequency control. A single-switch active PPB-based single-phase converter can thus be


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formulated by integrating two single-switch single-stage power converters having different types of control

inputs, leading to seven types of single-switch active PPB-based single-phase converters, as summarized in

Table I, where d represents duty cycle, and fs represents switching frequency.

Representative single-switch converters with d as control inputs are PWM based converters, such as boost,

buck, and buck-boost converter operated in the continuous conduction mode (CCM); single-switch

converters with fs as control inputs include a range of resonant converters such as class-E resonant converters;

and single-switch converters with both fs and d as control inputs include PWM based converters operated in

the discontinuous conduction mode (DCM) [35]. Isolated converters are also viable candidates when galvanic

isolation is needed. The integration of different power converters may be realized based on power converter

synthesis methods, e.g. tree theory [36]–[38], canonical switching cell theory [39]–[41] or layer and graft

schemes [42]–[45], which will not be detailed in this paper.

TABLE I

FAMILIES OF SINGLE-SWITCH ACTIVE PPB-BASED SINGLE-PHASE CONVERTERS

Control Type Converter I Converter II

I d fs II d fs and d III fs d IV fs fs and d V fs and d d VI fs and d fs VII fs and d fs and d

III. SINGLE-SWITCH ACTIVE PPB-BASED RECTIFIERS BASED ON PWM INTEGRATED CONVERTERS

A. Topologies

One integration approach is to cascade the two single-switch converters in series and then share the use of

the active switch and the dc-link capacitor, as shown in Fig. 4. If the two converters are PWM-based

converters, then there are three possible combinations according to Table I, with the operation mode

highlighted in Table II.


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Converter I Converter II


Fig. 4 A conceptual illustration of how to formulate a single-switch PPB-based rectifier based on integrating two cascaded

PWM converters.

TABLE II

POSSIBLE CONFIGURATIONS OF PWM INTEGRATED CONVERTERS

Operation mode Type


II CCM DCM V DCM CCM

VII DCM DCM

Fig. 5(a) depicts a PWM integrated converter derived by merging a boost converter (as Converter I) and a

buck converter (as Converter II), while Fig. 5(b) illustrates another PWM integrated converter with a boost

converter as Converter I and a forward converter as Converter II, thereby offering an extra benefit of galvanic

isolation. Each of the newly derived single-switch converters in Fig. 5 operates as if there were two cascaded

converters operated independently. Therefore, the operation of the single-switch converters can be analyzed

conveniently by analyzing each of the constitutional converters individually.

L1

D1Co

EMIFilter

Q

vovc

vac

RCb

D2

D3

L2

iac+

− +

−

(a)


8

L1

D1Co

EMIFilter

Q

vovc

vac

RCb

D2

D3

L2

iac+

− +

−

D4

(b)

Fig. 5 (a) An exemplary non-isolated topology by integrating a boost converter and a buck converter and (b) an isolated topology

by integrating a boost converter with a forward converter.

With reference to Fig. 5, the following three comments are made:

(i) The topologies derived in Fig. 5 do not indicate explicitly the operating mode of the constitutional

converters. This means the integrated converters may be operated in type II, type V, or type VII,

despite the same circuit topologies;

(ii) The topologies do not necessarily guarantee (2) is solvable. For example, regarding the topologies in

Fig. 5(a), the steady-state terminal equations at the ac port and the dc port can be obtained as (when

operated as a type VII converter)

( )

( )

2 2

1 1 1

1

2

2 2 12

2

2 1,

281 1

acac

ac s s

c

co

ss

v d di f f uv f f

Lv

v dv f f ufL f

R d

= = = −

= = = + +

(3)

where the symbols are defined in Fig. 5. Noticing both control outputs (i.e., iac and vo) are functions of a

single control input u1 = d2/fs only, no solutions of u1 exist that can satisfy both equations. Therefore,

the topology shown in Fig. 5(a) cannot be operated in Type VII.

(iii) The idea of integrating two single-stage power converters is not new and can be traced back to 1990s

when the converters were named Integrated High-Quality Rectifier Regulators (IHQRR) [46].

Intensive efforts of searching for IHQRR had resulted in a myriad of interesting topologies and


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hundreds of literature [47], [48], and the same topologies as those shown in Fig. 5 were actually

reported [49]. However, there are three key distinctions between an IHQRR and the proposed single-

switch active PPB-based single-phase rectifier:

(a) most IHQRR only employ d as their control inputs [46]. This means either the output voltage vo or the

input current iac (e.g., with control Strategy C) can be controlled. There is always a compromise between vo

and PF regulation. In contrast, the proposed converter operates with both d and fs as control inputs,

thereby enabling both tight vo regulation and a high PF;

(b) some IHQRR employ both d and fs as their control inputs [50]. However, a majority of these converters

employ d for vo regulation and fs for the regulation of the average PPB capacitor’s voltage (i.e., cV ).

Therefore, the input current is left uncontrolled, leading to a deteriorated PF. The same is the case for other

topologies proposed in [51], where fs is used for vo regulation and d for cV regulation. In the proposed

converters, however, d and fs are utilized to directly control vo and iac;

(c) In the proposed rectifiers, vc has a large voltage ripple Δvc with a reduced PPB capacitance. Most

IHQRR, in contrast, employ large PPB capacitors to ensure negligible twice-line frequency voltage ripples

Δvc. This is the case even for IHQRR reported in [49], where d and fs are employed for direct vo and iac

regulation. Therefore, the control methods in [49] which use large PPB capacitor for the assumption of

negligible Δvc are invalid for controlling the proposed rectifier (that allows a relatively large Δvc without

adversely affecting the PF and the dc output voltage vo).

B. Steady-State Analysis

D1

CoEMIFilter

Q

vo

vc

vac R

D2 D3

iac+

− +

− L1

Cb

L2

Fig. 6 The studied non-isolated topology based on integration of a buck-boost converter and a second buck-boost converter.


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The steady-state analysis of a single-switch active PPB-based single-phase rectifier is demonstrated on the

topology shown in Fig. 6 operated in Type V: a buck-boost converter (DCM) integrated with a second buck-

boost converter (CCM). The analysis of the rectifier is performed under the assumption that all switches are

ideal, that the output power Po is constant, and that the converter operates with a unify power factor, i.e.,

sin

,sin

ac ac

ac ac

v V ti I t

ωω

= =

(4)

where ω is the line frequency, Vac and Iac are the peak amplitude of the line voltage and current, respectively.

Based on (1), vc can be derived as

2

sin 2 ,oc c

b

Pv V tC

ωω

= − (5)

where cV is a design choice, and Po = VacIac/2.

With reference to Fig. 6, the steady-state terminal equations at the ac port and the dc port can be obtained

as

( )

( )

2

11

2

,2 .

1

acac s

s

o c

v di f d fL f

dv v f dd

= =

= = −

(6)

Solution of (6) leads to

( )

2 22

21 1

11

.1

4 4 1

c o

ac acs

o o c o

dv v

V Vf dP L P L v v

= + = = +

(7)

Equation (7) leads to three key conclusions:

(i) Solutions of {d, fs} exist for (6) given any reference signals for vo and iac, i.e., vo* and iac

*. This

means the converter satisfies the controllability requirement for being a PPB-based single-phase

rectifier;


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(ii) Instead of cV , a vc term is included in the expressions for d and fs, respectively. Therefore, tight vo

regulation and PF control can always be attained despite large variations of vc;

(iii) d is inversely proportional to the ratio vc/vo, while fs is inversely proportional to vc/vo and

proportional to Vac2/PoL1.

0

-100

-200

100

200

190

200

210

220

230

240

250

Vc_m

120.8

121

121.2

121.4

121.6

121.8

Vo_m

200

100

0

-200

-100

250240230220210200190

20.5

Time: [100 mvac

50x iac

vcΔvc= 40 V

vo Δvo= 1 V

190

200

210

220

230

240

250

0.33

0.34

0.35

0.36

0.37

0.38

d

57.5K

60K

62.5K

65K

67.5K

70K

72.5K

75K

fs

250240230220210200190

vc

0.380.370.360.350.34

0.33

d

75 k

2.5 k70 k

fs fs_max

d_max

d_min

vc_min

vc_maxTime: [100 m

(a) (b)

Fig. 7 (a) Simulated operating waveforms at the ac port, ripple port, and dc port and (b) the duty cycle and switching frequency

employed for the control.

Fig. 7 (a) illustrates the simulated operating waveforms of the converter with an open-loop control based

on (7). The details of the circuit parameters used in the simulation are presented in Table IV. It is observed

that unity PF is successfully achieved at the ac port, that vo is well regulated at 100 V with negligible low-

frequency voltage ripples (less than 1% of Vo), and that the ripple port has significant voltage variations of

more than 40 V for this 100 W system.

On the other hand, Fig. 7 (b) shows that both d and fs are varying at a twice-line frequency. In particular,

the peaks and valleys of both d and fs occur when vc reaches its valley vc_min and peak vc_max, respectively.

This is consistent with the conclusion (iii) mentioned above that d and fs are inversely proportional to vc.

Specifically,


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2

_ min

2

_ max

,.

,

oc c

b

oc c

b

Pv VC

Pv VC

ω

ω

= −

= +

(8)

Therefore,

2

_ max 221

2

_ min 221

14

1

,1

41

acs

o oc o

b

acs

o oc o

b

VfP L PV v

C

VfP L PV v

C

ω

ω

=

− + = + +

(9)

with a frequency excursion of Δfs = fs_max − fs_min.

Fig. 8 illustrates the relationships of fs versus Cb with fs_min and fs_max highlighted. It is observed that fs_min

and fs_max gradually converge to a single operating frequency point fs_nom as Cb increases. This is exactly the

operation of an IHQRR (with a large Cb), where both d and fs are constant during the steady state. fs_nom can

be determined from (9) as

( )

2

_ 21

1 .4 1

acs nom

o c o

VfP L V v

=+

(10)

As Cb decreases, fs_min and fs_max begin to diverge from fs_nom, and the frequency excursion Δfs gradually

increases. Fig. 8 implies that IHQRR is essentially a special case of the proposed single-switch rectifier based

on PWM integrated converters when Cb is large.

Fig. 9 further illustrates the relationship between fs and c oV v , with Po and Cb fixed. The curve follows a

similar trend to that between fs and c ov v , and suggest that a high c oV v ratio is desired when a low fs is needed.

Fig. 9 also shows that a higher c oV v ratio leads to a smaller Δfs. The observations derived from Fig. 8 and

Fig. 9 are useful for system optimization regarding power conversion efficiency and power density, as fs

directly relates to power losses and the volumes of the passive components.


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Fig. 8 Switching frequency versus Cb (Po = 100 W, c oV v =1.83 and L1=115 μH).

1000

800

600

400

200

1.30

1.4 1.5 1.6 1.7 1.8 1.9 2.0

fs_max-Type II

fs_min-Type II

fs_max-Type V

fs_min-Type V

Type II

Type V

c oV v

Fig. 9 Switching frequency versus c oV v when operated as a Type II and a Type V converter (Po = 100 W, Cb = 30 μF, and L1=

L2=115 μH).

C. Alternative Modes of Operation

Section B discusses the converter’s operation as a Type V converter. However, the converter exhibits

entirely different dc characteristics when operated in Type II. With reference to Fig. 6, the terminal equations

now become:

100 200 300 40050

55

60

65

70

75

fs_nom

500

fs_max

fs_min

Switc

hing

freq

uenc

y f s

(kHz

)

PPB capacitance Cb (μF)


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( )

( )

1

22

2

1.,

2

c ac

co s

s

dv v f dd

vv f d fL fR d

= = − = =

(11)

Solution of (10) leads to

( )2 2 2

22 2

11

.

2 2 1

ac c

c cs

o o ac c

dv v

v d vfL P L P v v

= + = = +

(12)

Three key observations can be made from (11):

(i) d always reaches a maximum of dmax = 100% and fs always reaches a maximum of fs_max=2

22c oV L P ,

whenever 0acv = . These features are different from those in a Type V converter, as dmax is now

operating-point (e.g. Vac, Po, vo) and component-value (i.e., L1, L2, Cb) independent, while fmax only

depends on cV , Po, and L2 but is independent of vo and Cb;

(ii) Compared to (7), d and fs in (11) include a time-varying term acv having a large voltage variation

from 0 to Vac. As a result, the excursions of d and fs in a Type II converter are generally much larger

than that in a Type V converter (see Fig. 9). A larger Δfs is not desirable as it complicates the

magnetics design and compromises the volume of a passive component;

(iii) Fig. 9 also shows that fs_max in a Type II converter is generally much higher than that in a Type V

converter with the same Po, cV , Cb and DCM inductor design. This is because fs in both (7) and (11)

are proportional to d2. A type II converter, however, always has a dmax of 100%, while a type V

converter has a dmax which can be designed small by increasing the ratio of c oV v .

For general applications, a Type II converter may not be a good and practical choice due to its very high

fs_max and wide Δfs, especially for low-power applications.


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D. Buck Family, Boost Family, and Buck-Boost Family

By following a similar analysis, it is possible to calculate and characterize d and fs for all possible circuit

topologies with different converter configurations and operation modes. There is a total of nine feasible

configurations when buck, boost, and buck-boost converters are selected as converter I and II in Fig. 4 (see

Table III).

TABLE III

TOPOLOGIES OF PWM INTEGRATED CONVERTERS


buck buck boost

buck-boost

boost buck boost

buck-boost

buck-boost buck boost

buck-boost

If operated in Type V, the nine configurations can be further classified into three families: buck family,

boost family and buck-boost family. The family name is determined by the type of the converter used for

Converter I, and the converters within a family possess similar operating characteristics. The terminal

equation for the buck, boost and buck-boost family at the ac port is, respectively:

2

1

2

1

2

1

, buck family2

, boost family,2 1

, buck-boost family2

ac c

s

acac

ac s

c

ac

s

v v dL fv di

v fL

v

v dL f

−= −

(13)

and at the dc port is,

( )o cv M d v= , (14)


16

where M is the voltage conversion gain of Converter II and is a function of d. Namely, M (d) = d, 1/1−d, and

d/1−d, respectively, when Converter II is a buck, boost, and buck-boost converter. By solving (12) and (13),

both d and fs can be explicitly resolved.

Equation (13) shows that d is uniquely determined by the topology used for Converter II and can be

expressed as d = d (vc, vo). A smaller Cb leads to a larger variation of d per line period due to the increased

Δvc, and vice versa. On the other hand, (12) shows that fs equals

2

1 1

22

1

22

1

,buck family4 4 sin

, boost family.sin4 1

, buck-boost family4

ac c ac

o o

acs

aco

c

ac

o

V v V dL P L P t

Vf dV tL P

v

V dL P

ω

ω

2

− = −

(15)

Equation (14) mathematically characterizes fs of a buck, boost and buck-boost family converter, which can

be summarized as follows:

(i) fs in the buck-family converters always drop to a minimum of fs_min = 0 Hz per line period whenever

ac cv v= , or when ωt = sin−1 (vo/Vac). When ac cv v< (e.g., near the zero-crossing point of the line

voltage), the front-end bridge rectifier before Converter I stops conducting and the line current

becomes zero, leading to a deteriorated PF;

(ii) both the buck- and the boost-family converters have wide frequency excursion range due to the time-

varying sinusoidal term sin ωt, even if large Cb is employed. In contrast, Δfs in a buck-boost family

converter is relatively smaller. When a large Cb is utilized, Δvc → 0, and Δfs → 0;

(iii) fs of all the buck, the boost, and the buck-boost family converters are (quadratically) proportional to

Vac and d, and inverse proportional to L1 and Po. The characteristics suggest that the worst operating

scenarios (when fs_max is the highest) occur at the conditions of minimum load and highest line


17

voltage.

Based on the above discussions, the buck-boost family converters are the best among the three families

when a smaller Δfs is desired.

IV. DESIGN CONSIDERATIONS

A. Switching Devices and PPB Capacitor Selection

Take the converter in Fig. 6 as an example. The voltage stresses of the main switch Q and diode D1 equal:

( )_ 1_ 0 2max .Q stress D stress ac ct

V V v vω π≤ ≤

= = + (16)

The voltage stress of diode D2 equals:

2 _ .D stress ac oV V v= − (17)

The voltage stress of D3 equals:

3_ _ max .D stress c oV v v= + (18)

As a vc term is included in (15) and (17), the voltage stresses of Q, D1 and D3 are then dependent on Po, Cb

and cV .

A higher Po and cV and/or a smaller Cb will lead to higher voltage stresses in these switching devices.

Therefore, Q, D1, and D3 must be selected at full power. The voltage stress in these devices can only be

reduced by reducing cV and/or increasing Cb, based on curves illustrated in Fig. 10. If the maximum voltage

stress of Q is designed at 380 V, then a minimum Cb of 30 μF should be selected.


18

Fig. 10 Voltage stresses of the main switch Q and the diodes D1–D3 versus Cb (Po = 100 W, c oV v =1.83, and L1=115 μH).

On the other hand, (16) shows that the voltage stress of D2 is independent of the power level and the PPB

capacitance but depends only on vac and vo. Therefore, D2 should be selected at maximum input and output

voltage levels.

B. Inductors Selection

It is important to design L1 and L2 such that (i) the operating modes (CCM or DCM) are ensured, (ii) the

inductor current ripple is smaller than a rated value ΔiL_rated (for CCM of operation), and (iii) the switching

frequency lies within a predetermined frequency range.

To ensure a DCM operation in Converter I, L1 in Fig. 6 must satisfy

1 11 ,2 L Li i∆ ≥ (19)

where

12 sin ,ac o

Lac

i P tid V d

ω= = (20)

and

11

.acL

s

v diL f

∆ = (21)

Combination of (18)‒(20) leads to

100 200 300 400 500

100

200

300

400

Volta

ge s

tress

(V)

Q, D1

D2

D3

380

36

359

30 μFPPB capacitance Cb (μF)


19

( )

2 2

1 1max .4

aci

o s

V dL LP f

≤ = (22)

Based on the control law of (7), it is shown that (21) is always satisfied, meaning that a DCM operation in

Converter I is always ensured automatically. On the other hand, given a pre-determined maximum and

minimum switching frequency of fs_max and fs_min, respectively, L1 must satisfy L1 ∈ (L1min, L1max(ii)), where

( )

2

1min 22_ max

2

21max2_ min

14

1

.1

41

ac

o s oc o

b

acii

o s oc o

b

VLP f PV v

C

VLP f PV v

C

ω

ω

=

− + = + +

(23)

Assuming fs_min = 50 kHz and fs_max = 80 kHz at Po=100 W, L1min and L1max(ii) are calculated as 107 μH and

135 μH, respectively. In the final design, L1 = 115 μH is selected.

Similarly, to ensure a CCM operation in Converter II, L2 in Fig. 6 must satisfy

2 21 ,2 L Li i∆ ≤ (24)

with iL2 and ΔiL2 defined as

2 ,1

oL

iid

=−

(25)

and

22

.cL

s

v diL f

∆ = (26)

Solution of (23)‒(25) leads to

( )( )

2 2min

11 .2

ci

o s

d dvL Li f

−≥ = (27)

On the other hand, L2 must be designed such that the current ripple requirement is satisfied:

2 2 _ .L L ratedi i∆ ≤ ∆ (28)


20

Equation (27) indicates that

( )2

2 2min_

cii

L rated s

v dL Li f

≥ =∆

(29)

The minimum inductance of L2 is therefore given by

( ) ( )( )2min 2min 2minmax ,i iiL L L= (30)

In this design example, L2min(i) and L2min(ii) are calculated as 544 μH and 2 mH, respectively, assuming

ΔiL_rated = 80% Io. L2 of 2 mH is then selected.

C. Limiting the Maximum Switching Frequency

One major disadvantage of a single-switch active PPB-based rectifier based on PWM integrated converters

is that its operating frequency fs can become very high at light load. As illustrated in Fig. 11, if constant cV

is assumed, an approximately twofold variation in fs_max and fs_min, respectively, is needed, when the rectifier

in Fig. 6 operates between full load (i.e., Po = 100 W) and half load (Po = 50 W).

Fig. 11 Switching frequency characteristics for wide load range operation with constant cV control ( cV = 220 V, Cb = 30 μF).

fs can be reduced at light load by increasing L1. However, the requirement of L2 is inversely proportional

to fs according to (29). Reducing fs implies a larger L2 is needed to maintain a CCM operation. The use of a

large L1 and L2 lowers the power density of the overall system and is not desirable.

A second method to limit the maximum switching frequency for a wide-load-range operation is to actively

Switc

hing

freq

uenc

y f s

(kHz

) 140

120

100

80

60

50 60 70 90 10080Output power Po (W)

fs_max

fs_min


21

control cV to compensate for the variation of Po. This method is explained as follows:

Assume that Po = α⋅Po_full, where Po_full is the full load power, and α (0≤ α ≤ 100%) is the percentage of the

actual power relative to Po_full. If the maximum switching frequency at Po_full is to be maintained throughout

the load range, then, according to (9),

2 22 2_ _

_

1 1

o full o fullc c full

b b

o o

P PV V

C Cv v

αω ω

α

− −

+ = +

(31)

needs to be satisfied, where _c fullV is the average voltage of vc at Po_full. Solution of (30) gives

22

_ _ _1 1c full o full o fullc o

b b

V P PV v

C Cα

α αω ωα

= − + − +

(32)

Fig. 12 Calculated average capacitor voltage cV for retaining a constant fs_max at different power level (Po_full = 100 W, Cb = 30

μF).

Fig. 12 illustrates calculated cV versus α for achieving a constant fs_max at different _c fullV levels. Generally,

an increase of cV is needed at light load (i.e., around 50% increase at 50% load), which inevitably increases

the voltage stress of Q, D1, and D3, according to (15)–(17). However, the increase of cV at a lower _c fullV level

Output power ratio α (%) 50 60 70 90 10080

400

350

300

250

200

(V)

Aver

age

capa

cito

r vot

lage

cV

_ 180c fullV V=

_ 220c fullV V=

_ 180c fullV V=_ 260c fullV V=


22

is slower. For _c fullV = 180 V, 220 V and 260 V, the increase of cV at 50% load is 95 V, 118 V, and 138 V,

respectively. Therefore, a low _c fullV level is preferred when constant fs_max control and low voltage stresses

are mandated.

V. EXPERIMENTAL VERIFICATIONS

A 100-W hardware prototype (120 V/0.83 A) was built for demonstration purpose based on a Type V

rectifier with a circuit schematic illustrated in Fig. 6. The detailed converter specifications are shown in Table

IV. If a much lower output voltage is desired (e.g. vo = 12 V), an isolated version of the converter, e.g., a

buck-boost converter integrated with a flyback converter may be employed [52]. The controller is

implemented using a low-cost DSP (Model No.: F28069) based on a feedforward control. All waveforms are

captured using digital oscilloscope DSOX3024A and all data are obtained using Precision Power Analyzer

PPA5520.

TABLE IV

SPECIFICATIONS OF THE SIMULATED/EXPERIMENTAL 100-W RECTIFIER

Parameter Value Parameter Parameter

Line voltage vac 110 V (RMS)

/60 Hz L1 115 μH

Full power Po_full 100 W L2 2 mH Output voltage vo 120 V Cb 30 μF Average capacitor

voltage cV 220 V Co 5 μF

ΔiL_rated 80% D1-D3 IDH04G65C6XKSA1 fs_min 50 kHz Q TPH3208LDG fs_max 80 kHz Bridge rectifier STTH5L06

Cut-off frequency of EMI filter 1.2 kHz Gate driver SI8230BB


23

vac: [100 V/div]iac: [2 A/div]

vc: [100 V/div]

vo: [100 V/div]

Time: [5 ms/div]

Fig. 13 Measured steady-state operating waveforms at full load.

iL1: [5A /div]

iL2: [0.5 A/div]

vds: [200 V/div]

vgs: [10 V/div]

Time: [1 ms/div]

iL1: [5A /div]

iL2: [0.5 A/div]

vds: [200 V/div]

vgs: [10 V/div]

Time: [5 μs/div]

Fig. 14 Measured inductor currents, gate driving signal and drain-to-source voltage waveforms at full load.

The waveforms of the line voltage/current, output voltage, and PPB capacitor’s voltage are captured at full

load (see Fig. 13). Line current follows the line voltage sinusoidally with negligible distortions. The measured

THD is 3.46% and the PF is 0.995. At the same time, the output voltage is precisely controlled at 120 V with

small low-frequency voltage ripples (Δvo = 4.16% Vo), while the PPB capacitor has large voltage fluctuations

(Δvc = 20% cV ). These observations indicate that the output power is almost constant and the instantaneous

twice-line frequency pulsating power is dynamically buffered by Cb. The waveforms confirm that active PFC,

output voltage regulation and active PPB can be simultaneously achieved using a single active switch.

Fig. 14 illustrates the waveforms of both inductor currents iL1 and iL2, together with the gate signals and

drain-to-source voltages of the main switch Q. The zoomed-in waveforms at the peak line voltage are also

shown. Based on these waveforms, it is confirmed that Converter I is operated in the DCM and Converter II


24

is operated in the CCM.

Fig. 15 Measured fs_max with and without constant fs_max control.

Fig. 15 recorded the measured maximum switching frequency when the rectifier is operated between 50%

load and full load, with and without constant fs_max control. In particular, fs_max is obtained using oscilloscope

by zooming in the switching waveforms around vc_max. Overall, a good match between Fig. 11 and Fig. 15

has been observed.

The rectifier’s performance with and without constant fs_max control is further evaluated regarding the

voltage stress of the main switch, the power conversion efficiency, the PF, and total harmonic distortion

(THD), and the results are illustrated in Fig. 16 (a)–(d), respectively. Fig. 16 (a) shows that the voltage stress

of the main switch increases as the load decreases with constant fs_max control due to the increase of cV , while

it slightly decreases with constant cV control due to a decreased Δvc at light load. Fig. 16 (b) shows that

constant fs_max control slightly improves the power conversion efficiency throughout the load range examined

due to the reduction of the maximum switching frequency. The improvement is, however, not very significant

as constant fs_max control produces more output-capacitance-related switching loss in the main switch due to

the increased vc. Fig. 16 (c) and (d) further show that the PF and THD performance are almost identical with

and without constant fs_max control. Overall, high PF and low THD have been obtained with both control

methods across a wide load range.

020406080

100120140160

50 60 70 80 90 100

Max

Sw

itchi

ng F

requ

ency

(k

Hz)

Output Power (W)

Constant Vc controlConstant fsmax control


25

(a) (b)

(c) (d)

Fig. 16 (a) Measured voltage stress of the main switch, (b) power conversion efficiency, (c) power factor, and (d) total harmonic

distortion with and without constant fs_max control.

VI. CONCLUSION

This paper presents a family of single-switch single-phase rectifiers, featuring low-harmonic line currents,

stable dc output voltage, and no electrolytic capacitors. These converters are derived by integrating two

cascaded PWM converters (non-isolated or isolated) operated in DCM and CCM (or CCM and DCM),

respectively. Different from Integrated High-Quality Rectifier Regulators, which have identical circuit

topologies, the proposed converters take advantage of both duty cycle and switching frequency as control

inputs, thereby enabling simultaneous active power factor correction, active pulsating power buffering, and

output voltage regulation.

Steady-state operation of the proposed family of rectifiers has been analyzed based on the operating modes

0

100

200

300

400

500

600

50 60 70 80 90 100

Volta

ge S

tres

s of

Q(V

)

Output Power (W)


86.5

87

87.5

88

88.5

89

89.5

90

50 60 70 80 90 100Pow

er C

onve

rsio

n Ef

ficie

ncy

(%)

Output Power (W)


0.980.9820.9840.9860.9880.99

0.9920.9940.996

50 60 70 80 90 100

Pow

er F

acto

r

Output Power (W)


00.5

11.5

22.5

33.5

44.5

5

50 60 70 80 90 100Tota

l Har

mon

ic D

isto

rtio

n (%

)

Output Power (W)



26

(i.e., Type II, V, VII) and families (i.e., buck, boost and buck-boost family). It is shown that Type V

converters generally lead to a lower fs_max and a narrower frequency excursion Δfs, and are thus more desirable

for practical implementation. Additionally, the buck-boost family seems the best choice among the three

families when a smaller Δfs is needed.

A step-by-step design procedure example is also presented using a buck-boost converter integrated with a

second buck-boost converter operated in Type V. An active control approach to limit the maximum switching

frequency over a wide load range is also proposed. The feasibility of the converter is demonstrated on a 100-

W hardware protype, and its performance with and without the proposed control are thoroughly examined.

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minimum active switch requirements for single- phase pfc ......converter input load ppb t fig. 1...

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