3d integration for integrated circuits and advanced focal planes
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MIT Lincoln LaboratoryFermilab -1
CLK 2/28/2007
3D Integration for Integrated Circuits andAdvanced Focal Planes
Fermilab Colloquium
February 28, 2007
Craig Keast, Brian Aull, Jim Burns, Nisha Checka, Chang-Lee Chen, Chenson Chen, Mike Fritze, Jakub Kedzierski, Jeff Knecht, Brian Tyrrell, Keith Warner, Bruce Wheeler,
Dave Shaver, Vyshi Suntharlingam, Donna Yost
keast@LL.mit.eduMIT Lincoln Laboratory
*This work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA8721-05-C0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government .
MIT Lincoln LaboratoryFermilab -2
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Outline
• A brief history of CMOS scaling
• Drivers behind “Moore’s Law” and their future outlook
• The potential of “Next Generation” technologies beyond silicon CMOS
• 3D circuit integration technology and applications
• Summary
MIT Lincoln LaboratoryFermilab -3
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A Few Metrics
• Vacuum tube (early 1900’s) – transistor (1949) – integrated circuit- IC, “chip” (1959)
– During the first 10 years of the chip’s development the US government bought the majority of all ICs produced
– Today the US Government purchases are a few percent of the market
• Today’s microprocessors contain >500 million transistors and occupy ~2-3 cm2 area
– Equivalent number of vacuum tubes would cover an area equal to ~250 football fields
• First ICs cost ~$120 and contained 10 transistors ($12/transistor), today’s microprocessors cost ~$500 and contain 500,000,000 transistors ($0.000001/transistor)
– If this cost scaling was applied to the automobile industry a $100,000 Porsche 911(turbo) would now cost < 1 cent
MIT Lincoln LaboratoryFermilab -4
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Silicon – The Material Enabling the IC(Semiconductor Wafer Preparation)
Silicon makes up 25.7% of the earth’s crust
Sand
300 mm
Single-Crystal Ingot
Wafer Saw
Silicon’s Oxide (SiO2 ) is a KEY attribute of this material’s success
MIT Lincoln LaboratoryFermilab -5
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35 Years of CMOS Scalingand Process Improvements
Self-Aligned SilicidesSelf-Aligned Silicides
Presumed Limitto Scaling
Presumed Limitto Scaling
10 m
1 m
100 nm
10 nm
1 nm
1970 1980 1990 2000 2010 2020
Bulk Silicon
SOI ????
CMPCMP
Tec
hn
olo
gy
No
de
Year
CMOS Replaces BipolarFor High Performance Computing
CMOS Replaces BipolarFor High Performance Computing
CMOS Starts to ReplaceIII-V for Some RF Applications
CMOS Starts to ReplaceIII-V for Some RF Applications
Frontend
Backend
IC cross section
Tungsten PlugsTungsten Plugs
Halo ImplantsHalo Implants
Copper InterconnectCopper Interconnect
Low-k DielectricLow-k Dielectric
Strained SiliconStrained Silicon
High-k Dielectric???High-k Dielectric???
Self-Aligned GatesSelf-Aligned Gates
MIT Lincoln LaboratoryFermilab -6
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Drivers Behind Moore’s Law
• Smaller feature sizes– Pack more features in given silicon area
Lower cost per function
– Smaller transistors are faster– Smaller transistors and wires consume less energy
• Bigger chips– More functions on one chip reduces packaging and
integration costs, reduces power, improves reliability
• Bigger wafer sizes– More chips per wafer; wafer processing cost for bigger
wafers rises more slowly than number of transistors/wafer
• Manufacturing know-how– Faster machines, higher yields, better tool utilization
• More clever device, circuit, and process design– Pack more in a given area, even for a given feature size– “Equivalent scaling”: next generation performance through
improved process/materials: SiGe, SOI, strained silicon
MIT Lincoln LaboratoryFermilab -7
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Shrinking Feature Size….
Human Hair
~75 m
0.18 m180 nmfeature
.
.
~40,000 (65-nm node) transistors could fit on cross-section
MIT Lincoln LaboratoryFermilab -8
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• Current State of the art (>$25 M)– 65 nm resolution = 193 nm– 0.93 NA (n sin)– > 1013 pixels/wafer– ~120 300-mm wafers/hour– Wafer & mask move 100’s of mm/s
during exposure
4x reduction
W k1
n
sinW k1
n
sin
Lithographic Tools
~10’
MIT Lincoln LaboratoryFermilab -9
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Optical Lithographic Resolution
• Rayleigh criterion for resolution W
• 30x improvement in resolution over 25 years from 436 nm to 193 nm– sin from 0.35 to 0.93
– k1 from 0.6 to 0.35
– n from 1 to 1
• Now approaching limits limited by materials
and sources– sin < 1
– k1 > 0.25
– n ???
W k1
/ n
sin
Slide Courtesy M. Switkes, MIT-LL
MIT Lincoln LaboratoryFermilab -10
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Liquid Immersion Interference 27-nm Half Pitch
• High-index fluids have been designed and synthesized (n157 = 1.50)• Enable coupling of light from prism to wafer
• No need for solid contact – liquid gap of 2 m is used
Si mirror
CaF2
Substrate
Spacer Prism
157 nm light
Immersion fluid
sin = 0.87
Slide Courtesy M. Rothschild, MIT-LL
MIT Lincoln LaboratoryFermilab -11
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Optical Lithographyat the Nanometer Level
10 nm gold particle attached to Z-DNA antibody. (John Jackson & Inman. Gene [1989] 84, 221-226)
9-nm polysilicon gate on ultra-thin SOI fabricated at MIT-LL using 248-nm PSM optical lithography (2001)
10 nm
100 nm
9 nm9 nm
100 nm
MIT Lincoln LaboratoryFermilab -12
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It is likely that we can pattern the smaller feature sizes needed to maintain CMOS scaling….
But will the devices work?
MIT Lincoln LaboratoryFermilab -13
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Prognosis For Moore’s Law Benefits
Higher Speed? Lower Cost?
Lower Power?
• Historically, CMOS scaling has resulted in simultaneous improvements in cost per function, circuit (and system) speed, power consumption, and packing density
• Will continued scaling give us the same benefits?
MIT Lincoln LaboratoryFermilab -14
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Lower CostPrognosis For Moore’s Law Benefits
Past• Scaling (s) increases components
per unit area as s2
• Wafer size increase gives more chips per wafer
Increasing cost of equipment outweighed by huge increase in number of transistors made per wafer
Future Issues• Skyrocketing equipment costs…Today’s state-of-the-art production facilities
cost ~4 billion dollars
• NRE (e.g. >$1M mask sets) and productivity issues favor large volume production of “generic” components
• Increasing consolidation/pooling of fabrication resources and use of Taiwanese “Super Fabs” TSMC and UMC (China and India next?)
0
200
400
600
800
1000
1200
1400
1600
250 180 130 90
Technology Node (nm)
Ma
sk
Se
t C
os
t (x
$1
00
0)
Mask Set Cost
MIT Lincoln LaboratoryFermilab -15
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Lower PowerPrognosis For Moore’s Law Benefits
Past• Supply voltage (V) scales as 1/s
• Capacitance (C) scales as 1/s
• Energy per op scales as CV2 1/ s3 Voltage scaling from 5V to 1V
accounted for 25X reduction in power, just by itself
Future Issues• Power supply voltage only projected to
drop 2X over next 15 years (1.0 to 0.5 V)
• Subthreshold device operation?
Scaling energy per op is critical to long endurance battery powered systems and to supercomputers (getting power in and heat out)
Passive and Active Power vs Gate Length
E. J. Nowak, IBM J. Res. & Dev., Vol. 46, No. 2/3, p. 173
Stove top
(~1985)
MIT Lincoln LaboratoryFermilab -16
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Higher SpeedMoore’s Law in Trouble
Processor Speed (INTEL)*
4 GHz
*D. A. Muller, Nature Materials V 4, pg. 645 (2005)
• CPU speed has stalled for the first time in 35 years, with no processor able to break through the “4-Ghz barrier”
• Why?...Gate oxide scaling has stopped at Tox~1.2nm in 2003, at the 90-nm technology node (~3-4 monolayers)
– Only heroic integration efforts, such as use of strained-Si, have made small dents in the CPU speed barrier
– Need a workable High-k gate dielectric in order for performance scaling to continue
Gate Oxide Dielectric*
ResearchProduction
Gate
Channel
MIT Lincoln LaboratoryFermilab -17
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Future High PerformanceDevice “frontend” Possibilities
• Continue with Si CMOS. Some possible alternative silicon futures are:
– CPU speed could be maxed out – future improvements will come from reduced cost and higher density and integration “multi-core” chips
– High-k could save the day – if not tomorrow, maybe in 10 years
A perfect high-k gate dielectric will enable CPU speeds to increase until the next tunneling limit (source-to-drain) at the 10nm-node
– Changes in device architecture could take the pressure off the gate oxide, and CPU speed will continue to advance at a slower rate
FDSOI and FinFET lets Tsi scale instead of Tox
Intel - components research (IEDM2003)
With high-k
No high-k
MIT Lincoln LaboratoryFermilab -18
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Future Possibilities (Cont’d)
• A future with transistors, but without silicon:
– Germanium-based devices Improved mobility, at the expense of many other semiconductor
properties
– Carbon-based devices. Several flavors:
Carbon nanotubes: Have better device properties than Si, but are very difficult to integrate (thus far)
Graphite devices: Difficult to turn off
Molecular devices: Have not been demonstrated to work better than Si
MIT Lincoln LaboratoryFermilab -19
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Future Possibilities (Cont’d)
• A future without transistors:
– Josephson-junction-based logic Demonstrated and works, but at 4K Real speed and power advantages unclear
– Quantum Computation Can’t execute traditional code, even theoretically But can solve Schrödinger's equation blazingly fast, and factor
very large numbers
– Cross Point Arrays – nanowire, molecular Too simple for general purpose logic, if complexity is increased to
meet logic constraints the result is a transistor
– MEMS, protein, spin logic – too early to evaluate
MIT Lincoln LaboratoryFermilab -20
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Potential Technology Roadmap
Possible global directions for high performance logic technology in the next 20 years considered in this study,
and graphical summary of their evaluations when possible
Silicon devices
Perfect high-k
Res
earc
h
Req
uir
ed
Estimated Performance
Alternate SiStructuresFDSOIFinFET
Carbon-nanotubedevices
Graphite devices
Germanium devices
Molecular devices
Spintronics – no evaluation possible, insufficient experimental data
MIT Lincoln LaboratoryFermilab -21
CLK 2/28/2007 REF: A. Javey, et al. Nano Lett, 2004.
Future Technology Highlights:Carbon Nanotubes (CNTs)
• Example of experimental CNT device from Stanford Features: metal gate, high-k dielectric, metal source/drain High performance: 10x Si device of same geometry
• Putting tubes were they are needed is a problem
S
D S
SWNT 100 nm
10-9
10-8
10-7
10-6
10-5
-ID
S (
A)
-1.5 -1.0 -0.5 0.0 0.5VG (V)
VDS = -0.1,-0.2,-0.3 VL ~ 50 nm
L~30 nmVDS=-0.3 V10
-8
10-6
-I DS (
A)
-1 0VG (V)
(Drawing and AFM from CEA website)
1 nm
MIT Lincoln LaboratoryFermilab -22
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Future Technology HighlightsThin Graphite - Graphene
• Graphite has high mobility of >10,000 cm2/Vs (~15x Si)• Graphite is a semi-metal (semiconductor with band-gap of 0eV)
– Difficult to turn off, a fundamental challenge
• Proven planar techniques could be used in fabrication– Planar geometry of devices eliminates majority of integration difficulties
of carbon nanotubes
• MIT-LL has begun to explore this material system– Leveraging layer transfer, materials, and microelectronic fabrication
expertise at the Laboratory
REF: K.S Novoselov et al., Science, V. 306, 22 October 2004, p. 666
Few monolayer graphite device SEM and electrical characteristics at T=70K
MIT Lincoln LaboratoryFermilab -23
CLK 2/28/2007 *From 2005 International Technology Roadmap for Semiconductors (ITRS)
LocalInterconnect
GlobalInterconnect
(up to 5)
IntermediateInterconnect
(up to 8)
Cu Metal
Low-Dielectric
Typical Process Cross-Section*
250 180 130 90 65 45 32
Process Technology Node (nm)(year)
Re
lati
ve
De
lay
100
10
1
0.1
Gate Delay(Fan Out 4)
LocalInterconnectGlobalInterconnect(w Repeaters)
GlobalInterconnect(w/o Repeaters)
(2004) (2007) (2010) (2013)(2002)(2000)(1998)250 180 130 90 65 45 32
Process Technology Node (nm)(year)
Re
lati
ve
De
lay
100
10
1
0.1
Gate Delay(Fan Out 4)
LocalInterconnectGlobalInterconnect(w Repeaters)
GlobalInterconnect(w/o Repeaters)
(2004) (2007) (2010) (2013)(2002)(2000)(1998)
ActiveDevice
Relative Wiring Delay vs Feature Size*
The Integrated Circuit Interconnect “backend” Challenge
MIT Lincoln LaboratoryFermilab -24
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Wire Length Distribution in 90 nm Node IBM Microprocessor*
Area = A
Very Long Wires
Shorter Wires
2D
3D
A/2
A/2
0 t
o 7
20
72
0 t
o 1
44
0
11
40
to
21
60
21
60
to
28
80
28
80
to
36
00
36
00
to
43
20
43
20
to
50
40
50
40
to
57
60
57
60
to
64
80
64
80
to
72
00
72
00
to
79
20
79
20
to
86
40
86
40
to
93
60
93
60
to
10
08
0
10
08
0 t
o 1
08
00
10
80
0 t
o 1
15
20
11
52
0 t
o 1
22
40
12
24
0 t
o 1
29
60
12
96
0 t
o 1
36
80
13
68
0 t
o 1
44
00
14
40
0 t
o 1
51
20
15
12
0 t
o 1
58
40
15
84
0 t
o 1
65
60
16
56
0 t
o 1
72
80
17
28
0 t
o 1
80
00
Wire Length (m)
Nu
mb
er
of
Wir
es
1
10
100
1000
10000
1000000
to
72
0
72
0 t
o 1
44
0
11
40
to
21
60
21
60
to
28
80
28
80
to
36
00
36
00
to
43
20
43
20
to
50
40
50
40
to
57
60
57
60
to
64
80
64
80
to
72
00
72
00
to
79
20
79
20
to
86
40
86
40
to
93
60
93
60
to
10
08
0
10
08
0 t
o 1
08
00
10
80
0 t
o 1
15
20
11
52
0 t
o 1
22
40
12
24
0 t
o 1
29
60
12
96
0 t
o 1
36
80
13
68
0 t
o 1
44
00
14
40
0 t
o 1
51
20
15
12
0 t
o 1
58
40
15
84
0 t
o 1
65
60
16
56
0 t
o 1
72
80
17
28
0 t
o 1
80
00
0 t
o 7
20
72
0 t
o 1
44
0
11
40
to
21
60
21
60
to
28
80
28
80
to
36
00
36
00
to
43
20
43
20
to
50
40
50
40
to
57
60
57
60
to
64
80
64
80
to
72
00
72
00
to
79
20
79
20
to
86
40
86
40
to
93
60
93
60
to
10
08
0
10
08
0 t
o 1
08
00
10
80
0 t
o 1
15
20
11
52
0 t
o 1
22
40
12
24
0 t
o 1
29
60
12
96
0 t
o 1
36
80
13
68
0 t
o 1
44
00
14
40
0 t
o 1
51
20
15
12
0 t
o 1
58
40
15
84
0 t
o 1
65
60
16
56
0 t
o 1
72
80
17
28
0 t
o 1
80
00
Wire Length (m)
Nu
mb
er
of
Wir
es
1
10
100
1000
10000
100000
*After K. Guarini IBM Semiconductor Research and Development Center
• >50% of active power (switching) dissipation is in microprocessor interconnects • >90% of interconnect power is consumed by only 10% of the wires
MIT Lincoln LaboratoryFermilab -25
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Range of Wire in One Clock Cycle*
*After S. Amarasinghe, MIT Laboratory for Computer Science and Artificial Intelligence
0
50
100
150
200
250
300
1995 2000 2005 2010 2015
700 MHz
1.25 GHz
2.1 GHz
6 GHz
10 GHz13.5 GHz
Year
(20 mm x 20 mm Die)Pro
cess
Tec
hn
olo
gy
(nm
)
From 2003 ITRS Roadmap
• 3D Integration increases accessible active devices
MIT Lincoln LaboratoryFermilab -26
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Motivation for3-D Circuit Technology
High Bandwidth-Processors
Reduced Interconnect Delay
AdvancedFocal Planes
Exploiting DifferentProcess Technologies
Mixed MaterialSystem Integration
MIT Lincoln LaboratoryFermilab -27
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Pad-Level “3D Integration”Die Stacking
ChipPAC, Inc. Tessera, Inc.
Stacked Chip-Scale PackagesStacked-Die Wire Bonding
1 mm
In Production!
MIT Lincoln LaboratoryFermilab -28
CLK 2/28/2007
Approaches to High-Density 3D Integration(Photos Shown to Scale)
10 m
Bump Bond used to flip-chip interconnect
two circuit layers
Three-layer circuit using MIT-LL’s SOI-based vias
Two-layer stack with insulated vias through
thinned bulk Si
10 mPhoto Courtesy of RTI
3D-Vias
Tier-1
Tier-2
Tier-1
Tier-3
Tier-23D-Vias
10 m
MIT Lincoln LaboratoryFermilab -29
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Advantages of Silicon-on-Insulator (SOI)
for 3-D Circuit Integration• The electrically active portion of an integrated
circuit wafer is < 1% of the total wafer thickness
• Buried oxide layer in SOI provides ideal etch stop for wafer thinning operation prior to 3D integration
• Full oxide isolation between transistors allows direct 3D via formation without the added complexity of a via isolation layer
• SOI’s enhanced low-power operation (compared to bulk CMOS) reduces circuit stack heat load
Handle Silicon
Buried Oxide
Bonding Layer
SOI Cross-Section
Oxide
~675 m
~6 m
MIT Lincoln LaboratoryFermilab -30
CLK 2/28/2007
3-D Circuit Integration Flow-1
• Fabricate circuits on SOI wafers– SOI wafers greatly simplify 3D integration
• 3-D circuits of two or more active silicon layers can be assembled
Handle Silicon
Buried Oxide
Wafer-1
Handle Silicon
Buried Oxide
Wafer-2
Handle Silicon
Buried Oxide
Wafer-3
Wafer-1 can be either Bulk or SOI
MIT Lincoln LaboratoryFermilab -31
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• Invert, align, and bond Wafer-2 to Wafer-1
3-D Circuit Integration Flow-2
• Remove handle silicon from Wafer-2, etch 3D vias, deposit and CMP damascene tungsten interconnect metal
Concentric 3D Via
IC2
Wafer-1 Handle Silicon
Tier-1
Tier-2
Wafer-1
Wafer-2
Wafer bond
Handle Silicon
Buried Oxide
“Back Metal(s)”
MIT Lincoln LaboratoryFermilab -32
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• Invert, align, and bond Wafer-3 to Wafer-2/1-assembly, remove Wafer-3 handle wafer, form 3D vias
3-D Circuit Integration Flow-3
• Etch Bond Pads
IC2
Wafer-1 Handle Silicon
IC3
Tier-1
Tier-2
Tier-3
IC2
Wafer-1 Handle Silicon
IC3
Tier-1
Tier-2
Tier-3
IEEE Trans. on Electron Devices, Vol. 53, No. 10, October 2006
MIT Lincoln LaboratoryFermilab -33
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3D-Specific Enabling Technologies
Precision wafer-wafer alignmentHigh-density 3D-Via
Low temperature oxide-bond process
Bond Interface
1.2 1.4 1.6 1.8 2.0 2.2 2.4
1 hr.
10 hr.Ea=0.14eV
500450 400 350 300 250 200 150T(oC)
275oC, 10 h
1000/T (oK-1)1.2 1.4 1.6 1.8 2.0 2.2 2.4
100
1000
10000
1 hr.10 hr.Ea=0.14eV
450 400 350 300 250 150
275oC, 10 hr
Su
rfa
ce
En
erg
y (
mJ
/m2 )
MIT Lincoln LaboratoryFermilab -34
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4-Side-Abuttable Mosaic Focal Planes
1024 x 1024 Image
Image acquired at 10 frames/sec(Background Subtracted, Pixel Yield > 99.9%, 3.8M transistors)
Presented at 2005 ISSCC
5 mPixel
3D-Via CMOSMetal
CMOSVias
DiodeMetal
Transistor LevelBM1
Photodiode Tier 5 m5 mPixelPixel
3D-Via CMOSMetal
CMOSVias
DiodeMetal
Transistor LevelBM1
Photodiode Tier
Imager Cross-Section(8 m Pixel Pitch)
4 x 4 Tiled Array(mock-up)
• Tier-1: 100% fill-factor silicon photodetector layer
• Tier-2: CMOS address and readout layer
MIT Lincoln LaboratoryFermilab -35
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3D-Integrated, 3-Tier Avalanche Photodiode Focal Plane
• VISA laser radar focal plane based on single-photon-sensitive Geiger-mode avalanche photodiodes– 64 x 64 format – 50-m pixel size
To-Scale Pixel Layout of Completed 3-tier Laser Radar Focal Plane
Tier-1AvalanchePhotodiode
(APD)
Tier-2APD
Drive/SenseCircuitry
Presented at 2006 ISSCC
Tier-3High-Speed
Counter
~250 transistors/pixel(50 m x 50 m)
10 mTier-1: 30V Back Illuminated APD Layer
Tier-2: 3.5V SOI CMOS Layer
Tier-3: 1.5V SOI CMOS Layer
Completed Pixel Cross-Sectional SEM
10 m
Transistors
3DVia
3DVia
MIT Lincoln LaboratoryFermilab -36
CLK 2/28/2007
First 3-D IC Multiproject Run (Three 180-nm, 1.5 volt FDSOI CMOS Tiers)
MIT
NRL
Cornell
Pennsylvania
Delaware
Purdue
Idaho
RPI
Johns Hopkins
StanfordTennessee
Lincoln Laboratory
UCLA
Maryland
WashingtonNorth Carolina State
Yale
HRL
BAE
LPS
Minnesota
MIT
NRL
Cornell
Pennsylvania
Delaware
Purdue
Idaho
RPI
Johns Hopkins
StanfordTennessee
Lincoln Laboratory
UCLA
Maryland
WashingtonNorth Carolina State
Yale
HRL
BAE
LPS
Minnesota
3DL1 Participants (Industry, Universities, Laboratories)
• Leverages MIT-LL’s established 3D circuit integration technology- Low temperature oxide bonding,
precision wafer-to-wafer overlay, high-density 3D interconnect
• Preliminary 3D design kits developed- Mentor Graphics – MIT-LL, Cadence –
NCSU, Thermal Models – CFRDC
• Design guide release 11/04, fab start 6/05, 3D-integration complete 3/06
Concepts being explored in run:
3D-integrated S-band digital beam former
3D FPGAs, digital, and digital/mixed-signal/RF
ASICs exploiting parallelism of 3D-interconnects
Low Power Multi-gigabit 3D data links
3D analog continuous-time processor
Thermal 3D test structures and circuitsNoise coupling/cross-talk test structures and circuits
Stacked memory (SRAM, Flash, and CAM)Self-powered CMOS logic (scavenging)Integrated 3D Nano-radio and RF tags
Intelligent 3D-interconnect evaluation circuitsDC and RF-coupled interconnect devices
3D-integrated S-band digital beam former
3D FPGAs, digital, and digital/mixed-signal/RF
ASICs exploiting parallelism of 3D-interconnects
Low Power Multi-gigabit 3D data links
3D analog continuous-time processor
Thermal 3D test structures and circuitsNoise coupling/cross-talk test structures and circuits
Stacked memory (SRAM, Flash, and CAM)Self-powered CMOS logic (scavenging)Integrated 3D Nano-radio and RF tags
Intelligent 3D-interconnect evaluation circuitsDC and RF-coupled interconnect devices
22 mm
Completed 3DL1 Die Photo
MIT Lincoln LaboratoryFermilab -37
CLK 2/28/2007
Cross-Section of 3-Tier 3D-integrated Circuit (DARPA 3DL1 Multiproject Run)
3 FDSOI CMOS Transistor Layers, 10-levels of Metal
Tier-1: 180-nm, 1.5V FDSOI CMOS
Tier-2: 180-nm1.5V FDSOI CMOS
Tier-3: 180-nm, 1.5V FDSOI CMOSTier-3: Transistor Layer
Tier-2: Transistor Layer
3D-Via
3-Level Metal
StackedVias
Oxide Bond Interface
Oxide Bond Interface
10 m
Tier-1: Transistor Layer
3D-Via 3D-Via
Back Metal
Metal Fill
MIT Lincoln LaboratoryFermilab -38
CLK 2/28/2007
3D Technology Improvements(DARPA 3DL1 Multiproject Run)
• 3D technology enhancements successfully demonstrated in 3DL1 Run – Stacked 3D-vias for electrical
and thermal interconnect– 2X reduction in 3D-via size– Improved tier-to-tier overlay
99-Stage Ring Oscillator @1.5V
5 m
Scaled Conventional5 m
5 m
Stack 3D-vias demonstrated
>95% yield on 4800 link chains
Stacked 3D-via resistance ~1
Can be used as thermal vias Vector Scale
1 m
Vector Scale
1 m
Vector Scale
1 m
~0.5 m 3 Tier-to-Tier Registration
High-Yield on >5000-link Scaled 3D-via Chains
MIT Lincoln LaboratoryFermilab -39
CLK 2/28/2007
3-Tier, 3D-Integrated Ring Oscillator (DARPA 3DL1 Multiproject Run)
• Functional 3-tier, 3D-integrated ring oscillator – Uses all three active transistor
layers, 10 levels of metal and experimental stacked 3D-vias
– Demonstrates viability of 3D integration process
Tier-1: FDSOI CMOS Layer
Tier-2: FDSOI CMOS Layer
Tier-3: FDSOI CMOS Layer
3D Ring Oscillator Cross-Sectional SEM
5 m
Transistors
3DVia
3DVia
Stacked3D Via
0
100
200
300
400
500
600
700
0.5 0.75 1 1.25 1.5 1.75
Sta
ge
Del
ay (
ps)
Power Supply (V)
99-Stage Ring Oscillator @1.5V
MIT Lincoln LaboratoryFermilab -40
CLK 2/28/2007
3D IC Multiproject Run Highlights (a)
• RPI, Jack McDonald (PI)Designed high-bandwidth 3D
SRAM for high-performance computing applications
Demonstrated first functional 3D-integrated, 3-tier memory
• Stanford Univ., Sang-Min Lee, Bruce Wooley (PI)Designed and demonstrated high
dynamic range (18-19 bit) high frame rate (3000 fps) 3D ADC for LWIR focal plane array readouts
Reduced pixel size for complex readout to 50 m x 50 m
MIT Lincoln LaboratoryFermilab -41
CLK 2/28/2007
3D IC Multiproject Run Highlights (b)
• UCLA, Frank Chang (PI)Designed low power, low BER
10Gbps capacitor-coupled vertical Interconnects for 3D-IC
Demonstrated Baseband Impulse Shaping Interconnect (BISI) and self-synchronized RF Interconnect (RFI) at >11 GHz with BER < 1x10-14
>10x lower energy/bit and >3x faster than previously reported 180-nm 2D communication circuits
• NRL-Cornell-BAE, Maxim Zalalutdinov (PI)Designed 3D CMOS-integrated high
frequency, high quality factor micromechanical resonators
Demonstrated tuning fork and slot resonators at 34MHz with Q = 4700
Input
Output
10ps/div
100mV/div
500ps/divInput
Output
10ps/div
100mV/div
500ps/div
Input vs OutputOutput Eye diagram
RFI Test @ 12.5 GHz data rate
33.975 34.000 34.025 34.050 34.0750
2
4
6
8
10
12
Am
plit
ude,
a.u
.
Frequency, MHz
Q=4700
33.975 34.000 34.025 34.050 34.0750
2
4
6
8
10
12
Am
plit
ude,
a.u
.
Frequency, MHz
Q=4700
Post Process Released Resonator
MIT Lincoln LaboratoryFermilab -42
CLK 2/28/2007
3D IC Multiproject Run Highlights (c)
• Cornell Univ., Sandip Tiwari (PI)Designed full range of 3D test
structures and circuitsCharacterized 3D heat dissipation Demonstrated functional
asynchronous 3D FPGA Demonstrated low voltage adaptive
analog circuits with backgatingDemonstrated RF cross-talk reduction
through 3D-integrated ground planes
• Yale Univ., Eugenio Culurciello (PI)Designed 3D integrated detector
sensitive to intensity, contours, and motion
Demonstrated functionality of single and multiple tier photo detectors
Asynchronous 3D FPGA
8 bit data path
processors
Operationalamplifiers
Thermal testing
RF, Mixed-signal and Analog designs
RF & Cross-talk Reduction
Tier C
Tier A
Tier BAsynchronous 3D FPGA
3D pixel viewthree 3D vias per pixel
MIT Lincoln LaboratoryFermilab -43
CLK 2/28/2007
Temperature Measurement Results from 3DL1 Multiproject Run
M3
Back metal
3D via
T3
M1T2
Resistor heater
T1
M3
M2
M3
BOX
BOX via
Substrate
M1
M2
0.8 × 0.8 m
Diode temperaturesensor
M1
M2
M3
Back metal
3D via
T3
M1T2
Resistor heater
T1
M3
M2
M3
BOX
BOX via
Substrate
M1
M2
0.8 × 0.8 m
Diode temperaturesensor
M1
M2
0
50
100
150
200
250
300
0 50 100 150 200 250 300 350 400 450
DC Power (mW)
Tem
per
atu
re (
C)
None
BkMetal
BkMetal+BOXVia
Back metal
Back metal andBOX vias
No heat-sink
0
50
100
150
200
250
300
0 50 100 150 200 250 300 350 400 450
DC Power (mW)
Tem
per
atu
re (
C)
None
BkMetal
BkMetal+BOXVia
Back metal
Back metal andBOX vias
No heat-sink
• Thermal characterization structures included in 3DL1 Multiproject Run
– Measure temperatures in stack– Explore thermal sink paths through
buried oxide (BOX) vias and “Back-metal” hear sinks
– Calibrate thermal modeling tools
3D Temperature Characterization Structure
MIT Lincoln LaboratoryFermilab -44
CLK 2/28/2007
3DM2 Multiproject Run(3 Active Tiers, 11 levels of Metal)
• 3DM2 includes 2 “digital” 180-nm FDSOI CMOS tiers and 1 RF 180-nm FDSOI CMOS tier– 11 metal layers including:
2-m-thick RF Backmetal
Tier-2 Backmetal
• Second 3D Multiproject Design Schedule (3DM2)– 3DM2 announcement
(Mar 06)
– Contributor selection (Apr 06)
– Design guide release (Apr 06)
– Submission deadline (November 06)
MIT Lincoln LaboratoryFermilab -45
CLK 2/28/2007
3D-Integration with III-V Detectors
• Enables extension of 3D-integration technology to higher density, longer wavelength focal plane detectors
– Tight pixel-pitch IR focal planes and APD arrays
– InGaAsP (1.06-m), InGaAs (1.55-m)
• High-yield, 3.4 m pitch 3D-via chains demonstrated
150-mm-diameter InP wafer with oxide-bonded circuit layer transferred from silicon wafer
Presented at 2006 IPRM
MIT Lincoln LaboratoryFermilab -46
CLK 2/28/2007
SummaryA Few Closing Remarks…
• Transistor feasibility has been demonstrated to below ~10 nm gate lengths
• “Conventional” CMOS (Bulk, SiO2 gate oxide, poly gates) faces significant challenges to scale below 45nm-node
– Ultra-thin-body SOI, FinFET, Dual-Gate, Metal Gate, High-k – No new device technology has yet emerged that is expected to dethrone silicon
CMOS
• Moore’s Law scaling is showing its age and could run into serious speedbumps in the next few years (including economics), but the 2020 roadmap is theoretically feasible
– Process technology improvements are no longer the performance drivers
• Future performance improvements will most likely come through circuit, system architecture, and software advancements
• Initial 3D technology demonstrations (at MIT-LL) are centered around advanced focal plane architectures
– This is the “low hanging fruit”
• Full impact of 3D integration is far from being realized, but has the potential of revolutionizing the design architecture of future circuits and systems
• Potential application areas include: High-end focal planes, FPGAs, Dense memory, memory on processor, mixed signal systems, mixed material systems
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