3rd 3ddresd: sysgen

POLITECNICO DI MILANO

SysGen- System Generation in Caronte flow -

DDynamic ynamic RReconfigurability econfigurability inin EEmbeddedmbedded SSystemsystems DDesignesign

Matteo Renesto: matteo.renesto@dresd.org

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Context of WorkContext of Work

<<Earendil>>

<<Caronte>>

System Generation:

- Low Level Reconfiguration

- Last step of Caronte Flow

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State of ArtState of Art

At present for system generation there are two different flows, for different cases

-Acheronte, that uses Module-Based Partial reconfiguration.

-Inca, that uses Early Access Partial Reconfiguration.

The problem:To use one or the other flow we need to fulfill some requirements (ISE version and Board), otherwise the process will fail.At present, users must take care of this aspect.

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Proposed solutionProposed solution

Theoretical AspectWe need a Standard flow for System Generation

that should be:Correct Complete

START

Given a problem P, composed by a Project and HW – SW context.

IF it is possible to solve that problem, that is to realize the project,

THEN use right flow, in order to produce the right result

ELSE

Show why it’s not possible.

END

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Goal: A Standard FlowGoal: A Standard Flow

System Generator

Reconfigurable Project System Characterization

Acheronte:Module-Based

INCA:EAPR

Other:MB or EAPR or Other

Erroror

Success

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Key aspectsKey aspects

System Characterization.

Reconfigurable Hardware Design.

Reconfigurable Flow with different ISE version

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System CharacterizationSystem Characterization

What do we mean with “System Characterization” ?Design possibilites:-Area dimension-Number of modular areas supported-2D placement or 1D placement-2D reconfiguration or 1D reconfiguration-Type of GPP supported (PPC and/or Microblaze)-Dynamic or only static.-Type of dynamic reconfiguration supported (MB–EAPR)-Internal or External reconfiguration.

Tools-ISE version.-Board.

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System CharacterizationSystem Characterization

To decide if is possibile to realize the project.

To point out the logical error of a project.

To use the right flow.

Why is important to know the characterization?

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Requirements:a) Your IP Cores. VHDL filesb) Bus HardMacros. NMC files c) Your Application, .c file.

Procedure, in EDK:1) Create a new architecture with EDK, following the wizard.2) Import your IP cores as peripheral (at this point only one for each reconfigurable area)3) Implement your software. 4) Generate Netlist and generate BistreamNow you have a static architecture, you should make it dynamic.

How To Create a Reconfigurable How To Create a Reconfigurable ProjectProject

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How To Create a Reconfigurable How To Create a Reconfigurable ProjectProject

Take system.vhd, generated by EDK

Using ArchGen generate top.vhd and fix.vhd

Using the wrapper obtained from EDK project you must generate all modules for all’IP cores.

Syntetize all: top, fix and modules. Only top with I/O buffers.

Take from EDK project the constrains files, edit it adding constrains for Bus Macros, and areas.Mode = “Reconfig”; constrain defines that an area will be reconfigurable.

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Matching our flow with Xilinx Matching our flow with Xilinx ISEISE

  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1

Module-Based ? ? ? ?

Early Access ? ? ? ?

In order to have a working flow,we have to analyze each case, and what that case allows us to do.

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Module Based FlowModule Based Flow

Working only on Virtex II, Virtex II pro, Virtex-E, Virtex 4 Virtex 5.

No signal crossing reconfigurable area allowed.

No 2D reconfiguration. Areas must use all the height.

Reconfigurable area size, multiple of 4 (number of slices)

XC2VP7 is usually too small for our achitecture, generated with EDK.

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MB Flow with ISE 7.1: MB Flow with ISE 7.1: AcheronteAcheronte

We can realize an architecture like Yara, with a fix area and some reconfigurable regions.

Following Module Based Flow.

Step 1: Initial BudgetingStep 2: build of Fix areaStep 3: build of each moduleStep 4: MergeStep 5: Generate Bitstream.

Important: Use the last ISE’s service pack!

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First ResultFirst Result

Early Access Flow is not yet supported for ISE 7.1.

  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1

Module-Based V

Early Access X

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Module Based with ISE 8Module Based with ISE 8

Theoretically, following Xilinx user guide, there are no differences form Module Based with ISE 7.1

Pratically, Module Based partial reconfiguration with ISE 8.1 or 8.2 DOESN’T WORK!

During Merge Phase, PAR fail to route some signal.

If we remove the constrains “MODE = RECONFIG” we meet no error.

Let’s analyze the problem…

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The problem of ISE 8The problem of ISE 8

During MAP phase Xilinx tool introduces the power lines to the design. In order to supply power to SLICES, BRAM etc..

During Route phase the tool should route two signals that drive power.

GLOBAL_LOGIC0 and GLOBAL_LOGIC1 (they are GND and VCC)

But PAR, when doesn’t crash throwing exception, fails.

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The problem of ISE 8The problem of ISE 8

All other unrouted signals can be routed by FPGA Editor. Problems come from the first unrouted…

Little changes in the design, may remove other unrouted signals, but not GLOBAL_LOGIC0 (or 1)

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The problem of ISE 8The problem of ISE 8

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The problem of ISE 8The problem of ISE 8

Other solutions proposed by Xilinx, like “reentrant route”, produce no different result.If we try to route manually that signal…… FPGA Editor Crash!

Let’s us setup EPAR patch… to solve this problem too…

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Early Access Partial Early Access Partial ReconfigurationReconfiguration

EAPR flow have no big differences from Module Based, but gives us some good features

Manage arch.exclude file, which provides a description of busy logic, this allows us to cross reconfigurable region with signals without big troubles.

Manage 2D placement, and 2D reconfiguration, if the device allows it, like Virtex 4 and 5 do.

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EAPR on ISE 8.2: INCA FlowEAPR on ISE 8.2: INCA Flow

ISE 8.2 is required, EAPR patch doesn’t work correctly with previous version like 8.1

Inca is an automated flow that follows similar steps like Acheronte, but using EAPR patch.

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Second ResultSecond Result

With ISE 8.2, Module Based doesn’t work correctly

EAPR fixes the problem and offers new features.

  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1

Module-Based V X

Early Access X V

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ISE 9.2ISE 9.2

No significant differences, for us, from ISE 8.2

  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1

Module-Based V X X

Early Access X V V

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ISE 10.1ISE 10.1

Module Based was removed from the last update of Xapp290

EAPR patch hasn’t been still relased for ISE 10.1.

  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1

Module-Based V X X X

Early Access X V V ?

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ConclusionConclusion

Now we have a full coverage of all cases, and we know, in every case, if Dynamic Partial Reconfiguration does work or not.Unfortunately EAPR project, often aren’t compatible with old Module Based.With this know-how we could build automated tools for:

A) Create a System Characterization that could give guidelines to all the design procedure, signalling to the user all the errors and conflicts as output.

B) Implement our design with only one tool that follows the right flow in each situation.

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Future WorksFuture Works

Create only one tool for Low Level Reconfiguration, that in autonomus way, once launched, starts creating context charachterization, and follows all the steps, without user’s intervention until final result.

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Future WorksFuture Works

Xilinx is developing a new flow for Dynamic Partial Reconfiguration, so we will need to update our classification and tools.

  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1 ISE X.Y

Module-Based V X X X X

Early Access X V V ? X

New Flow X X X X V

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Questions?Questions?

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