4. mos: device operation and large signal...

4. MOS: Device Operation and Large Signal Model

Lecture notes: Sec. 4

Sedra & Smith (6th Ed): Sec. 5.1-5.3 Sedra & Smith (5th Ed): Sec. 4.1-4.3

ECE 65, Winter2013, F. Najmabadi

Operational Basis of a Field-Effect Transistor (1)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (2/29)

P-type semiconductor

Insulator

Dopent ions

Holes (majority carries)

Consider the hypothetical semiconductor below: (constructed similar to a parallel plate capacitor)

Electrical contact

If we apply a voltage v1 between electrodes, a charge Q = C v1 will appear on each capacitor plate. o The electric field is strongest at the interface with the

insulator and charge likes to accumulate there.

Holes are pushed away from the insulator interface forming a “depletion region”.

Depth of depletion region increases with v1.

Depletion Region (no majority carrier)

If we increase v1 above a threshold value (Vt), the electric field is strong enough to “pull” free electrons to the insulator interface. As the holes are repelled in this region, a “channel” is formed which contains electrons in the conduction band (“inversion layer”).

Inversion layer is a “virtual” n-type material.

Depletion Region (no majority carrier)

Inversion layer (“channel”)

With inversion layer (v1 > Vt):

A current will flow in the channel

Current will be proportional to electron charge in the channel or (v1 − Vt )

Magnitude of Current i2 is controlled by voltage v1 (a Transistor!)

We apply a voltage across the p-type semiconductor: (Assume current flows only in the n-type material, ignore current flowing in the p-type semiconductor)

No inversion layer (v1 < Vt):

No current will flow

We need to eliminate currents flowing in the p-type, i.e., current flows only in the “channel” which is a virtual n-type.

Body-source and body-drain junctions should always be in reverse bias for FET to work!

Make n-type material terminals (set up diodes between terminals & p-type “body”)

Heavy doping of the n-type terminals provides a source of free electrons for the channel.

Make insulator layer as thin as possible to increase the electric field.

Channel width (L) is the smallest feature on the chip surface

MOSFET implementation on a chip

MOSFET “cartoons” for deriving MOSFET characteristics MOSFET (or MOS): Metal-oxide field-effect transistor

NMOS: n-channel enhancement MOS

NMOS i-v Characteristics (1)

To ensure that body-source and body-drain junctions are reversed bias, we assume that Body and Source are connected to each other and vDS ≥ 0. o We will re-examine this assumption later

Without a channel, no current flows (“Cut-off”).

For vGS > Vtn, a channel is formed. The total charge in the channel is

)SiO(for F/m 1045.39.3

insulator ofy permitivit :insulator of Thickness :

areaunit per eCapacitanc :

0−×==

tnGSox

LWCC-VvWL CCV|Q|

Overdrive Voltage: VOV = vGS –Vtn

vGS > Vtn A channel is formed

Apply a small vDS between drain & source.

A current flows due to the “drift” of electrons in the n-channel:

DSOVoxnD

DStnGSoxnD

For small vDS, MOS acts as a resistance with its conductivity controlled by VOV (or vGS).

WCgv gi OVoxnDSDSDSD with µ==

When vDS is increased the channel becomes narrower near the drain (local depth of the channel depends on the difference between VG and local voltage).

Triode Mode

[ ]25.0 DSDSOVoxnD vvVL

WCi −= µ

When vDS is increased further such that vDS = VOV , the channel depth becomes zero at the drain (Channel “pinched off”).

When vDS is increased further, vDS > VOV , the location of channel pinch-off remains close to the drain and iD remains approximately constant.

Saturation Mode 25.0 OVoxnD V

LWCi µ=

For a given vGS (or VOV)

NMOS i-v Characteristics Plot (1)

NMOS i-v characteristics is a surface

* Plot for Vt,n = 1 V and µnCox (W/L) = 2.0 mA/V2

),( DSGSD vvfi =

Looking at surface with vGS axis pointing out of the paper*

*Note: surface was truncated (i.e., vGS < 5 V)

Channel-Width Modulation

The expression we derived for saturation region assumed that the pinch-off point remains at the drain and thus iD remains constant.

In reality, the pinch-off point moves “slightly” away from the drain: Channel-width Modulation

DSOVoxnD

1 5.0 2

Body Effect

Recall that Drain-Body and Source-Body diodes should be reversed biased. o We assumed that Source is connected to the body (vSB = 0) and vDS = vDB > 0

In a chip (same body for all NMOS), it is impossible to connect all sources to the body (all NMOS sources are connected together.

Thus, the body (for NMOS) is connected to the largest negative voltage (negative terminal of the power supply).

Doing so, changes the threshold voltage (called “Body Effect”)

( )|2||2| 0, FSBFtntn VVV φφγ −++=

In this course we will ignore body effect as well as other second-order effects such as velocity saturation.

P-channel Enhancement MOS (PMOS) A PMOS can be constructed analogous to an NMOS: (n-type body), heavily

doped p-type source and drain.

A virtual “p-type” channel is formed in a P-MOS (holes are carriers in the channel) by applying a negative vGS.

i-v characteristic equations of a PMOS is similar to the NMOS with the exception: o Voltages are negative (we switch the terminals to have positive voltages: use

vSG instead of vGS ).

o Use mobility of holes, µp , instead of µn in the expression for iD

MOS Circuit symbols and conventions

PMOS NMOS

MOS i-v Characteristics Equations

NMOS (VOV = vGS – Vtn)

[ ]DSOVoxnDOVDSOV

DSDSOVoxnDOVDSOV

WCiVvV

+=≥≥

−=≤≥

1 5.0 and 0 :Saturation

2 5.0 and 0 :Triode

0 0 :Off-Cut

PMOS (VOV = vSG – |Vtp|)*

[ ]SDOVoxpDOVSDOV

SDSDOVoxpDOVSDOV

WCiVvV

+=≥≥

−=≤≥

1 5.0 and 0 :Saturation

2 5.0 and 0 :Triode

0 0 :Off-Cut

*Note: S&S defines |VOV |= vSG – |Vtp| and uses |VOV |in the PMOS formulas.

MOS operation is “Conceptually” similar to a BJT -- iD & vDS are controlled by vGS

Controller part: Circuit connected to GS sets vGS (or VOV )

Controlled part: iD & vDS are set by transistor state (& outside circuit)

A similar solution method to BJT:

o Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve with the corresponding MOS equation and validate the assumption.

MOS circuits are simpler to solve because iG = 0 ! o However, we get a quadratic equation to solve if MOS in triode (check MOS in

saturation first!)

Example 1: In the circuit below, RD = 1 k, and VDD = 12 V. Compute vo for vi = 0, 6, and 12 V. (µnCox (W/L) = 0.5 mA/V2 , Vt = 2 V, and λ = 0 )

DSDDSDDDD

viviRVvv

10 12 :KVL-DS

:KVL-GS3

V 12 0 10 12 :KVL-DS

0 off-Cut V2 0 :KVL-GS3 ==→+×=

=→→=<==

vvviVvv

correct Assumption V 4V 0.8V 0.8 104 10 12 :KVL-DS

mA 0.44105.05.0 5.0

V 4 :Saturation Assume

→=>===→+××=

=×××==

OVoxnD

Part 1: vi = 0

V4 off-Cutin Not V2 6 :KVLGS

=−=→=>==−

VvVVvv

Part 2: vi = 6 V

o DSvv =

DSDDSDDDD

viviRVvv

10 12 :KVL-DS

:KVL-GS3

incorrect Assumption V 10V 13V .13 100.25 10 12 :KVL-DS

mA 0.2510105.05.0 5.0

V 10 :Saturation Assume

→=>−=−=→+××=

=×××==

OVoxnD

V10 off-Cutin Not V2 12 :KVL-GS

=−=→=>==

VvVVvv

Part 3: vi = 12 V

o DSvv =

DSDDSDDDD

viviRVvv

10 12 :KVL-DS

:KVL-GS3

o DSvv =

]20[ 105.05.0 1012

10 12 :KVL-DS

V 10 :Triode Assume

+−××××=

DSDSDS

DSDSOVoxnD

V10 =−= tGSOV VvV

Part 3 (cont’d): vi = 12 V

mA 8.9 10 12

V 10 V 2.2)(incorrect 10 V 8.21

3 =→+×=

=<===>==

iviVvv

NMOS Transfer Function (1)

vi can be applied directly to MOS There is no need for a RG .

Circuit Equations: o vGS = vi

o NMOS iv characteristics: iD = f (vGS , vDS ) o KVL: vo = vDS = VDD − RD iD

2) Just to the right of point A: o VOV = vGS − Vt is small, so iD

is small. o vDS = VDD − RD iD is close to VDD

o Thus, vDS > VOV and NMOS is in saturation.

1) For vGS < Vt , NMOS is in cutoff: iD = 0 & vDS = VDD − RD iD = VDD

3) As vGS increases: o VOV = vGS − Vt and iD become larger;

o vDS = VDD − RD iD becomes smaller.

o At point B, vDS = VOV

4) To the right of point B, vDS < VOV = vGS − Vt and NMOS enters triode.

Point B is called the “Edge of Saturation”

2) Just to the right of point A: o VOV = vGS − Vt is small, so iD

is small. o vDS = VDD − RD iD is close to VDD

o Thus, vDS > VOV and NMOS is in saturation.

3) As vGS increases: o VOV = vGS − Vt and iD become larger;

o vDS = VDD − RD iD becomes smaller.

o At point B, vDS = VOV

1) For vGS < Vt , NMOS is in cutoff: iD = 0 & vDS = VDD − RD iD = VDD

4) To the right of point B, vDS < VOV = vGS − Vt and NMOS enters triode.

Point B is called the “Edge of Saturation”

Graphical analysis of NMOS Transfer Function (1)

KVL equation is a plane in this space.

Intersection of KVL plane with the iv characteristics surface is a line.

NMOS operating point is on this line (depending on the value of vGS.)

DSDDDD

viRVvvfii-v

:KVL),( :siticsCharacteri NMOS

If we look from the bottom (iD axis out of the paper), we can see the transfer function.

Graphical analysis of NMOS Transfer Function (2)

Every point on the load line corresponds to a specific vGS value.

As vGS increases, NMOS moves “up” the load line.

Looking from the bottom

Looking parallel to vGS axis

NMOS Functional circuits

Similar to a BJTs in the active mode, NMOS behaves rather “linearly” in the saturation region (we discuss NMOS amplifiers later)

Transition from cut-off to triode can be used to build NMOS switch circuits. o Voltage at point C (see graph)

depends on NMOS parameters and the circuit (in BJT vo = Vsat)!

We can also built NMOS logic gate similar to a RTL. But there is are much better gates based on CMOS technology!

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