carbonnanotubes: highly#energyvefficientsub … · 4/3/2017 · vlsi#circuit#analysis...
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~ 2X benefit
~ 1.25X benefit
~ 4X benefit
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• Carbon nanotube FETs§ 9X EDP benefit vs. FinFET (sub-10 nm node)
§ Processor cores (wires included)
• Silicon alternatives§ 30% benefit
Key Message
EDP: “energy-delay product”
on-‐chip thermal mgmt.
VLSI Circuit Analysis
Multiple Technologies Analyzed
5nm8nm
[Tsutsui IEDM 05]100nm
FinFET NWFET ETSOI CNFETCNTd~1nm
• Oracle OpenSparc T2 SoC§ Synthesis + place & route
§ Parasitics: standard cells + interconnects
FETs: 28 M
Area: 0.27 mm2
Total wire length: 9.5 meterscore5
core6
core7
core8
core1
core2
core3
core4
www.opensparc.net
VLSI Design Flow: Step 2 of 2• Circuit EDP optimization§ Synthesis + place & route: 100s of designs
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total energy per cycle (nJ)
clock frequency (GHz)
Pareto-optimal curve
EDP-optimal design
design space sweep:•Target frequency•Off-current•VDD•…
Results: OpenSparc EDP
total energy/cycle
(nJ)
clock frequency (GHz)
CNFET: 9.0× EDP benefit• same IOFF & power density
30% benefit
7 nm node: OpenSparc T2 cores
VLSI Design Flow: Step 1 of 2Step 1) Library characterization
§ Multiple VDD & VT§ Each technology optimized separately*
compact models+
AOI222_X1
standard cell layouts+experimental data
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I D(mA/μm)
VDS (V)
datamodel
[Lee TED 15][IBM Nature Nanotech 10]
*Optimized parameters: gate length, contact length, …
…CNFET Enables Circuit Benefits
• 20% lower VDD• 25% drive current increase• 2X lower circuit capacitance§ Shorter LG
§ Reduced parasitics
§ Smaller FET widths required to meet timing
EDP ~ CV2 * CV/Ienergy delay
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on-current (mA/μm)
VDD (V)
CNFET, bestexperimental RC
CNFET, experimental7 nm node RCFinFET
FAQ2: Contact Resistance?• CNFET with experimental RC: outperforms Si
[IBM Science 15]
On-current taken for VGS = VDS = VDD with fixed IOFF = 100 nA/μm
MULTIPLE paths
5 nm node: OpenSparc “pku”
GOALdelay penalty
energy increase
spacing(σ/μ)2
%m-CNTs
s-CNTs removed
0.15 4% 4%0.3 0.9% 0.9%0.2 7% 1%0.1 4% 7%
ProcessImprovementoptions
Selective upsizing
Initial design point
FAQ 5: CNT Variations
• CNFET improves wire energy & delayFAQ3: Wires Limit Performance?
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I D(mA/μm)
VDS (V)
injectionvelocity
mobility
CNFET(ballistic)
LG scaling benefitscarrier transport benefits
FinFET(ballistic)
lower intrinsiccapacitance
lowerparasitics
fixed pitch
LG
FAQ4: Aren’t FETs Good Enough Already?• Ballistic transport & ~60 mV/dec sub-threshold slope§ Insufficient alone for energy efficiency
[Hills TCAD 15]
FAQ1: Where do Benefits Come From?• Simultaneous ultra-thin body + high drive current§ Challenging for bulk materials
superior carrier transport
d
LG<10nm
d~1nm for LG scaling
CNT
body thickness (nm)
mobility (cm2 /V.s) CNFET
ETSOIFinFET
NWFET
+2000
18000
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1000
0 10
Best experimental data from publications
ETSOIFinFETNWFETCNFET, experimental RC=18KΩ/CNTCNFET
RW,CWRDRIVE
CINCOUT
delay~½ RWCW+RDRIVECW+RWCIN+RDRIVECOUT+RDRIVECIN
energy~½ CWVDD2+½ CINVDD2+EINTERNAL
…
full chip energy/delay due to:wires vs. logic gates
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critical path delay(ns)
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energy/cycle(pJ)
wire delay components
…
7 nm node: OpenSparc “lsu”
Carbon Nanotubes:Highly Energy-Efficient Sub-10 nm VLSI
G. Hills1, M. Shulaker1, C.-S. Lee1, P. Debacker3, M. Garcia Bardon3, D. Yakimets3, R. Ritzenthaler3,P. Schuddinck3, D. Yang3, I. Radu3, F. Catthoor3, P. Raghavan3, A. Thean3, H.-S. P. Wong1, S. Mitra1,2
1Dept. EE & 2Dept. CS, Stanford University;; 3IMEC
Frequently-asked Questions (FAQ)CNFET: 9X energy efficiency vs. FinFET
sub-10 nm VLSI circuits+ physical design
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