ch28 microelectronic devices

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Chapter 28Fabrication of Microelectronic Devices

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Parts Made by Chapter 28 Processes

(a) (b) (c)

Figure 28.1 (a) A completed eight-inch wafer with completed dice. (b) A singlechip in a ball-grid array (BGA) with cover removed. (c) A printed circuit board.Source: Courtesy of Intel Corporation.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Fabrication of IntegratedCircuits

Figure 28.2 Outline of the generalfabrication sequence for integratedcircuits.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Fabrication of MOS Transistor

Figure 28.3 Cross-sectional views of the fabrication of a MOS transistor.Source: After R. C. Jaeger.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Allowable Particle Size Counts for Clean Rooms

Figure 28.4 Allowable particle size counts for different clean room classes.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Crystallographic Structure and Miller Indices for Silicon

Figure 28.5 Crystallographic structure and Miller indices for silicon. (a) Constructionof a diamond-type lattice from interpenetrating face-centered cubic-cells; one of eightpenetrating cells is shown. (b) Diamond-type lattice of silicon; the interior atoms havebeen shaded darker than the surface atoms. (c) Miller indices for a cubic lattice.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Finishing Operations on aSilicon Ingot to Produce

Wafers

Figure 28.6 Finishing operations on asilicon ingot to produce wafers (a)sawing the ends off the ingot; (b)grinding of the end and cylindricalsurfaces of a silicon ingot; (c) machiningof a notch or flat; (d) slicing of wafers;(e) end grinding of wafers; (f) chemical-mechanical polishing of wafers.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

CVD Diagrams

Figure 28.7 Schematic diagrams of (a) a continuous, atmospheric-pressureCVD reactor and (b) a low-pressure CVD. Source: After S. M. Sze.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Silicon Dioxide Growth

Figure 28.8 Growth of silicon dioxide showing consumption of silicon.Source: After S. M. Sze.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

General Characteristics of Lithography Techniques

Figure 28.9 Comparison of lithographytechniques.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Spinning of Organic Coating on Wafer

Figure 28.10 Spinning of an organic coating on a wafer.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Techniques of Pattern Transfer

Figure 28.11 Schematic illustration of (a) wafer stepper techniqueto pattern transfer and (b) step-and-scan technique.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Pattern Transfer by Photolithography

Figure 28.12 Pattern transfer by photolithography. Note that themask in Step 3 can be a positive or negative image of the pattern.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

SCALPEL Process

Figure 28.13 Schematic illustration of the SCALPEL process.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Moore’s Law

Figure 28.14 Illustration of Moore’s law. Source: After M. Madou.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

General Characteristics of Silicon EtchingOperations

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Comparison of Etch Rates

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Etching Directionality

Figure 28.15 Etching directionality. (a) Isotropic etching: etch proceeds verticallyand horizontally at approximately the same rate, with significant mask undercut. (b)Orientation-dependant etching (ODE): etch proceeds vertically, terminating on {111}crystal planes with little mask undercut. (c) Vertical etching: etch proceed verticallywith little mask undercut. Source: Courtesy of K. R. Williams, Agilent Laboratories.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Etch Rates of Silicon

Figure 28.16 Etch rates of silicon indifferent crystallographic orientations usingethylene-diamine/pyrocatechol-in-water asthe solution. Source: After Seidel, H. etal., Journal Electrochemical Society, 1990,pp. 3612-3626.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Application of Boron Etch Stop and Back Etchingto Form Membrane and Orifice

Figure 28.17 Application of a boron etch stop and back etching toform a membrane and orifice. Source: After Brodie, I., and Murray,J.J., The Physics of Microfabrication, Plenum Press, 1982.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Machining Profiles Associated with Dry-Etching

Figure 28.18 Machining profiles associated with different dry-etching techniques:(a) sputtering; (b) chemical; (c) ion-enhanced energetic; (d) ion-enhanced inhibitor.Source: After M Madou.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Etching

Figure 28.19 (a) Schematic illustration of reactive plasma etching. (b) Examples of deepreactive-ion etched trench. Note the periodic undercuts or scallops. (c) Near-verticalsidewalls produced through DRIE with an anisotropic-etching process. (d) An examples ofcryogenic dry etching showing a 145-µm deep structure etched into silison using a 2.0- µmthick oxide masking layer. The substrate temperature was -140°C during etching. Source:(a) After M. Madou. (d) After R. Kassing and I.W. Rangelow, University of Kassel, Germany.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Holes Generated from Square Mask

Figure 28.20 Various holes generated from a square mask in: (a) isotropic (wet)etching; (b) orientation-dependant etching (ODE); (c) ODE with a larger hole; (d)ODE with a rectangular hole; (e) deep reactive-ion etching; and (f) verticaletching. Source: After M. Madou.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Ion Implantation Apparatus

Figure 28.21 Schematic illustration for an apparatus for ion implantation.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

PN-Junction DiodeFabrication

Figure 28.22 Fabricationsequence for a pn-diode.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Interconnection of Integrated Circuit Hierarchy

Figure 28.23 Connections between elements in the hierarchy for integrated circuits.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Two-Level Metal Interconnect Structures

Figure 18.24 (a) Scanning electron microscope (SEM) photograph of a two-level metalinterconnect. Note the varying surface topography. (b) Schematic illustration of a two-level metal interconnect structure. Source: (a) Courtesy of National SemiconductorCorporation. (b) After R. C. Jaeger.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Wire Bonds Connecting Package Leads toDie Bonding Pads

Figure 18.25 (a) SEM photograph of wire bonds connectingpackage leads (left-hand side) to die bonding pads. (b) and (c)Detailed views of (a). Source: Courtesy of Micron Technology, Inc.

(a) (b) (c)

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Thermosonic Welding of Gold Wires

Figure 28.26 Schematic illustration of thermosonic weldingof gold wires from package leads to bonding pads.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

IC Packages

Figure 28.27 Schematic illustration of various IC packages:(a) dual-in-line package (DIP); (b) flat, ceramic package; (c)common surface-mount configurations; (d) ball-grid arrays.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Flip-Chip Technology

Figure 28.28 Illustration of flip-chip technology. Flip-chip package with(a) solder-plated metal balls and pads on the printed circuit board; (b)flux application and placement; (c) reflow soldering; (d) encapsulation.

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid.ISBN 0-13-148965-8. © 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

Circuit Board Structures and Features

Figure 28.29 Printed circuit board structures and design features.