chapter 5 fabrication of microelectronic devices

FABRICATION OF MICROELECTRONIC DEVICES

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UNIT 5 : FABRICATION OF MICROELECTRONICDEVICES

5.1 INTRODUCTION

Miniaturized microelectronic circuits are in common use today inwristwatches, portable CD players, cellular phones, home entertainmentsystem, fax machine, artificial hearts, military satellites, automotive fuelinjection and others. Over the past decades, the number of components perintegrated circuits has increased from 2,300 in 1971 to 42 million in 2001,while the number of calculations per second has increased 100,000 times,from 10,000 to over a billion. The key to this progress has been developmentof large-batch-size, semi-conductor processing methods coupled withminiaturization of electrical components and connectors.

Although semiconducting materials have been used in electronics since theearly decades of this century, it was the invention of the transistor in 1948 thatset would become one of the greatest technological advancements of allhistory.

Microelectronics have played an ever-increasing role in our lives sinceintegrated circuit (IC) technology became the foundation for calculators,wrist watches, home appliances control, information systems,telecommunications, automotive controls, robotics, space travel, militaryweaponry, and personal computers.

Definition of ICAn integrated circuit (IC) is a collection of electronic devices such astransistors, diodes, and resistors that have been fabricated and electricallyintra-connected onto a small flat chip of semiconductor material.

The major advantages of today's lCs are their- Small size : as fabrication technology becomes more advanced, the size

of devices decreases; consequently, more components can be put onto achip (a small piece of semiconducting material on which the circuit isfabricated).

- Cost : mass processing and process automation have helped to reducethe cost of each completed circuit. The components fabricated diodes,resistors, and capacitors.

Typical chips produced today have sizes that range from 3 mm X 3 mm tomore than 50mm X 50 mm. In the past, no more than 100 devices could belubricated on a single chip; new technology, however, allows densities therange of 10 million devices per chip. This magnitude of integration has beentermed very large scale integration (VLSI). Some of the most advanced ICsmay contain more than 100 million devices.

Because of the minute scale of microelectronic devices, all fabrication musttake place in an extremely clean environment. Clean rooms are used for thispurpose and are allowed to have a maximum number of 0.5-µm particles per


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cubic foot. Most modem clean rooms are class 1 (one particle per cubic foot)to class 10 (ten particles per cubic foot) facilities. In comparison, thecontamination level in modern hospitals is on the order of 10,000 particles percubic foot.

The current processes used in the fabrication of microelectronic devices andintegrated circuits can be outlined by Figure 5.1.

FIGURE 5.1 General fabrication sequences for integrated circuits.


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5.2 LEARNING OUTCOMES

After completing the unit, students should be able to:1. Define IC.2. Arrange the fabrication sequence of IC.3. Explain silicon, wafer preparation and film deposition process4. Discuss oxidation, lithography, etching, diffusion and ion implantation,

metallization and testing, bonding and packaging and theirs purpose.5. Explain yield and reliability


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5.3 SEMICONDUCTORS AND SILICON

As the name suggests, semiconductor materials have electrical propertiesthat lie between those of conductors and insulators, and exhibit resistivitiesbetween 10-3Ω-cm and 108Ω-cm. Semiconductors have become thefoundation for electronic devices because their electrical properties can bealtered when controlled amounts of selected impurity atoms are added to theircrystal structures. These impurity atoms, also known as dopants, have eitherone more valence electron (n-type or negative dopant) or one less valenceelectron (p-type or positive dopant) than the atoms in the semiconductorlattice.

n – type - donor (extra one valence electron) / group V(phosphorous)

p – type - acceptor (less one valence electron) / group III (boron)

For silicon, which is a group IV element, typical n-type and p-type dopantsinclude phosphorus (group V) and boron (group III), respectively. Theelectrical operation of semiconductor devices can be controlled through thecreation of regions of different doping types and concentrations.

Although the earliest electronic devices were fabricated on germanium,silicon has become the industry standard. The abundance of alternativeforms of silicon is second only to that of oxygen, making it economicallyattractive. Silicon's main advantage over germanium is its large energy gap(1.1 eV) compared to that of germanium (0.66 eV). This energy gap allowssilicon-based devices to operate at temperatures about 150°C higher thandevices fabricated on germanium (about 100°C).

Silicon's important processing advantage is that its oxide (silicon dioxide) isan excellent insulator and can be used for both isolation and passivationpurposes. Conversely, germanium oxide is water soluble and unsuitable forelectronic devices.

However, silicon has some limitations, which have encouraged thedevelopments compound semiconductors, specifically gallium arsenide. Itsmajor advantage over silicon is its ability to emit light, allowing fabrication ofdevices such as lasers and light-emitting diodes (LEDs). It also has a largerenergy gap (1.43 eV) and therefore a higher maximum operating temperature(about 200 °C).

Devices fabricated on gallium arsenide also have much higher operatingspeeds than those fabricated on silicon. Some of gallium arsenide'sdisadvantages include its considerably higher cost, greater processingcomplications, and the difficulty of growing high-quality oxide layers (the needfor which is emphasized throughout this chapter).


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5.4 CRYSTAL GROWING AND WAFER PREPARATION

Silicon occurs naturally in the forms of silicon dioxide and various silicates. Itmust undergo a series of purification steps in order to become the high-quality, defect-free, single-crystal material that is required for semiconductordevice fabrication. The process begins by heating silica and carbon togetherin an electric furnace, which results in a 95% to 98% pure polycrystallinesilicon. This material is converted to an alternative form, commonlytrichlorosilane, which in turn is purified and decomposed in a high-temperature hydrogen atmosphere. The result is extremely high-qualityelectronic-grade silicon (EGS).

The most widely used crystal-growing method in the semiconductor industryis the Czochralski process, illustrated in Figure 5.2, in which a single crystalingot, called a boule, is pulled upward from a pool of molten silicon. The setup includes a furnace, a mechanical apparatus for pulling the

boule, a vacuum system, and supporting controls. The furnace consists of a crucible and heating system contained in a

vacuum chamber. The crucible is supported by a mechanism thatpermits rotation during the crystal-pulling procedure.

Chunks of EGS are placed in the crucible and heated to a temperatureslightly above the melting point of silicon: 1410CC.

Heating is by induction or resistance, the latter being used for largemelt sizes.

The molten silicon is doped (Table 5.1) prior to boule pulling to makethe crystal either p-type or n-type.

To initiate crystal growing, a seed crystal of silicon is dipped into themolten pool and then withdrawn upward under carefully controlledconditions.

At first the pulling rate (vertical velocity of the pulling apparatus) isrelatively rapid; this causes a single crystal of silicon to solidify againstthe seed, forming a thin neck.

The velocity is then reduced, causing the neck to grow into the desiredlarger diameter of the boule while maintaining its single crystalstructure.

In addition to pulling rate, rotation of the crucible and other processparameters are used to control boule size.

Single-crystal ingots of diameter = 200 mm or greater and up to 3 mlong are commonly produced for subsequent fabrication ofmicroelectronic chips.

It is important to avoid contamination of the silicon during crystal growing,since contaminants, even in small amounts, can dramatically alter theelectrical properties of Si. To minimize unwanted reactions with silicon andthe introduction of contaminants at the elevated temperatures of crystalgrowing, the procedure is carried out either in an inert gas (argon or helium)or a vacuum. Choice of crucible material is also important; fused silica (SiO2),although not perfect for the application, represents the best available materialand is used almost exclusively. Gradual dissolution of the crucible introducesoxygen as an unintentional impurity in the silicon boule. Unfortunately, thelevel of oxygen in the melt increases during the process, leading to a variation


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in concentration of the impurity throughout the length and diameter of theingot.

FIGURE 5.2 The Czochralski process for growing single-crystal ingots of silicon: (a)initial setup prior to start of crystal pulling, and (b) during crystal pulling to form theboule.

Next, the crystal is sliced into individual wafers by using an inner diameterblade.In this method a rotating blade with its cutting edge on the inner ring isutilized. While the substrate depth needed for most electronic devices is nomore than several microns, wafers are typically cut to a thickness of about 0.5mm. This thickness provides the necessary physical support for theabsorption of temperature variations, and the mechanical support neededduring subsequent fabrication. Finally, the waters must be polished andcleaned to remove surface damage caused by the sawing process.

FIGURE 5.3 Grinding operations used in shaping the silicon ingot: (a) aform of cylindrical grinding provides diameter and roundness control, and(b) a flat ground on the cylinder.


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Fabrication takes place over the entire wafer surface, and many identicalcircuits are generated at the same time. Because of decreasing device sizesand larger wafer diameters, thousands of individual circuits can be put on onewafer. Once processing is finished, the wafer is sliced into individual chips,each containing one complete integrated circuit.

FIGURE 5.4 Wafer slicing using a diamond abrasive cut-off saw.

FIGURE 5.5 Two of the steps in wafer preparation: (a)contour grinding to round the wafer rim, and (b) surfacepolishing


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Summarizing the preceding discussion, the production of silicon-basedintegrated circuits consists of the following stages, portrayed in Figure 5.6:(1) Silicon processing, in which sand is reduced to very pure silicon and

then shaped into wafers;(2) IC fabrication, consisting of multiple processing steps that add, alter,

and remove thin layers in selected regions to form the electronicdevices; lithography is used to define the regions to be processed onthe surface of the wafer; and

(3) IC packaging, in which the wafer is tested, cut into individual dies (ICchips), and the dies are encapsulated in an appropriate package.

FIGURE 5.6 Sequence of processing steps in the production of integrated circuits:(1) pure silicon is formed from the molten state into an ingot and then sliced intowafers; (2) fabrication of integrated circuits on the wafer surface; and (3) wafer is cutinto chips and packaged


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5.5 FILM DEPOSITION

Films of many different types, particularly insulating and conducting films, areused extensively in microelectronic device processing. Common depositingfilms include polysilicon, silicon nitride, silicon dioxide, tungsten, titanium, andaluminum. In some instances, the wafers serve merely as a mechanicalsupport on which custom epitaxial layers are grown. Epitaxy is defined as thegrowth of a vapor deposit or electrodeposit in which the crystal orientation ofthe deposit is directly related to the crystal orientation in the underlyingcrystalline substrate. The advantages of processing on these deposited films,instead of on the actual wafer surface, include fewer impurities (notablycarbon and oxygen), improved device performance, and the tailoring ofmaterial properties, which cannot be done on the wafers themselves.

Some of the major functions of deposited films are masking, for diffusion orimplants, and protection of the semiconductor surface. In maskingapplications, the film must effectively inhibit the passage of dopants andconcurrently display an ability to be etched into patterns of high resolution.Upon completion of device fabrication, films are applied to protect theunderlying circuitry. Films used for masking and protection include silicondioxide, phosphosilicate glass (PSG), and silicon nitride. Each of thesematerials has distinct advantages, and they are often used in combination.

Other films contain dopant impurities and are used as doping sources for theunderlying substrate. Conductive films are used primarily for deviceinterconnection. These films must have a low resistivity, be capable ofcarrying large currents, and be suitable for connection to terminal packagingleads with wire bonds. Generally, aluminum and copper are used for thispurpose. Increasing circuit complexity has required up to six levels ofconductive layers, which must all be separated by insulating films.

Films may be deposited using a number of techniques, which involve avariety of pressures, temperatures, and vacuum systems, as described here:

a. One of the simplest and oldest methods is evaporation, which is usedprimarily for depositing metal films. In this process the metal is heatedto its point of vaporization in a vacuum. Upon evaporation, the metalforms a thin layer on the substrate surface. The heat for evaporation isusually generated by a heating filament or electron beam.

b. Another method of metal deposition is sputtering and entailsbombarding a target with high-energy ions, usually argon (Ar+), in avacuum. Sputtering systems usually include a dc power source toobtain the energized ions. As the ions impinge on the target, atomsare knocked off and subsequently deposited on wafers mounted withinthe system. Although some argon may be trapped within the film, thistechnique results in very uniform coverage. Advances in this fieldinclude using a radio-frequency power source (RF sputtering) andintroducing magnetic fields (magnetron sputtering).


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c. In one of the most common techniques, chemical vapor deposition(CVD), film depositing is achieved by way of the reaction and/ordecomposition of gaseous compounds. Using this technique, silicondioxide is routinely deposited by the oxidation of silane or achlorosilane. Figure 5.7a shows a continuous CVD reactor thatoperates at atmospheric pressure.

FIGURE 5.7 Schematic diagrams of (a) continuous, atmospheric-pressure CVDreactor and (b) low-pressure CVD. Source: S. M. Sze.

A similar method that operates at lower pressures, referred to as low-pressure chemical vapor deposition (LPCVD), is shown in Figure 5.7b.Capable of coating hundreds of wafers at a time, this method results in amuch higher production rate than that of atmospheric-pressure CVD, andprovides superior film uniformity with less consumption of carrier gases. Thistechnique is commonly used for depositing polysilicon, silicon nitride, andsilicon dioxide.

d. Plasma-enhanced chemical vapor deposition (PECVD) involvesthe process of wafers in an RF plasma containing the source gases.This method has the advantage of maintaining low wafer temperatureduring deposition.

Silicon epitaxy layers, in which the crystalline layer is formed using thesubstrate as a seed crystal can be grown using a variety of methods. If thesilicon is deposited from the gaseous phase, the process is known as vapor-phase epitaxy (VPE). In another variation, the heated substrate is broughtinto contact with a liquid solution containing the material to be deposited(liquid-phase epitaxy, or LPE).

Another high-vacuum process utilizes evaporation to produce a thermal beamof molecules that are deposited on the heated substrate. This process, calledmolecular beam epitaxy (MBE), results in a very high degree of purity. Inaddition, since the films are grown one atomic layer at a time, it is possible tohave excellent control over doping profiles. This level of control is especiallyimportant in gallium arsenide technology. Unfortunately, MBE suffers fromrelatively low growth rates compared to other conventional film-depositiontechniques.


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5.6 OXIDATION

Recall that the term oxidation refers to the growth of an oxide layer as a resultof the reaction of oxygen with the substrate material. Oxide films can also beformed using the previously described deposition techniques. The thermallygrown oxides described in this section display a higher level of purity thandeposited oxides because they are grown directly from the high-qualitysubstrate. However, deposition methods must be used if the composition ofthe desired film is different from that of the substrate material.

Silicon dioxide is the most widely used oxide in IC technology today, and itsexcellent characteristics are one of the major reasons for the widespread useof silicon. Aside from its effectiveness in dopant masking and device isolation,silicon dioxide's most critical role is that of the "gate oxide" material.

Silicon surfaces have an extremely high affinity for oxygen, and a freshlysawed slice of silicon will quickly grow a native oxide of 30 Å- 40 Å. ModernIC technologies requires oxide thicknesses from the tens to the thousands ofangstroms.

a. Dry oxidation is a relatively simple process and is accomplished byelevating the substrate temperature typically to 750 °C-1100 °C, in anoxygen-rich environment.

As a layer of oxide forms, the oxidizing agents must be able to pass throughthe oxide and reach the silicon surface where the actual reaction takes place.Thus, an oxide layer does not continue to grow on top of itself, but rather itgrows from the silicon surface outward. Some of the silicon substrate isconsumed in the oxidation process (Figure 5.8).

FIGURE 5.8 Growth of silicon dioxide, showing consumption ofsilicon. Source: S. M. Sze.

The ratio of oxide thickness to amount of silicon consumed is found to be1:0.44. Therefore, to obtain an oxide layer 1000 A thick, roughly 440 A ofsilicon will be consumed. This does not present a problem, as substrates arealways grown sufficiently thick.

One important effect of this consumption of silicon is the rearrangement ofdopants in the substrate near the interface. As different impurities have


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different segregation coefficients in silicon dioxide, some dopants depleteaway from the oxide interface while others pile up. Hence, processingparameters must be adjusted to compensate for this effect.

b. Another oxidizing technique utilizes a water-vapor atmosphere as theagent and is called, appropriately, wet oxidation. This method affectsa considerably higher growth rate than that of dry oxidation, but itsuffers from a lower oxide density and therefore a lower dielectricstrength. Common practice is to combine both dry and wet oxidationmethods, growing an oxide in a three-part layer: dry, wet, dry. Thisapproach combines the advantages of wet oxidation's much highergrowth rate and dry oxidation's high quality.

c. These oxidation methods are useful primarily for coating the entiresilicon surface with oxide, but it can also be necessary to oxidize onlycertain portions of the substrate surface. The procedure of oxidizingonly certain areas is termed selective oxidation and uses siliconnitride, which inhibits the passage of oxygen and water vapor. Thus,through the masking of certain areas with silicon nitride, the siliconunder these areas remains unaffected but the uncovered areas areoxidized.

5.7 LITHOGRAPHY

Lithography is the process by which the geometric patterns that definedevices are transferred from a reticle to the substrate surface. In currentpractice, the lithographic process is applied to each microelectronic circuitmany times, each time using a different reticle to define the different areas ofthe working devices. Typically designed at several thousand times their finalsize, reticle patterns go through a series of reductions before being appliedpermanently to a defect-free quartz plate.

Computer-aided design (CAD) has had a major impact on reticle design andgeneration. Cleanliness is especially important in lithography, and manymanufacturers are now using robotics and specialized wafer-handlingapparatus in order to minimize dust and dirt contamination.

Once the film deposition process is completed and the desired reticle patternshave been generated, the wafer is cleaned and coated with an organicphotoresist (PR), which is sensitive to ultraviolet (UV) light. Photoresistlayers of 0.5 µm-2.5 µm thick are obtained by applying the PR to thesubstrate in liquid form and then spinning it at several thousand rpm for 30 or60 seconds to give uniform coverage.

The next step in lithography is prebaking the wafer to remove the solventfrom the PR and harden it. This step is carried out on a hot plate that hasbeen heated to around 100 °C. The wafer is then aligned under the desiredreticle in a "stepper". In this crucial step, called registration, the reticle mustbe aligned correctly with the previous layer on the wafer. Once the reticle isaligned, it is stepped across the wafer and subjected to UV radiation. Upon


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development and removal of the exposed PR, a duplicate of the reticlepattern will appear in the PR layer.

As can be seen in Figure 5.9, the reticle can be a negative or a positiveimage of the desired pattern. A positive reticle uses the UV radiation to breakdown the chains in the organic film, so that these films are preferentiallyremoved by the developer. Positive masking has become dominant becauseit complements dry etching.

FIGURE 5.9 Pattern transfer by lithography. Note that the mask in stepthree can be a positive or negative image of the pattern. Source: After W. C.Till and J. T. Luxon.

Following the exposure and development sequence, the wafer is post bakedto toughen and improve the adhesion of the remaining resist. In addition, adeep UV treatment (baking the wafer to 150°C-200°C in ultraviolet light) canbe used to further strengthen the resist against high-energy implants and dryetches. The underlying film not covered by the PR is then etched away orimplanted. Finally, the PR is stripped, by exposure to oxygen plasma (Figure5.9). The lithography process is sometimes repeated as many as 25 times inthe fabrication of the most advanced ICs.

One of the major issues in the area of lithography is linewidth, which refersto the width of the smallest feature unprintable on the silicon surface. Ascircuit densities have escalated over the years, device sizes and featureshave become smaller and smaller. Today, minimum commercially feasiblelinewidths are between 0.15 µm and 0.25 µm, with considerable researchbeing done in regard to smaller linewidths of 0.12 µm.

As pattern resolution and device miniaturization have been limited by thewavelength of the radiation source used, the need has arisen to move towavelengths shorter than those in the ultraviolet range, such as "deep" UVwavelengths, electron beams, and x-rays. In these technologies, thephotoresist is replaced by a similar resist that is sensitive to a specific rangeof shorter wavelengths.


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5.8 ETCHING

Etching is the process by which entire films or particular sections of films areremoved and it plays an important role in the fabrication sequence. One of themost important criteria in this process is selectivity, which refers to the abilityto etch one material without etching another.

In silicon technology, an etching process must effectively etch the silicondioxide layer with minimal removal of the underlying silicon or the resistmaterial. In addition, polysilicon and metals must be etched into high-resolution lines with vertical wall profile and with minimal removal of theunderlying insulating film or photoresist. Typical etch rates range fromhundreds to several thousands of angstroms per minute, and selectivities(defined as the ratio of the etch rates of the two films) can range from 1:1 to100:1.

An older etching method requires the wafers to be immersed in a liquidsolution (wet etching). If silicon dioxide is to be etched, this solution usuallycontains hydrofluoric acid, which etches silicon very slowly. The maindrawback of this etching technique is that it is isotropic, meaning that theetch occurs equally in all directions. This condition leads to undercutting(Figure 5.10a), which in turn prohibits the transfer of very high resolutionpatterns.

FIGURE 5.10 Etching profiles resulting from (a) isotropic wet etching and(b) anisotropic dry etching. Source: R. C. Jaeger.

Modern ICs are processed using, exclusively, dry etching which involves theuse of chemical reactants in a low-pressure system. In contrast to the wetprocess, dry etching allows for a high degree of directionality, resulting inhighly anisotropic etch profiles (Figure 5.10b). Also, the dry process requiresonly small amounts of reactant gases, whereas the aqueous solutions used inthe wet process need to be refreshed periodically.

The most widely used dry-etching techniques include(a) sputter etching, which removes material by bombarding it with noble

gas ions, usually Ar+, and(b) plasma etching, which utilizes a gaseous plasma of chlorine or

fluorine ions generated by RF excitation.(c) Reactive ion etching combines these two processes, using both

momentum transfer and chemical reaction to remove material.


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5.9 DIFFUSION AND ION IMPLANTATION

We should mention again that the electrical operation of microelectronicdevices depends on regions that have different doping types andconcentrations. The electrical character of these regions is altered throughthe introduction of dopants into the substrate, which is accomplished by thediffusion and ion implantation processes. This step in the fabrication se-quence is repeated several times, since many different regions ofmicroelectronic devices must be defined.

In the diffusion process, the movement of atoms is a result of thermalexcitation. Dopants can be introduced to the substrate surface in the form ofa deposited film, or the substrate can be placed in a vapor containing thedopant source. The process takes place at elevated temperature, usually800°C - 1200°C. Dopant movement within the substrate is strictly a functionof temperature, time, and the diffusion coefficient (or diffusivity) of the dopantspecies, as well as the type and quality of the substrate material.

Because of the nature of diffusion, the dopant concentration is very high atthe substrate surface and away from the surface, drops off sharply. To obtaina more uniform concentration within the substrate, the wafer is heated furtherto drive in the dopants in a process called drive-in diffusion. Diffusion,desired or undesired will always occur at high temperatures; this fact isalways taken into account during subsequent processing steps. Although thediffusion process is relatively inexpensive, it is highly isotropic.

FIGURE 5.11 Apparatus for ion implantation.

Ion implantation is a much more extensive process and requires specializedequipment (Figure 5.11). Implantation is accomplished by accelerating theions through a high-voltage field of as much as one million electron-volts andthen choosing the desired dopant by means of a mass separator. In a mannersimilar to that of cathode-ray tubes, the beam is swept across the wafer bysets of deflection plates, thus ensuring uniform coverage of the substrate. Thecomplete implantation system must be operated in a vacuum.

The high-velocity impact of ions on the silicon surface damages the latticestructure and results in lower electron mobilities. This condition is


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undesirable, but the damage can be repaired by an annealing step, whichinvolves heating the substrate to relatively low temperatures, usually 400°C-800°C for 15-30 minutes. This provides the energy that the silicon latticeneeds to rearrange and mend itself.

Another important function of annealing is driving in the implanted dopants.Implantation alone imbeds the dopants less than half a micron below thesilicon surface; the annealing step enables the dopants to diffuse to a moredesirable depth of a few microns.


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5.10 METALLIZATION AND TESTING

The preceding sections focused only on device fabrication. However,generating a complete and functional integrated circuit requires these devicesto be interconnected. Interconnections are made by metals that exhibit lowelectrical resistance and good adhesion to dielectric insulator surfaces.Aluminum and aluminum-copper alloys remain the most commonly usedmaterials for this purpose in VLSI technology today.

However, as device dimensions continue to shrink, electromigration hasbecome more of a concern with aluminum interconnects. Electromigration isthe process by which aluminum atoms are physically moved by the impact ofdrifting electrons under high current conditions. In extreme cases, this canlead to severed and/or shorted metal lines. Solutions to the electromigrationproblem include

(a) the addition of sandwiched metal layers such as tungsten andtitanium, and more recently,

(b) the usage of pure copper, which displays lower resistivity andsignificantly better electromigration performance thanaluminum.

Metals are deposited using standard deposition techniques, andinterconnection patterns are generated through lithographic and etchingprocesses as previously described. Modern ICs typically have one to sixlayers of metallization, in which case each layer of metal is insulated by adielectric.

Planarization (producing a planar surface) of these inter-layer dielectrics iscritical in the reduction of metal shorts and of the linewidth variation of theinterconnect. A common method used to achieve a planar surface is auniform oxide etches process that smoothens out the "peaks" and "valleys" ofthe dielectric layer.


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Example 5.1 : Processing of a p-Type Region in n-Type Silicon.

Assume that we wish to create a p-type region within a sample of n-type silicon.Draw cross-sections of the sample at each processing step in order to accomplishthis. (See Figure 5.12)

Solution: This simple device is known as a pn junction diode, and the physics of itsoperation are the foundation for most semiconductor devices.

FIGURE 5.12 Processing of a p-Type Region in n-Type Silicon


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However, today's standard for planarizing high density interconnects and hasquickly become chemical mechanical polishing (CMP). This process entailsphysically polishing the wafer surface in as manner similar to that by which adisc or belt sander flattens the ridges in a piece of wood. A typical CMPprocess combines an abrasive medium with a polishing compound, or slurry,and can polish a wafer to within 300 angstroms of being perfectly flat.

Layers of metal are connected together by vias; access to the devices on thesubstrate is achieved through contacts (Figure 5.13).

(a) (b)

FIGURE 5.13 (a) Scanning electron microscope photograph of a two-levelmetal interconnect. Note the varying surface topography. Source: NationalSemiconductor Corporation, (b) Schematic drawing of a two-level metalinterconnect structure. Source: R. C. Jaeger.

In recent years, as devices have become smaller and faster, the size andspeed of some chips have become limited by the metallization itself.

Wafer processing is complete upon application of a passivation layer, usuallysilicon nitride (Si3N4). The silicon nitride acts as an ion barrier for sodium ionsand also provides excellent scratch resistance.

The next step is to test each of the individual circuits on the wafer. Each chip,also known as a die, is tested by a computer-controlled probe platform thatcontains needlelike probes which access the bonding pads on the die. Theplatform steps across the wafer, and tests whether each circuit functionsproperly with computer-generated timing waveforms. If a defective chip isencountered, it is marked with a drop of ink.

After this wafer-level testing is complete, each die is separated from thewafer. Diamond sawing is a commonly-used separation technique and resultsin very straight edges, with minimal chipping and cracking damage. The chipsare then sorted; the functional dies are sent on for packaging, and the inkeddies are discarded.


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5.11 BONDING AND PACKAGING

The working dice must be attached to a more rugged foundation to ensurereliability. One simple method is to fasten a die to its packaging material withan epoxy cement. Another method makes use of a eutectic bond, which ismade by heating metal-alloy systems. One widely used mixture is 96.4% goldand 3.6% silicon, and has a eutectic point at 370 °C.

Once the chip has been attached to its substrate, it must be electricallyconnected to the package leads. This is accomplished by wire-bonding verythin (25 µm diameter) gold wires from the package leads to bonding padslocated around the perimeter or down the center of the die (Figure 5.14 a).

FIGURE 5.14 (a) SEM photograph of wire bonds connecting package leads (left-hand side) to die bonding pads, (b) and (c) Detailed views of (a). Source: Courtesyof Micron Technology, Inc.

The bonding pads on the die are typically drawn at 75 µm -100 µm per side,and the bond wires are attached using thermocompression, ultrasonic, orthermosonic techniques (Figures 5.14 b and c).

The connected circuit is now ready for final packaging. The packagingprocess largely determines the overall cost of each completed IC, since thecircuits are mass produced on the wafer but then packaged individually.Packages are available in a variety of styles; the appropriate one must reflectoperating requirements.

Consideration of a circuit's package includes chip size, number of externalleads, operating environment, heat dissipation, and power requirements. Forexample, ICs that are used for military and industrial applications requirepackages of particularly high strength, toughness, and temperatureresistance.

An older style of packaging is the dual-in-line package (DIP), shownschematically in Figure 5.15a. Characterized by low cost and ease ofhandling, DIP packages are made of thermoplastic, epoxy, or ceramic andcan have from 2 to 500 external leads. Ceramic packages are designed foruse over a broader temperature range and in high-reliability and militaryapplications, thus costing considerably more than plastic packages.


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Figure 5.15b shows a flat ceramic package in which the package and all theleads are in the same plane. This package style does not offer the ease ofhandling or the modular design of the DIP package. For this reason, it isusually permanently affixed to a multiple-level circuit board in which the lowprofile of the flat pack is necessary.

FIGURE 5.15 Schematic illustrations of different IC packages: (a) dual-in-line (DIP), and (b) ceramic flat pack, and (c) common surface mountconfiguration. Sources: R. C. Jaeger and A. B. Glaser; G. E. Subak-Sharpe.

Surface mount packages have become the standard for today's integratedcircuits. As can be seen in Figure 5.15, the main difference in the designs isin the shape of the connectors.

The DIP connection to the surface board is via prongs which are inserted intocorresponding holes, while a surface mount is soldered onto speciallyfabricated pad or land designs. A land is a raised solder platform forcomponent interconnections in a printed circuit board. Package size andlayouts are selected from standard patterns, and usually require adhesivebonding of the package to the board, followed by wave soldering of theconnections.

After the chip has been sealed in the package, it undergoes final testing.Because one of the main purposes of packaging is isolation from theenvironment, testing at this stage usually involves heat, humidity, mechanicalshock, corrosion, and vibration. Destructive tests are also performed toinvestigate the effectiveness of sealing.


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5.12 SUMMARY

In this unit we have studied that1. The microelectronics industry is developing rapidly. The possibilities

for new deviceconcepts and circuit designs appear to be endless. Thefabrication of microelectronic devices and integrated circuits involvesmany different types of processes, most of which have been adaptedfrom those of other fields of manufacturing.

2. After bare wafer have been prepared, they undergo repeatedoxidation or film deposition, lithographic, and etching step to openwindows in the oxide layer in order to access the silicon substrate.

3. After each of these processing cycles is complete, dopants areintroduced into various regions of the silicon structure throughdiffusion and ion implantation.

4. After all doping regions have been established, devices areinterconnected by multiple metal layers, and the completed circuit ispackaged and made accessible through electrical connections.

5. Finally, the packaged circuit and other discrete devices are solderedto a printed circuit board for final installation.

5.13 SELF TEST

1. Define IC2. What are dopants?3. Arrange the fabrication sequence of IC4. Explain the three main stages in production of silicon-based integrated

circuits.5. State three types of oxidation.6. What is lithography?7. What is etching?8. Distinguish diffusion and ion implantation.9. Compare silicon, germanium and gallium arsenide.10. Define electromigration.

5.14 KEY TERM

Integrated CircuitPlanarizationMetallization


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5.15 REFERENCES

Serope Kalpakjian, Steven R. Schmidt (2001). Manufacturing Engineeringand Technology, (4th Edition), state: Prentice Hall.

Mikell P. Groover (2002). Fundamentals of Modern Manufacturing Materials,Processes, and Systems, (2nd Edition), state: John Wiley & Son, Inc.

John A. Schey, (year). Introduction to Manufacturing Processes, (3rd Edition),state: Mc Graw Hill.

E. Paul Degarmo, J T. Black, Ronald A. Kohser (2003). Materials andProcesses in Manufacturing, (9th Edition), state: John Wiley & Son, Inc.


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5.16 ANSWER

1. Define ICAn integrated circuit (IC) is a collection of electronic devicessuch as transistors, diodes, and resistors that have beenfabricated and electrically intra-connected onto a small flat chipof semiconductor material.

2. What are dopants?Dopants are impurity atoms, have either one more valenceelectron (n-type or negative dopant) or one less valence electron(p-type or positive dopant) than the atoms in the semiconductorlattice.n – type - donor (extra one valence electron) / group V

(phosphorous)p – type - acceptor (less one valence electron) / group III

(boron)

3. Arrange the fabrication sequence of IC


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4. Explain the three main stages in production of silicon-based integratedcircuits.The production of silicon-based integrated circuits consists ofthe following stages:(1) Silicon processing, in which sand is reduced to very pure

silicon and then shaped into wafers;(2) IC fabrication, consisting of multiple processing steps that

add, alter, and remove thin layers in selected regions toform the electronic devices; lithography is used to definethe regions to be processed on the surface of the wafer;and

(3) IC packaging, in which the wafer is tested, cut intoindividual dies (IC chips), and the dies are encapsulated inan appropriate package.

2. State three types of oxidation. Dry oxidation Wet oxidation Selective oxidation

3. What is lithography?Lithography is the process by which the geometric patterns thatdefine devices are transferred from a reticle to the substratesurface.

4. What is etching?Etching is the process by which entire films or particularsections of films are removed and it plays an important role inthe fabrication sequence.

5. Distinguish diffusion and ion implantation.In the diffusion process, the movement of atoms is a result ofthermal excitation. Dopants can be introduced to the substratesurface in the form of a deposited film, or the substrate can beplaced in a vapor containing the dopant source. The processtakes place at elevated temperature, usually 800°C - 1200°C.Dopant movement within the substrate is strictly a function oftemperature, time, and the diffusion coefficient (or diffusivity) ofthe dopant species, as well as the type and quality of thesubstrate material.

Ion implantation is a much more extensive process and requiresspecialized equipment. Implantation is accomplished byaccelerating the ions through a high-voltage field of as much asone million electron-volts and then choosing the desired dopantby means of a mass separator. In a manner similar to that ofcathode-ray tubes, the beam is swept across the wafer by sets ofdeflection plates, thus ensuring uniform coverage of thesubstrate. The complete implantation system must be operatedin a vacuum.


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The high-velocity impact of ions on the silicon surface damagesthe lattice structure and results in lower electron mobilities. Thiscondition is undesirable, but the damage can be repaired by anannealing step, which involves heating the substrate to relativelylow temperatures, usually 400°C-800°C for 15-30 minutes. Thisprovides the energy that the silicon lattice needs to rearrangeand mend itself.

9. Compare silicon, germanium and gallium arsenide.Although the earliest electronic devices were fabricated ongermanium, silicon has become the industry standard. Theabundance of alternative forms of silicon is second only to thatof oxygen, making it economically attractive. Silicon's mainadvantage over germanium is its large energy gap (1.1 eV)compared to that of germanium (0.66 eV). This energy gap allowssilicon-based devices to operate at temperatures about 150 °Chigher than devices fabricated on germanium (about 100 °C).

Silicon's important processing advantage is that its oxide (silicondioxide) is an excellent insulator and can be used for bothisolation and passivation purposes. Conversely, germaniumoxide is water soluble and unsuitable for electronic devices.

However, silicon has some limitations, which have encouragedthe developments compound semiconductors, specificallygallium arsenide. Its major advantage over silicon is its ability toemit light, allowing fabrication of devices such as lasers andlight-emitting diodes (LEDs). It also has a larger energy gap (1.43eV) and therefore a higher maximum operating temperature(about 200 °C).

Devices fabricated on gallium arsenide also have much higheroperating speeds than those fabricated on silicon. Some ofgallium arsenide's disadvantages include its considerably highercost, greater processing complications, and the difficulty ofgrowing high-quality oxide layers.

10. Define electromigration.Electromigration is the process by which aluminum atoms arephysically moved by the impact of drifting electrons under highcurrent conditions.

chapter 5 fabrication of microelectronic devices

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