thermal management in microelectronic devices and interfaces

Zurich Research Laboratory

Advanced Thermal Packaging

© IBM Research 2010

Thermal Management in

Microelectronic Devices and InterfacesW. Escher, J. Goicochea, G.I. Meijer, and B. Michel, Advanced Thermal Packaging, IBM Research GmbH, Säumerstrasse 4, 8803 Rüschlikon, Switzerland, [email protected]

IBM Zurich Research Laboratory | Mar 22, 2011 © IBM Research 2010

2


Overview

Green Datacenter market drivers and trends- Inefficient air cooled data centers: Waste of energy and exergy- Role of IT to tackle climate change: Economic and political interest- Efficiency roadmap of transistors and packaging

Energy re-use in hot water cooled data centers- Reduction of carbon footprint with community heating- Joint project with ETH: Aquasar

Key components enabling efficiency and energy re-use- Improved thermal conductivity, reduced bondline- Improved heat transfer with micro and nanotechnology - Minimized exergy losses with water and hotspot cooling - Future interlayer cooling of 3D stacked chips- Computer efficiency is dominated by communication

Phonon Transport Engineering- Improved nanoscale heat transfer from nano to macro- Chemical surface functionalization- Geometrical patterning for phonon resonance matching- Long-term research: Modeling and experiment needed


3


Green Datacenter Drivers and Trends

Increased green consciousness, and rising cost of power

IT demand outpaces technology improvements - Server energy use doubled 2003-2008;

temporary slowdown due to economic crisis resume of power growth is not sustainable

- Koomey Study: Server use 1.2% of U.S. energy

ICT industries consume 2% world wide energy- Carbon dioxide emission like global aviation

Real Actions Needed

Brouillard, APC, 2006Future datacenters dominated by energy cost;

half energy spent on coolingSource IDC, 2009


4


From the Transistor to the Globe

100

kmD

ay

5’00

0 km

Yea

r

40’0

00 k

m10

0 ye

ars

Morteratsch Glacier, Switzerland, 1985

Morteratsch Glacier, Switzerland, 2007

Glacier recession 1985-2007: 400 meters!

Pow

er

Sta

tion

Co

nti

nent

alP

ower

Net

s

Glo

bal

T

emp

erat

ure

- Thermal issues propagate up to the world climate

- Global length- and decade time-scales involved

- A holistic view is required to solve these problems

IT to become part of the solution to climate challenge!


5


High-performance chip-level cooling improves energy efficiency AND reduces carbon emission:- Cool chip with ∆T = 20ºC instead of 75ºC- Save chiller energy: Cool withT > 60ºC hot water - Re-use: Heat 700 homes with 10 MW datacenter

Need for carbon footprint reduction - EU, IPCC, Stern report targets- Chillers use ~50% of datacenter energy - Space heating ~30% of carbon footprint

Zero-emission concept valuable in all climates- Cold climates: energy savings and energy re-use - Hot climates: Free cooling, desalination

Europe: 5000 district heating systems- Distribute 6% of total thermal demand- Thermal energy from datacenters absorbed

Zero-Emission Data Centers

T. Brunschwiler, B. Smith, E. Ruetsche, and B. Michel, “Toward zero-emission datacenters through direct reuse of thermal energy”, IBM JRD 53(3), paper 11.

>35 kW racks need water cooling Inlet >60ºC

Outlet >65ºC

Water cools the chip through micro-channels or micro-jets

Heat exchanger for transfer to district heating

Floor heating


6


First Prototype at IBM Rüschlikon

Reduce cooling energy by water cooling- Cooling the chip with “hot” water (60°C)- Free cooling: no energy-intensive chillers needed

Reuse heat for remote heating - Re-uses 75% of blade energy - Recyclable 60°C heat

Prototype- Same power for air and 60°C “hot”

liquid cooled version- Large fan power reduction

G.I. Meijer, T. Brunschwiler, S. Paredes, and B. Michel, using Waste Heat from Data Centres, to Minimize Carbon Dioxide Emission, ERCIM News 79, 23-24 (2009).

G. I. Meijer, Cooling Energy-Hungry Data Centers, Science 328, 318-319 (2010).

Direct attached / integrated micro-channel cold plate with one interface

Experimental validation: Inlet temperatures up to 60°C / 140 F


7


Connection to ETHheating system

Aquasar Rack

Aquasar Hot-Water Cooled HPC Cluster for ETH

Liquid-cooled Blade Center ChassisTarget Reach world record in performance (MFlops/W)

and low emission (MFlop/gCO2) Reduce energy cost by a factor two Lead standardization for future datacenters PUEreuse less than 1

Technical Details 33 QS22 and 9 HS22

IBM BladeCenter® Servers Two chassis liquid cooled and one air cooled Infiniband communication equipment and

a storage server Closed cooling loop with 20 liters of water The coolant flow in rack is 30 liters per minute


8


Aquasar Inauguration at ETH May6, 2010

Linpack benchmark executed at 450 MFlop/W

Re-use >80% of BladeCenter energy at 60ºC

Performance evaluation and optimization ongoing as part of CCEM project


9


Value of Heat in Different Climates

Value of heat depends on temperature and target technology- Space heating (blue)- Desalination (green)- Sorption Cooling (red)

Space heating provides large cost reduction in cold climates but not in hot climates- Best in cold climate: Space heating- Best in hot and dry climate: Desalination- Best in hot climate: Sorption cooling

Heating degree days (red) and cooling degree days (blue) for New York a), Seattle b), and Huston c)

PUE and reduction of energy cost in New York, Seattle, and Huston. a) reference (red), direct heat reuse (green), and with cooling (blue). b) Energy cost reduction with heating (green) and cooling (blue); Emission reduction (light green / light blue)

T. Brunschwiler, G.I. Meijer, S. Paredes, W. Escher, and B. Michel, Direct Waste Heat Utilization from Liquid-Cooled Supercomputers, IHTC14-23352 (2010).


10


Motivation for Packaging Research

Scaling beyond 22 nm decreases performance ~30% per generation - Needs to be compensated by new technologies

like high k dielectrics, air gap, multicore

- Will get more difficult with every generation

ITRS reports “Acceleration of pace in assembly and packaging” and extensively revised roadmap in 2008 upgrade

Packaging compensates for slower chip efficiency improvements

2002 2007/08 2010

System PerformanceMoore’s law

Transition from chipto packaging dominateddevelopment 2008

?

Chip scaling3D packaging

Slow down

Packaging investments will save Moore’s law and the electronics industry

Exaflop computers needed for 2018 1000x performance in 11 years

Peta to Exaflop transition:

Transistors may provide 20x efficiency

Packaging has to provide 50x

Tera to Petaflop transition caused a 10x energy waste increase


11


© IBM Research, GmbH Do not distribute11

Why Thermal Packaging?

Performance Electron, hole mobility is increased at lower temperatures Leakage current is exponentially dependent on temperature

Reliability Most failure mechanisms depend exponentially on temperature Catastrophic failure can occur due to thermo-mechanical stress

Typical processor package Thermal interface between chip and lid

TIM up to 50% of system thermal resistance !!!


12


12

Hierarchical Nested Channel Interface

l

pdV H

⋅⋅∆⋅⋅=

ηπ128

4

Squeeze flow theory:

tpwh

⋅⋅=

2

η

2. Evacuation of paste:

Poiseuille flow theory

→ array of punches needed

→ big channels needed

1. Basic Idea: Allow two solid surfaces (Chip and Cooler) to approach in presence of a third medium (TIM) such that the gap is minimal for a given pressure and a given duration

3. Thermal efficiency:

→ small channels needed

High fill factor needed

Hierarchically Nested Channels

COOLER

PASTE

p

ηh

CHIP w

d

+ reduced thermal resistance

+ reduced assembly pressure

+ reduced assembly time


13


Packaging and Thermal Interfaces

Interfaces are large portion of total resistance- Thermal interface materials TIM 1 and TIM 2 cause

almost half the overall thermal resistance in a high performance processor package

Particle filled materials have cost benefit- Easier processing, no metallization,

flexibility for many applications

Conductivity increase with higher particle loading- Viscosity and shear strength also increase- If bondline thickness increases – No Gain!

Assembly loads cannot be too high- C4 crushing, chip cracking- Substrates bend trapping thick TIM

Hierarchical Nested Channel (HNC) createsthinner bondlines withhigher conductivity materials usinglow assembly forces…

TIM1

TIM2

Surface Channels


14


High Performance Thermal Interface Technology

bifurcation lines (flow separation) HNC micro channels

IEEE Harvey Rosten Award for Excellence in Thermal Sciences 2008 R. Linderman, T. Brunschwiler, U. Kloter, H. Toy and B. Michel

Directed self-assembly Fluid-shear driven self-assembly Control of stacking with channel pattern

High performance thermal interface Increased particle density

High performance with matched paste Rth (<5 mm2K/W)

Quick integration into products possible


15


Ongoing: Validation for Electrically Conductive Adhesives (ECAs)Same stacking effects observed

Locally increased electrical conductivity

Application Range & Outlook

Applicability of HNC

TIM1 : 20x20mm chip

TIM2 : 50x50mm lid

“TIM N” : 200x150 mm module

Demonstrated benefits over 100x length scales

Stacking Lines

Optical image


16


16

Large Area Thermal Interfaces

2 bar nominal assembly pressure 5.5 kN

3kW IGBT switch per module

AlSiC base plate w/ HNC after squeeze

200x140mm module, AlSiC Baseplate

Final Gap dependence on Pressure

0

10

20

30

40

50

60

0 0.5 1 1.5 2 2.5 3

Assembly pressure

Fin

al

Gap

FlatHNC L3Power (HNC L3)Power (Flat)

90% BLT reduction

compared to 16.7% for same paste, pressure at TIM1

(bar)

BL

T (

µm

)


17


17

Bondline Thickness and Squeeze Time Reduction

0

20

40

60

80

100

120

140

0 5 10 15 20

Time [min]

BL

T [

µm

]

FlatHNC1

HNC2HNC3

Stabilizes at 29 µm after 6.5 hours

19 µm after 70 min.

Temporal bondline assembly profile for Wacker P12 silicone-based TIM common in power electronics applications. The 14×20 cm interface was assembled with 2 bar pressure.

-5

5

15

25

35

45

0 0.1 0.2 0.3 0.4 0.5

Time (hours)A

ve

rag

e B

LT

(u

m) Flat

HNC2b

HNC2a

Squeeze profile for (unfilled) hi-MW PDMS

Adhesive example: For cure time @ 10 min, only HNC system reaches natural final BLT before being cured

B. Smith, W. Glatz, and B. Michel, Mini- and microchannels in thermal interfaces: spatial, temporal, material, and practical significance, Electronics Cooling, Feb. 2009.


18


18

Filled Pastes

• High fill factor → up to 80%• Small particles resulting in small gap• Low voiding due to paste pumping• Filler: Al2O3, BN, ZnOx • Matrix: silicone oil, epoxy oil

Chip

CapFiller particles

Paste

ATC 3.8 filler particlesdiameter distribution:- average 5µm, max 40 µm

ATC 3.8 after cyclingvoiding due to paste pumping

Particle Interaction limited gap versus volumetric FillPaste: 0-8um Ag particles in PDMS matrix oil

0

10

20

30

40

50

60

70

80

15 25 35 45 55 65 75 85

Volumetric fill of particles [%]

Bo

nd

Lin

e T

hic

knes

s [u

m]

100cSt, Flat

165,000 cSt, Flat

low visc. matrix

high visc. matrix

~2X

bulk conductivity

Large bondline thickness increase at critical loading- Particle stacking

Higher matrix viscosity required for higher particle loading- Large gains in bulk conductivity


19


Motivation for Liquid Cooling

- Increase in heat removal performance: Superior thermal properties of liquids compared to air

- Design flexibility: Sensible heat transport to locations with available space

- Centralized secondary heat exchanger

- Efficient water-water heat exchanger

Limited heat transport due to fin efficiencyLong distance transport possible

Thermal conductivity [W/(m*K)]

Volumetric heat capacity [kJ/(m3*K)]

Air 0.0245 1.27

H2O 0.6 4176

Transport

Primary

Secondary

Disadvantage: Increased complexity


20


Chip Scale Liquid Cooling

A

A’

A-A’

Arrayed jets, distributed return

SEM cross-section of two-level

jet plate with diameter of 35µm

Biological vascular systems are optimized for the mass transport at low pressure

Direct Liquid Jet-Impingement Cooling with Micron-Sized Nozzle Array and Distributed Return Architecture, T. Brunschwiler et al., ITHERM 2006

Cooling of up to 350 W/cm2


21


Ultra Thin High Efficiency Heat Sinks

30

mm

2m

m

Motivation: Find the best coolant and the best structure for ultra-compact heatsinks (thickness < 2 mm)

Nanofluid thermal properties explained by effective medium theory which means they cannot ‘magically’ improve heat transfer

Water provides the best combination of material properties

Flat heatsinks reduce the board pitch of future systems from >30 mm (1U) to 3 mm (1/10 U)

Optimum design provides a total thermal resistance of 0.09 cm2K/W @ V =1.3 l/min, Δp = 0.22 bar

maximum power density > 700 W/cm2 for ΔT = 65 K

Increasing inlet temperature to 70ºC (190 F) enhances the heat sink efficiency >40%


22


Manifold Micro-Channel Heat sink

W. Escher, T. Brunschwiler, B. Michel and D. Poulikakos, ‘Experimental Investigation of an Ultra-thin Manifold Micro-channel Heat Sink for Liquid-Cooled Chips’, ASME Journal of Heat Transfer, 2009.

W. Escher, B. Michel and D. Poulikakos, ‘A novel high performance, ultra thin heat sink for electronics’, International Journal of Heat and Mass Transfer, 2009.


23


Hot Spots are Everywhere

Power map of a dual core microprocessor Temperature map of a data center

Current thermal management infrastructure is over-dimensioned to keep hot spots cool

Improved efficiency: Thermal aware chip and datacenter design reduced hot spot peak heat flux Hot spot adapted cooling architectures minimal pumping power and thermal mixing

Hot spot heat flux 4x higher then mean


24


64 xOff Chip Memory

1 xOff Chip Memory

8 x Off Chip Memory

Multi-Core Architecture: Communication Bandwidth Limit

00.10.20.30.40.50.60.70.80.9

1

64k 256k 1024k 4096k

Misses

Cores share constant off-chip bandwidth Core proportional system performance

demands cubic cache size scaling Total chip area increase

signal delay in wires

lithographic limit reached (~4cm2)

Wilfried Haensch 08

A /1 ≈M

Cache – core balancing at constant off-chip bandwidth Cache miss behavior:

Solution: Vertical integration


25


3D Stacking Roadmap – Through Silicon Vias (TSV)

Through Silicon Via Technologyis key but very expensive to develop


26


Scalable Heat Removal by 3D Interlayer Cooling 3D integration will require interlayer cooling for stacked logic chips

Bonding scheme to isolate electrical interconnects from coolant

Heat removal scales with the number of dies

sealing

electrical

Thermo-

mechanical

Solder functionality

Cool between logical layers with optimal vias- Best performance with 200 μm pin fins

- Through-silicon via height limit, typically 150µm

- Microchannel, pin fins staggered/in line, drop shape

Interlayer cooling of 3D stacked chips- Remove 180 W/cm2 per layer or

- Remove 7.2 KW from 10 layers with 4 cm2

Interlayer cooling with lateral feed manifold

Through silicon via with bonding scheme

Interconnect compatible heat transfer structures

Microchannel Pin fin inline / staggered


27


Electro-Thermal Co-Design

Efficient heat removal Heat transfer structure

Modulation of heat transfer structure

Increase in local hot spot flow rat Fluid focusing

Chip design Heat Transfer Building Blocks Heat Transfer Structure Design

Power map

Electrical interconnects

Power map

Interconnects

Pressure

Flow rate

Fluid

Geometry

Temp. map

Pumping power

Op

tim

izat

ion

Feedback


28


Experimental Validation: Pyramid Chip Stack

Pyramid chip stack

Random power map

Thermal Demonstrator: Three active tiers, cooled with four cavities Polyimide bonding represents wiring levels Multi-scale modeling accuracy validated (+/-10%)

Realistic Product Style Stack: Aligned hot-spot heat flux of 250W/cm2 possible

Interlayer cooled chip stack


29


Phonon Transport Engineering Thermal transport in electronics

Silicon substrate

Gate

Strained Si, Ge, SiGe

Buried oxide

TIM1

TIM2

ElectronHot spot

Optical modesAcoustic modes

Buried oxideSilicon substrate

TIM1Cap

TIM2Heat sink

Ambient

Heat path

Tem

per

atu

re

Interface

Transistor level

Characteristics: Multiscale (from nano to macro) Heat flux crosses multiple interfaces Interface resistances become dominant as characteristic dimension reduces


30


Boltzmann Transport Equation

Fourier Law

Hyperbolic Heat

Equation

Molecular Dynamics

λ Λ

cτ

Λ>rl rlL >>

Spatial characteristic dimension

Temporal characteristic dimension

rτ

rt τ>

rt τ>>

Boltzmann Transport Equation

Fourier Law

Hyperbolic Heat

Equation

Molecular Dynamics

λ Λ

cτ

Λ>rl rlL >>

Spatial characteristic dimension

Temporal characteristic dimension

rτ

rt τ>

rt τ>>

0 2 4 6 8

x 1013

100

102

104

106

Frequency (rad/s)

Mea

n fr

ee p

ath

(nm

)

TALALOTO4.5 5 5.5 6

x 1013

10-1

100

101

102

Phonon Transport Engineering Investigation: Phonon relaxation times in semiconductors (Si, Ge and III-V)

Tunneling of phonons in superlattices (Si-SiO2)

Impact of surface functionalization (chemical and geometrical) on thermal interface resistance TIM performance analysis based on effective medium approximation (EMA) and MD Impact of electron-phonon interactions on thermal performance of TIMs

Phonon relaxation time determination

1012

1013

101410

9

1010

1011

1012

Frequency (rad/s)

1/τ

m,r (

1/s

)

TALALOTO

ba ωωτ *)(/1 =

Ge relaxation rates of and mean free path for acoustic and optical modes

)(/1 ωτMultiscale heat conduction

J.V. Goicochea and B. Michel, Phonon Relaxation Times of Germanium Determined by Molecular Dynamics at 1000 K, SEMITHERM Paper# 151 (2010).


31


Silicon substrate

GateSi

Buried oxide

SiO2

Si

SiO2

Si

SiO2

Si

SiO2

Silicon substrate

Transistor

phonons

Low: σ, moderate: κ

t Si / SiO2

t Si

Silicon substrate

GateSi

Buried oxide

Silicon substrate

GateSi

Buried oxide

SiO2

Si

SiO2

Si

SiO2

Si

SiO2

Silicon substrate

Transistor

phonons

SiO2

Si

SiO2

Si

SiO2

Si

SiO2

Silicon substrate

Transistor

phonons

Low: σ, moderate: κ

t Si / SiO2

t Si

Phonon Transport Engineering Investigation: Phonon relaxation times in semiconductors (Si, Ge and III-V)

Tunneling of phonons in superlattices (Si-SiO2)

Impact of surface functionalization (chemical and geometrical) on thermal interface resistance TIM performance analysis based on effective medium approximation (EMA) and MD Impact of electron-phonon interactions on thermal performance of TIMs

Hot spot mitigation in SOI channel

20 40 60 80 1000

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time step

Ene

rgy

chan

ge

nP=1,nA=20,nB=1,wP=40nP=1,nA=20,nB=2,wP=40nP=1,nA=20,nB=3,wP=40nP=1,nA=20,nB=4,wP=40nP=1,nA=20,nB=8,wP=40

R= 0.4

R= 0.55-0.6

Phonon transmission at Si / SiO2 interface*

T. W

ata

nabe

, et

al.

1999

, “N

ove

l Int

era

tom

icP

ote

ntia

l Ene

rgy

Fu

nctio

n fo

r S

i, O

Mix

ed S

yste

ms.

”Jp

n. J

. A

ppl.

Phy

s. V

ol. 3

8, p

p.L

366

-L36

9.

Si

O

* T

. Wa

tana

be, e

t al

. 19

99,

“No

vel I

nte

rato

mic

Po

tent

ial E

nerg

y F

unc

tion

for

Si,

O M

ixed

Sys

tem

s.”

Jpn

. J.

App

l. P

hys.

Vol

. 38,

pp.

L36

6-L

369.

Si

O

* T. Watanabe, et al. 1999, “Novel Interatomic Potential Energy Function for Si, O Mixed Systems.” Jpn. J. Appl. Phys. Vol. 38, pp.L366-L369.

Si

O

* T. Watanabe, et al. 1999, “Novel Interatomic Potential Energy Function for Si, O Mixed Systems.” Jpn. J. Appl. Phys. Vol. 38, pp.L366-L369.

Si

O

0 0.5 1 1.5 2 2.5 3 3.5 4

x 10-8

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1x 10

-12

z

AB B

m

m

Am

plitu

de

0 0.5 1 1.5 2 2.5 3 3.5 4

x 10-8

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1x 10

-12

z

AB B

m

m

Am

plitu

de Wavepacket

k/kmax=0.5

0 0.5 1 1.5 2 2.5 3 3.5 4

x 10-8

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1x 10

-12

z

AB B

m

m

Am

plitu

de

Wavepacket

k/kmax=0.5


32


Phonon Transport Engineering Silanol: hydrophilicSilane: hydrophobic

Chemical surface functionalization Hydrophobic or hydrophilic interfaces Impact on thermal conductance Applicable to solid-water interfaces

amphiphilic substrate

Si-H Si-OH

neg. flux

pos. flux

positive heat flux

green = hydrophilicred = hydrophobic

cold substrate

hot substrateamphiphilic substrate

Si-H Si-OH

neg. flux

pos. flux

positive heat flux

green = hydrophilicred = hydrophobic

cold substrate

hot substrate

silanolsilane

SiO2

H2O

Si–OHSi–H

SiO2

H2O

Hydrophobic side

Critical conductance

Si/Si grain boundary conductance

Hydrophilic side

Hydrophobic side

Critical conductance

Si/Si grain boundary conductance

Hydrophilic side


33


Phonon Transport Engineering

SAM: -H or OH terminated

Chemical surface functionalization Hydrophobic or hydrophilic interfaces Impact on thermal conductance Applicable to solid-water interfaces

SiO2H2O SAMsSAMs H2O

M. Hu, J.V. Goicochea, B. Michel, and D. Poulikakos, Thermal rectification at water/functionalized silica interfaces, APL 95, 151903 (2009).


34


Geometrical surface functionalization Applicable to any solid-fluid interface

Phonon Transport Engineering M. Hu, J.V.Goicochea, B. Michel, and D. Poulikakos, Surface

Functionalization Mechanisms of Enhancing Heat Transfer at Solid-Liquid Interfaces, IHTC14-22362 (2010).


35


Phonon Transport Engineering Effective medium approximation: Identify key parameters

Study impact of: Particle size, paricle aspect ratio Volume fraction, interface resistance Orientation

EVAC – P13: 3.9-4.19 W/m-K, 82%wt Al NPs + Graphite flakes, d = 5x10-6 m

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

-1

100

101

102

103

20 W/m-K

5.0 W/m-K

~15x

Glycerol + Al spheres

G = 1x103 W/m2K

G = 1x106 W/m2K

G = 1x109 W/m2K d = 10x10-6 m

d = 1x10-6 m

Km = 0.280 W/m-KKp = 238.5 W/m-K

Ke

Volume fraction, f

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

-1

100

101

102

103

20 W/m-K

5.0 W/m-K

20 W/m-K

5.0 W/m-K

~15x~15x

Glycerol + Al spheres

G = 1x103 W/m2K

G = 1x106 W/m2K

G = 1x109 W/m2K d = 10x10-6 m

d = 1x10-6 m

Km = 0.280 W/m-KKp = 238.5 W/m-K

Ke

Volume fraction, f

EVAC – P1: 1.56 W/m-K, 16%wt CNTs rt=133-266

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

-1

100

101

102

103

Glycerol + CNTs (randomly oriented)

Km = 0.280 W/m-KKp = 600 W/m-K

Volume fraction, f

Ke

p = 200 (L/d)L = 20x10-6 m

20 W/m-K

5.0 W/m-K

G = 1x106 W/m2K

G = 1x107 W/m2K

G = 1x109 W/m2K

G = 1x108 W/m2K

EVAC – P1: 1.56 W/m-K, 16%wt CNTs rt=133-266

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

-1

100

101

102

103


Km = 0.280 W/m-KKp = 600 W/m-K

Volume fraction, f

Ke

p = 200 (L/d)L = 20x10-6 m

20 W/m-K

5.0 W/m-K

G = 1x106 W/m2K

G = 1x107 W/m2K

G = 1x109 W/m2K

G = 1x108 W/m2K

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

-1

100

101

102

103


Km = 0.280 W/m-KKp = 600 W/m-K

Volume fraction, f

Ke

p = 200 (L/d)L = 20x10-6 m

20 W/m-K

5.0 W/m-K

20 W/m-K

5.0 W/m-K

G = 1x106 W/m2K

G = 1x107 W/m2K

G = 1x109 W/m2K

G = 1x108 W/m2K

101

102

103

10410

-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4


CNT aspect ratio, p

RBK

Km = 0.280 W/m-KKp = 600 W/m-K

d = 10x10-9 mI = 1.00, Ke

= 0.28 W/m-K

I = 7.14, Ke= 2 W/m-K

I = 17.9, Ke= 5 W/m-K

I = 71.4, Ke= 20 W/m-K

*

101

102

103

10410

-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4


CNT aspect ratio, p

RBK

Km = 0.280 W/m-KKp = 600 W/m-K

d = 10x10-9 mI = 1.00, Ke

= 0.28 W/m-K

I = 7.14, Ke= 2 W/m-K

I = 17.9, Ke= 5 W/m-K

I = 71.4, Ke= 20 W/m-K

*

J.V. Goicochea, W. Escher, X. Tan, and B. Michel, Performance of thermal interface materials: Numerical analysis, to be presented at THERMINIC (2010).


36


Phonon Transport Engineering Effective medium approximation: Filler-matrix thermal interface resistance estimation Impact of particle size, aspect ratio, volume fraction,

interface resistance and orientation

Silicone (PDMS) GlycerolCNT array

60 80 100 120 140 160 180 200 220250

300

350

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450

500

550

600

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700

750

CNT-PDMS

Time (ps)

T (K)

relaxation

heat

ram

p

adiabatic relaxation

CNT

matrix

60 80 100 120 140 160 180 200 220250

300

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CNT-PDMS

Time (ps)

T (K)

relaxation

heat

ram

p

adiabatic relaxation

CNT

matrix

Lump-heat-capacity method

[ ]

−++=x

zxme f

fKK

βββ

3

3

mc

mc

xKK

KK

+−=

11

11 )(2β

Ω+=

d

pc KK

α111

daKd /2=α

mBKK KRa =


37


Summary

Thinking global about energy usage- Crucial to allow exascale computers- Total cost of ownership perspective- Demand and supply of sensible heat: Thermal energy re-use- Cooling chips with “hot” water to obtain recyclable heat (65°C / 149 F) for remote heating- Joint project with ETH: Aquasar

Key components enabling efficiency and energy re-use (short term)- Improved thermal conductivity, reduced bondline- Improved heat transfer with micro and nanotechnology - Minimized exergy losses with water and hotspot cooling

Future interlayer cooling of 3D stacked chips (medium term)- Computer efficiency is dominated by communication- Collapse one rack of computers to one cubic centimeter and improve efficiency by more than 10x

Phonon Transport Engineering (long term)- Improved nanoscale heat transfer from nano to macro- Chemical surface functionalization- Geometrical patterning for phonon resonance matching- Long-term research: Modeling and experiment needed


38


Aquasar: Main Messages and Next Steps

Key Component for Future Datacenters- High-performance cooling technology exists but needs

to be combined with current computers- Thermal conductive and convective resistance are key

Roadmap for large efficiency increase in 10 years - 3D interlayer cooling and electrical-thermal co-design- Long-term reduction of boundary resistance - Work on reduction of nanoscale

thermal resistances

Aquasar specifications - Saves 40% of energy- Reduces emission by 85% through

heat re-use on ETH campus

Scale up to full size HPC and business data centers

Thermal energy re-use in solar collectors


39


Acknowledgment

Co-Authors: Werner Escher, Javier Goicochea, Ingmar Meijer

Advanced Thermal Packaging Group Members: Thomas Brunschwiler, Wulf Glatz, Javier Goicochea, Stephan Paredes, Patrick Ruch, Brian Smith, Reto Waelchli, Ryan Linderman

Microfabrication team: Rene Beyeler, Daniele Caimi, Ute Drechsler, Urs Kloter, Richard Stutz, Kurt Wasser, and Martin Witzig

IBM Boeblingen Research and Development GmbH (Germany): Martin Bachmaier, Bruno Battaglia, Gottfried Goldrian, Michael Malms, Juergen Marschall, Manfred Ries, and Walter Weber

IBM Research Yorktown (USA): Paul Andry, Evan Colgan, Claudius Feger, Winfried Haensch, Hendrik Hamann, Theodore vanKessel, Ken Marston, Yves Martin, John Maegerlein, and Thomas Theis

IBM Server and Technology Group in East Fishkill and Poughkeepsie (USA): Pepe Bezama, Kamal Sikka, Michael Ellsworth, Roger Schmidt, and Madhu Iyengar

IBM Austin and other locations (USA): Dave Frank, Vinod Kamath, Hannes Engelstaedter

CCEM Colleagues: Dimos Poulikakos, Petros Komoutsakos, Severin Zimmermann, Peter Kasten

Financial Support: IBM Zurich Research Laboratory, IBM Research FOAK program, Swiss Government KTI Projects, Swiss Government CCEM Project, Swiss Government NanoTera Project, EU FP7 project NanoPack

Thank your for your attention

thermal management in microelectronic devices and interfaces

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