school of microelectronic engineering emt362: microelectronic fabrication interlevel dielectric...

School of Microelectronic Engineering

EMT362: Microelectronic FabricationInterlevel Dielectric

Technology


Lecture Objectives

• Able to describe the main dielectric materials used in PMD and IMD

• Able to describe the main planarization techniques used in MOS fabrication.


FOUR MAIN CHALLENGES IN MULTILEVEL INTERCONNECT

PLANARIZATION OF INTERLEVEL DIELECTRIC

LOW-K DIELECTRIC MATERIALS

FILLING OF HIGH ASPECT RATIO CONTACT HOLES AND VIAS

INTERGRATION OF MANY TYPES OF CONDUCTOR AND DIELECTRIC MATERIALS


TERMINOLOGY

PASSIVATION

IMD OR ILD-1

METAL-2

VIA-1

METAL-1

PMD

CONTACT


REQUIREMENTS OF DIELECTRIC LAYERS

DIELECTRIC LAYERS MUST BE USED TO ELECTRICALLY ISOLATE ONE LEVEL OFCONDUCTOR FROM ANOTHER IN MULTI LEVEL INTERCONNECT SYSTEMS.

LOW K TO KEEP CAPACITANCE BETWEEN METAL LINES LOW HIGH BREAKDOWN ( > 5 MV / cm) NO MOISTURE ABSORPTION GOOD ADHESION TO ALUMINUM STABLE AT TEMPERATURES OF ~ 500 C GOOD CONFORMALITY (STEP COVERAGE) GOOD THICKNESS UNIFORMITY EASILY ETCHED


DIELECTRIC MATERIALS FOR PMD

DOPED SIO2 FILMS BY CVD TECHNIQUE

SILANE / TEOS BASED B(3-5%)P(3-5%)SG MOSTLY USED DIELECTRIC FOR PMD. REFLOW TEMPERATURE OF <850 C CAN BE ACHIEVED.

IN SUB-MICRON CMOS PROCESS, TEOS BASED CVD OXIDE IS MORE WIDELY USED COMPARED TO THAT OF THE SILANE BASED.

TYPICAL PMD USG (UNDOPED SIO2) – TO ACT AS A BARRIER TO THE B & P OUT DIFFUSION BPSG – EASY TO REFLOW AT LOW TEMPERATURE.


USG

BPSG

PB


DIELECTRIC MATERIALS FOR IMD

DOPED SILANE / TEOS BASED SIO2 FILMS

PHOSPHORUS IS ADDED TO; REDUCE FILM STRESS MORE RESISTANCE TO WATER SODIUM GETTERING

CURRENTLY, TEOS BASED FILMS ARE FAVOURABLE DUE TO; LOWER DEPOSITION TEMPERATURE (< 400C) BETTER GAP FILLING CAPABILITY (BETTER CONFORMALITY)

.


VOID


IMD FOR SILANE / TEOS BASED DIELECTRIC FILMS – MIMOS 0.5UM 1-P 2-M PROCESS


IMD FOR SILANE / TEOS BASED DIELECTRIC FILMS – MIMOS 0.5UM 1-P 2-M PROCESS

Silane oxide (3000A) or Silane NitrideBarrier for moisture and sodium ion

TEOS - O3 oxide (4000A)

SOG (1500A)

TEOS-02 (4000A)


PLANARIZATION OF INTERLEVEL DIELECTRIC FILMS

IMD

METAL No planarization

IMD

METAL Smoothing

IMD

METALSmoothing & partial planarization

ti

tf


IMD

METAL Complete local planarization

IMD

METAL Complete global planarization

Planarization factor, β = 1 – (tf / ti)

β = 1, complete planarizationβ = 0, no planarization


PROBLEM ASSOCIATED WITH POOR PLANARIZATION

1. Poor metal step coverage with result in metal thinning higher resistance open problem


2. Metal stringers after metal etch.3. DOF limititation for optical lithography – patterning problem

IMD

METAL

PR

MASK

DOF < 5um


PLANARIZATION TECHNIQUES

1. Thermal flow (only for PMD)


As deposited

After reflow


2. TEOS oxide deposit,etch-back and deposit


3. SOG deposit,etch-back and Oxide deposition


4. Oxide deposition, CMP oxide

school of microelectronic engineering emt362: microelectronic fabrication interlevel dielectric...

Documents

used dielectric

dielectric materials

main dielectric materials

pmd contact slide

etched slide

main challenges

imd able

main planarization techniques