27.dielectricmaterialsformicroelectronics dielectricma · dielectric materials are an integral...

Dielectric Ma615Part

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27. Dielectric Materials for Microelectronics

Robert M. Wallace

Dielectrics are an important class of thin-filmelectronic materials for microelectronics. Applica-tions include a wide swathe of device applications,including active devices such as transistors andtheir electrical isolation, as well as passive de-vices, such as capacitors. In a world dominatedby Si-based device technologies, the properties ofthin-film dielectric materials span several areas.Most recently, these include high-permittivity ap-plications, such as transistor gate and capacitordielectrics, as well as low-permittivity materials,such as inter-level metal dielectrics, operating atswitching frequencies in the gigahertz regime forthe most demanding applications.

This chapter provides a survey of the variousdielectric material systems employed to addressthe very substantial challenge associated withthe scaling Si-based integrated circuit technol-ogy. A synopsis of the challenge of device scaling isfollowed by an examination of the dielectric ma-terials employed for transistors, device isolation,memory and interconnect technologies. This ispresented in view of the industry roadmap whichcaptures the consensus for device scaling (and theunderlying economics) – the International Tech-nology Roadmap for Semiconductors.

27.1 Overview .......................................... 61527.1.1 The Scaling of Integrated Circuits ........ 61527.1.2 Role of Dielectrics for ICs .................... 619

27.2 Gate Dielectrics . ................................ 62027.2.1 Transistor Structure ............................ 62027.2.2 Transistor Dielectric Requirements

in View of Scaling .............................. 62127.2.3 Silicon Dioxide .................................. 62527.2.4 Silicon Oxynitride: SiOxNy ................... 63127.2.5 High-k Dielectrics. ............................. 633

27.3 Isolation Dielectrics. .......................... 635

27.4 Capacitor Dielectrics . ......................... 63627.4.1 Types of IC Memory ............................ 63627.4.2 Capacitor Dielectric Requirements

in View of Scaling .............................. 63627.4.3 Dielectrics

for Volatile Memory Capacitors ............ 63727.4.4 Dielectrics for Nonvolatile Memory ...... 637

27.5 Interconnect Dielectrics . .................... 63927.5.1 Tetraethoxysilane (TEOS) ..................... 64027.5.2 Low-k Dielectrics............................... 640

27.6 Summary .......................................... 641

References ................................................... 641

27.1 Overview

This chapter considers the role of dielectric materialsin microelectronic devices and circuits and providesa survey of the various materials employed in their fab-rication. We will examine the impact of scaling on thesematerials, and the various materials utilized for their di-electric behavior. Extensive reviews are available on thedevice characteristics for the reader to consult [27.1–4]. We will primarily confine the discussion here toSi-based microelectronic circuits, which continue todominate the industry.

Dielectric materials are an integral element of allmicroelectronic circuits. In addition to their primaryfunction of electrical isolation of circuit and devicecomponents, these materials also provide useful chem-

ical and interfacial properties. The material (and re-sulting electrical) properties of dielectrics must alsobe considered in the context of the thin films used insemiconductor microelectronics, as compared to bulkproperties. The dimensions of these dielectric thin filmsare determined by the device design of the associ-ated integrated circuit technology, and these dimensionsdecrease due to a calculated design process called scal-ing.

27.1.1 The Scaling of Integrated Circuits

The ability to reduce the size of the components ofintegrated circuits (ICs), and therefore the circuits

© Springer International Publishing AG 2017S. Kasap, P. Capper (Eds.), Springer Handbook of Electronic and Photonic Materials, DOI 10.1007/978-3-319-48933-9_27

PartC|27.1

616 Part C Materials for Electronics

themselves, has resulted in substantial improvements indevice and circuit speeds over the last 40 years. Equallyimportant, this calculated size reduction permits thefabrication of a higher density of circuits per unit areaon semiconductor substrates. The economic implicationof this scaling was captured by G. Moore more than50 years ago [27.5].

Moore’s LawMoore observed that the minimum cost of manufactur-ing integrated circuits per component actually decreaseswith increasing number of IC components, and thuswith greater circuit functionality and computing power.This is obviously an important economic driving force,as the ability to increase the number of circuits perunit area would lead to a lower minimum cost, andthus higher market demand and more potential profit.Moreover, Moore noted that the rate of increase inthe number of components for a given circuit functionroughly doubled each year in the early 1960s, and pre-dicted that it would continue to do so through 1975.In 1975, Moore revised this estimate of doubling timeto 24months due to the anticipated complexity of cir-cuits [27.6].

The semiconductor industry has generally con-firmed (and pursued) these extrapolations, often re-ferred to as Moore’s law, over the last 40 years. Theextrapolation is often analyzed in the semiconductorindustry, and the doubling period, which has variedbetween 17 and 32 months over the life of the in-dustry, is now roughly 24 months, with projectionsto lengthen [27.8]. Indeed the cost per transistor hasdecreased from � 5 $=transistor in 1965 to less than10�9 $=transistor today [27.9]. Current advanced Si ICproduction technology results in the fabrication of wellover 1 billion transistors on a microprocessor chip.

Technology RoadmapThe contemporary industry analysis encompassing thisobservation is presented in the International Technol-

Table 27.1 Selected scaling targets from the ITRS roadmap [27.7]

Year of production 2013 2014 2015 2016 2017 2018 2019 2020Technology node label (nm) “16/14” “11/10” “8/7” “6/5”High-Performance applicationsPhysical gate length (nm) 20 18 16:7 15:2 13:9 12:7 11:6 10:6Equivalent oxide thickness, Tox (nm) 0:8 0:77 0:73 0:70 0:67 0:64 0:61 0:59Drive voltage Vdd (V) 0:86 0:85 0:83 0:81 0:80 0:78 0:77 0:74Ioff (Leakage) (nA=�m) 100 100 100 100 100 100 100 100Low Power applicationsPhysical gate length (nm) 23 21 19:0 18:0 16:0 14:6 13:3 12:2Tox (nm) 0:8 0:77 0:73 0:70 0:67 0:64 0:61 0:59Vdd (V) 0:86 0:85 0:83 0:81 0:80 0:78 0:77 0:74Ioff (nA=�m) 0:1 0:1 0:1 0:1 0:1 0:1 0:1 0:2

ogy Roadmap for Semiconductors (ITRS) where the ex-trapolations of the future technological (and economic)targets for the industry are annually updated [27.7]. Thecurrent scaling trends indicate that the compound an-nual reduction rate (CARR) in device dimensions iscurrently consistent with the following equation

CARR.T/ D 1

2

. 12T / � 1 ; (27.1)

where T is the technology node cycle time measuredin years. Thus in two years, the rate of reduction is�15:9%. This corresponds to a scaling factor of �0:7� from a given technology node to the next, or a fac-tor of � 0:5� over the time of two technology nodes.This pace has been enabled through the introduction ofnew materials technologies such as strained Si, SiGe,and high-k/metal gate technologies. Analysis of thelimits of Si-based scaled integrated circuit technologyare available, including alternative channel materials,such as Ge and III-V semiconductors integrated onSi, have been discussed [27.10, 11]. According to themost recent ITRS Roadmap, non-Si channel materialsmay be in transistor production soon [27.7]. Scalinghas also driven the transistion from planar complemen-tary metal-oxide-semiconductor (CMOS) technologiesin production to three-dimensional (3-D) (vertical) tran-sistor component geometries.

Table 27.1 provides selected scaling targets from theITRS through 2020 [27.7]. As may be seen, the industryroadmap now has scaling targets which are driven bycontrolling power consumption. Higher-performancetechnologies, such as MPU/ASIC applications, requiremore aggressive scaling, while low power applicationsrequire less-aggressive scaling. A key criteria to enablethese technologies is the associated power managementin the on and off state, hence leakage current (Ioff)remains an important distinction amongst the variousroadmap applications.

Dielectric Materials for Microelectronics 27.1 Overview 617Part

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Gate Delay OnlyInterconnect – Cu + low-KInterconnect – Al + SiO2Total Delay – Cu + low-KTotal Delay – Al + SiO2

Time delay (ps)

Technologie generation (m)0.50 0.10

40

30

20

10

0.650

0.35 0.25 0.18 0.13

Fig. 27.1 Time delay contributions for integrated circuits.The resultant delay is dependent upon the circuit archi-tecture as well as the material constituents. (After [27.12],© 2004 IEEE, with permission)

Performance and ScalingThe concomitant reduction in device dimensions, suchas transistor channel length, associated with increasingthe number of components per unit area has resultedin a significant increase in processing performance –the speed at which computations can be done. Forexample, as scaling reduces the distance that carriersmust travel in a transistor channel, the response timeof the transistor as a digital switch also decreases (aslong as sufficient mobility is maintained). Scaling hasresulted in the speeds of microprocessors increasingfrom 25�50MHz clock frequencies in the early 1990s(� 106 transistors) to 2:2GHz in 2003 (� 108 tran-sistors) [27.13]. This speed has essentially leveled offsince 2003 due to power consumption considerationsand the resultant voltage scaling invoked, as well as in-terconnect limitations [27.9].

The various dielectric materials associated with thecomponents impacts the overall performance of thecorresponding IC technology. In the case of transis-tors, the gate dielectric is integral to the performanceof transistor electrical characteristics such as the drivecurrent Id. The interconnection performance of circuitelements is influenced by the dielectric material thatisolates the various metal interconnection lines throughthe line-to-line capacitance. Memory elements incorpo-rate very-low-leakage dielectric materials for charge-storage purposes. The behavior of these materials withcomponent size reduction is thus an important designconsideration in IC technology.

Figure 27.1 shows the dependence of the delaytime as a function of technology node (scaling) associ-ated with conventional CMOS transistor gates intercon-nected with metal lines that are isolated with differentdielectrics [27.12]. The total delay time associated withthe circuit response for a given technology node isa combination of the temporal response of the transis-tor gate (influenced by the gate capacitance) as well asthe propagation through the interconnecting wire linesassociated with the circuit (influenced by the wire resis-tance and the line-to-line capacitance, i. e., a resistive–capacitive (RC) delay) [27.12, 15]. Changing both theinterconnect wire material (from Al to Cu) to decreasethe line resistivity as well as decreasing the dielectricconstant in the material isolating these lines (from SiO2

to a lower dielectric constant material) to decrease line-to-line parasitic capacitance minimizes the overall RCdelay time response. Of course, the challenge in adopt-ing this solution was the successful integration of thesematerial changes into a high-volume fabrication line,which took the investment of considerable time and ef-fort.

In order to compare the performance of differ-ent CMOS technologies, one can consider a perfor-mance metric that captures the dynamic response (i. e.,charging and discharging) of the transistors associ-ated with a specific circuit element to the supplyvoltage provided to the element at a representative(clock) frequency [27.14, 16, 17]. A common elementemployed to examine such switching-time effects ina new transistor design technology node is a CMOSinverter. This circuit element is shown in Fig. 27.2where the input signal is attached to the gates andthe output signal is connected to both the n-typemetal/oxide/semiconductor (MOS) (NMOS) and p-typeMOS (PMOS) transistors associated with the CMOSstage. The switching time is limited by both the fall timerequired to discharge the load capacitance by the n-typefield-effect transistor (n-FET) drive current and the risetime required to charge the load capacitance by the p-FET drive current. That is, the switching response times� are given by

� D CLOADVdd

Id; where

CLOAD D FCGATE CCj CCi ; (27.2)

and Cj and Ci are the parasitic junction and local inter-connection capacitances, respectively. Of course, as oneconsiders the combination of transistors to produce var-ious circuit logic elements to enable computations (viz.a processor), it is also clear that the manner in whichthe transistors are interconnected also plays an impor-

PartC|27.1


Inverter stage NAND gate Logic fanout

Vdd

Vs

In Out

Fig. 27.2 Example circuits employed to evaluate the performance of a transistor technology. For example, elements arecombined to simulate processor performance adequately. (After [27.14], AIP, with permission © 2001)

tant role on the overall performance of the circuit. Thefan out for interconnected devices is given by the fac-tor F. Ignoring delay in the gate electrode response, as�GATE � �n,p, the average switching time is therefore

N� D �p C �n

2D CLOADVdd

�1

Ind C Ipd

�: (27.3)

The load capacitance in the case of a single CMOSinverter is simply the gate capacitance if one ignoresparasitic contributions such as junction and intercon-nect capacitance. Hence, an increase in Id is desir-able to reduce switching speeds. For more realisticestimates of microprocessor performance, the load ca-pacitance is connected (fanned out) to other inverterelements in a predetermined fashion. When coupledwith other NMOS/PMOS transistor pairs in the con-figuration shown in Fig. 27.2, one can create a logicNAND gate, which can be used to investigate the dy-namic response of the transistors and thus examine theirperformance under such configurations. For example,a fan out F D 3 can be employed in microprocessor per-formance estimates, as shown in Fig. 27.2.

One can then characterize the performance of a cir-cuit technology (based on a particular transistor struc-ture) through this switching time. To do this, variousfigures of merit (FOMs) have been proposed that in-corporate parasitic capacitance as well as the influenceof gate sheet resistance on the switching time [27.16–18]. For example, a common FOM employed is relatedto (27.3) simply by

FOM Š 1

N� D 2

�p C �n: (27.4)

In the case where parasitic capacitance and resis-tance effects are ignored, it is easily seen then that anincrease in the device drive current Id results in a de-crease in the switching time and thus an increase inthe FOM value (performance). However, the incorpora-tion of parasitic effects results in the limitation of FOM

Original device Scaled device

p Substrate, doping = NA

WiringVoltage V

Wn+

Gate Gate

Lg

XD

tOX

n+ n+

tOX/αV/α

W/αn+

Lg/α

Doping = αNA

Wiring

Fig. 27.3 Classical scaling methodology for integrated cir-cuit technology. (After [27.21], © 2004 IEEE, with permis-sion)

improvement, despite an increase in the gate dielectriccapacitance. All of these issues depend critically uponthe materials constituents of the integrated circuit, anddielectrics are an important component [27.14].

Impact of Scaling on DielectricsThe scaling associated with the device dimensionsthat constitute an integrated circuit impacts on virtu-ally all film dimensions such as thickness, includingthe dielectrics employed in the circuit. Various scalingmethodologies have been applied since the pioneeringwork byDennard and coworkers [27.19, 20]. These var-ious methods have been recently summarized [27.2,21]. For example, following the work byDennard et al.,the scaling of the transistor from one node N to the nextN C 1 under a constant-electric-field condition wouldresult in a relationship between the new transistor gate(or channel) length LNC1 D LN=˛, where ˛ > 1 is theconstant scaling factor (Fig. 27.3). Other dimensions,such as the gate dielectric thickness and the gate width,scale similarly. The voltage would also scale accordingto VNC1 D VN=˛ in this scenario as well. Table 27.1provides the drive voltage scaling (Vdd) anticipated bythe ITRS roadmap, depending upon the application.

Dielectric Materials for Microelectronics 27.1 Overview 619Part

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nMOS gate length (m)0.1

60

55

50

45

40

35

301

Fig. 27.4 Scaling trends of the planar transistor gate lengthand the gate insulator thickness for various generations ofintegrated technologies. The solid line is a linear fit to thedata. The dashed line represents the approximate scalingtrend between the gate dielectric thickness and gate lengthobserved over several technology generations: LG D 45�tox. (After [27.22], with permission)

This scaling approach has several shortcomings, in-cluding the reduction of power-supply voltages witheach node, raising problems with circuit power-supplycompatibility. So, for earlier technology nodes (L 0:35�m), the power supply was kept constant whilethe device dimensions were scaled as described above.Eventually, the resultant higher electric fields associ-ated with this scaling approach led to reliability con-cerns for the gate dielectric, mobility degradation andhot-carrier effects. For further scaling, the power sup-ply was scaled at a different factor (such as ˛1=2) tocompensate for such effects. For modern devices withdeep-submicron gate length, other techniques are usedto scale from node to node. Nevertheless, for planarCMOS technology through the 90 nm node, it has beennoted that the gate dielectric thickness can be relatedto the channel length as shown in Fig. 27.4 for a widevariety of device technologies as the depletion depthwas scaled with the dielectric [27.22]. As seen in theITRS Roadmap [27.7], scaling of the gate dielectrichas now reached a value just below a Tox � 0:8 nm(k � 12:5), and projected to decrease to Tox � 0:6 nmby 2020, implying a higher dielectric constant will beneeded (k � 16).

The critical point in the context of dielectric filmsis that the dimensions and geometry of the devices,and therefore the dimensions (thicknesses) of the di-electric layers, are significantly reduced as scalingproceeds (Table 27.1). At some point, the materialsproperties associated with the dielectric in a compo-

f (Hz)10 –2 1 102 104 106 108 1010 1012 1014 1016

Radio Infrared Ultraviolet

ModernCMOS

εr = 1

Electronic

εr

ε''r

Interfacial andspace charge

Orientational,dipolar

Ionic

Fig. 27.5 Schematic of the dependence of dielectric permittivity onfrequency. (After [27.23], with permission)

nent will be predicted to no longer provide the desirableelectrical behavior attained in previous nodes, thusstimulating research on new dielectric materials. Inthe case of gate dielectrics, scaling results in thinnerlayers of a given material to a point where quantum-mechanical tunneling becomes an issue. For memorycapacitor dielectrics, a specific capacitance density isrequired, regardless of capacitor dimensions, for a re-liable memory element. Indeed, scaling impacts on theselection and integration of numerous constituents ofelectronic devices including gate electrode materials,source/drain junction regions, contacts, interconnect di-electrics.

27.1.2 Role of Dielectrics for ICs

Dielectrics are pervasive throughout the structure ofan integrated circuit. Applications include gate di-electrics, tunneling oxides in memory devices, capac-itor dielectrics, interconnect dielectrics and isolationdielectrics, as well as sacrificial or masking applicationsduring the circuit fabrication process.

The basic properties utilized in dielectric materialsinclude their structure and the resultant polarizabilitybehavior. As noted in Fig. 27.5, there are several mech-anisms to consider in the polarization of materials inthe presence of an electric field. For nonmetallic (in-sulating) solids in CMOS applications, there are twomain contributions of interest to the dielectric con-stant which give rise to the polarizability: electronicand ionic dipoles. Figure 27.5 illustrates the frequencyranges where each contribution to the real part of thecomplex relative dielectric permittivity "r dominates,as well as the imaginary part of the complex per-mittivity (dielectric losses), "00

r [27.23]. The region ofinterest to CMOS applications includes the shaded areawhere switching frequencies are in the GHz range at thepresent time.

PartC|27.2


In general, atoms with a large ionic radius (i. e.,high atomic number, Z) exhibit more electron dipoleresponse to an external electric field, because thereare more electrons to respond to the field (electronscreening effects also play a role in this response). Thiselectronic contribution tends to increase the permittivityof materials with higher-Z atoms.

The ionic contribution to the permittivity canbe much larger than the electronic portion in casessuch as perovskite crystals of (Ba,Sr)TiO3 (BST) and(Pb,Zr)TiO3 (PZT), which exhibit ferroelectric behav-ior below the Curie point. In these cases, Ti ions inunit cells throughout the crystal are uniformly displaced

in response to an applied electric field (for the caseof ferroelectric materials, the Ti ions reside in one oftwo stable, non-isosymmetric positions about the centerof the Ti�O octahedra). This displacement of Ti ionscauses an enormous polarization in the material, andthus can give rise to very large dielectric constants inbulk films of 2000�3000, and has therefore been con-sidered for dynamic random-access memory (DRAM)capacitor applications [27.24, 25]. Since ions respondmore slowly than electrons to an applied field, theionic contribution begins to decrease at very high fre-quencies, in the infrared range of � 1012 Hz, as shownin Fig. 27.5.

27.2 Gate Dielectrics

27.2.1 Transistor Structure

A cross-sectional schematic of the structure of a planarmetal–oxide–semiconductor (MOS) field-effect transis-tor (FET) and a modern CMOS transistor, consisting ofthe n-FET and p-FET pair, is shown in Fig. 27.6. Thesource- and drain-region dopant profiles reflect modernplanar CMOS technologies where an extended, dopedregion is produced under the gate region in the channel.Additionally, so-called halo or pocket dopant implan-tation regions are also shown. These dopant profileapproaches have been incorporated in recent years in aneffort to permit transistor channel scaling and yet main-tain performance [27.27].

As can be seen, there exist several regions of the de-vice which require dielectric materials to enable usefultransistor operation. Both n-MOS and p-MOS transis-tors are isolated with a dielectric, typically depositedSiO2 in most modern device technologies, which is de-posited in trench structures. This isolation techniqueis called shallow trench isolation (STI) as the associ-

a) b)

p-well

n-gate p-gate

n+

Sidewall (spacer)dielectricGate

electrodeGatedielectric

Source

Sourcecontact

Drain

Sourceextension

Drainextension

Channelregion

Draincontact

Gate dielectric contact

n+ p+ p+

n-well

Isolationdielectric

Halo (“pocket”)implants

Fig. 27.6a,b Important regions of (a) a metal–oxide–semiconductor (MOS) field-effect transistor, and (b) a planarCMOS transistor structure. (After [27.26], © 2004 IEEE, with permission)

ated trench depth is 0:5�m. Earlier generations ofCMOS (and often devices under research) also utilizedthe so-called local oxidation of silicon (LOCOS) isola-tion approach [27.28, 29]. So-called spacer dielectrics(typically SiO2, SiOxNy, or SiNx) are also used aroundthe transistor gate stack for isolation and implantation-profile control. The gate stack is defined here as thefilms and interfaces comprising the gate electrode, theunderlying gate dielectric, and the channel region. Thegate dielectric, typically SiO2 or SiOxNy for transistorscurrently in production, electrically isolates the gateelectrode from the underlying Si channel region whileallowing the modulation of the carrier flow in the chan-nel. As we shall see, the interface between the gatedielectric and the channel regions is particularly impor-tant in regard to device performance.

Transistor structures have further evolved(Fig. 27.7) to a non-planar configuration to enableadequate electrostatics. Drive current and charac-teristics control with scaling. Examples include themultigate (FinFET) and gate-all-around transistor

Dielectric Materials for Microelectronics 27.2 Gate Dielectrics 621Part

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Gate

Gate

Multiple Drains

Drains

Multiple Sources

Sources

Fig. 27.7 Schematic and image ofa trigate transistor structure

structures. All of such structures still include a gatedielectric to isolate the gate from the channel, butrequire conformal deposition processes to enablereproducible and reliable performance.

27.2.2 Transistor Dielectric Requirementsin View of Scaling

In addition to the thickness reduction associated withscaling, the gate dielectric must adhere to several re-quirements that are dependent upon the specific productapplication, including adequate drive current, suitablecapacitance, minimal leakage current, and reliable per-formance. Table 27.1 provides some selected valuesdescribing the ITRS 2013 roadmap.

Drive CurrentThe improved performance associated with the scalingof logic device dimensions can be seen by consideringa simple model for the drive current associated witha FET [27.14, 16, 18, 30]. In the gradual channel ap-proximation, the drive current can be written as

Id D W

L�Cinv

�VG �VT � VD

2

�VD ; (27.5)

where W is the width of the transistor channel, L isthe channel length, � is the channel carrier mobility(assumed to be constant in this analysis), Cinv is thecapacitance density associated with the gate dielectricwhen the underlying channel is in the inverted state, VG

andVD are the voltages applied to the transistor gate anddrain, respectively, and the threshold voltage is given byVT. It can be seen that in this approximation the draincurrent is proportional to the average charge across thechannel (with a potential VD=2) and the average electricfield (VD=L) along the channel direction. Initially, ID in-creases linearly with VD and then eventually saturates toa maximum when VD,sat D VG �VT to yield:

ID,sat D W

L�Cinv

.VG �VT/2

2: (27.6)

A goal here is to increase the saturation drive cur-rent as much as possible for a given transistor technol-

ogy design. The term (VG �VT) is limited in range dueto reliability concerns as too large a VG would create anundesirable, high electric field across the gate dielec-tric. Moreover, practical operation of the device at roomtemperature (or above) requires that VT cannot eas-ily be reduced below about 8� kBT Š 200meV (kBT �25meV at room temperature). Elevated operating tem-peratures could therefore cause statistical fluctuationsin thermal energy, which would adversely affect thedesired VT value. Thus, even in this simplified approxi-mation, one is left to pursue a reduction in the channellength, increasing the width, increasing the gate dielec-tric capacitance, or a carefully engineered combinationof all of these in order to increase ID,sat. Note that noneof these dimensions are, in reality, independent and sosubstantial resources are utilized to simulate device per-formance in order to maximize the performance prior tothe fabrication of a representative transistor [27.2, 29,31].

Gate CapacitanceIn the case of increasing the inversion capacitance toimprove ID, consider the gate stack structure ideal-ized as a parallel-plate capacitor (ignoring quantum-mechanical and depletion effects from a Si substrateand gate [27.32]),

C D k"0A

t; (27.7)

where k is the dielectric constant of the material, "0 isthe electric constant (D 8:85� 10�3 fF=�m), A is thearea of the capacitor, and t is the thickness of the dielec-tric between the capacitor electrode plates. (Note thatthe relative permittivity of a material is often given by "or "r, such as with the expressionC D ""0A=t. Note thatthe relation between k and " varies depending on thechoice of units (e.g., when "0 D 1), but since it is alwaysthe case that k � ", we shall assume here that k D ".)It is clear that transistor designs utilizing planar CMOSscaling approaches discourage increasing the area of thecapacitor, and so one is left to considering the reductionof the dielectric thickness in order to increase the ca-pacitance.

PartC|27.2


In order to compare alternative dielectric materialswhich exhibit a dielectric constant higher than the stan-dard for the industry, SiO2, this expression for C canalso be rewritten in terms of teq (i. e., equivalent ox-ide thickness) and the kox of the capacitor (kox D 3:9for the low-frequency dielectric constant of SiO2). Theterm teq then represents the theoretical thickness of SiO2

that would be required to achieve the same capacitancedensity as the dielectric (ignoring important issues suchas leakage current and reliability). For example, if thecapacitor dielectric is SiO2, teq D 3:9 "0.A=C/, and soa capacitance density of C=A D 34:5 fF=�m2 corre-sponds to teq D 10Å.

Thus, the physical thickness of an alternative high-kdielectric employed to achieve the equivalent capaci-tance density of teq D 10Å can be obtained from theexpression

teqkox

D thigh-kkhigh-k

or simply,

thigh-k D khigh-kkox

teq D khigh-k3:9

teq : (27.8)

From this expression, a dielectric with a relative permit-tivity of 16 therefore results in a physical thickness of� 40Å, to obtain teq D 10Å. The increase in the phys-ical thickness of the dielectric impacts on propertiessuch as the tunneling (leakage) current through the di-electric, and is discussed further below.

The industry scaling process clearly presents a ma-jor challenge for the core transistor gate dielectric aspredictions call for a much thinner effective thicknessfor future alternative gate dielectrics: teq 1 nm [27.7].The interfacial regions between the gate electrode,dielectric and channel (in totality termed the metal–insulator–semiconductor (MIS) gate stack as shownschematically in Fig. 27.8) require careful attention, asthey are particularly important in regard to transistorperformance. These regions, less than approximately0:5 nm thick, serve as a transition between the atoms as-sociated with the materials in the gate electrode, gate di-

Gate electrode

Upper interface

Gate dielectric

Lower interfaceChannel layer

Si substrate

Fig. 27.8 Schematic ofthe important regions ofthe transistor gate stack.(After [27.14], AIP, withpermission © 2001)

electric and Si channel, and can alter the overall capaci-tance of the gate stack, particularly if they have a thick-ness that is substantial relative to the gate dielectric.Additionally, these interfacial regions can be exploitedto obtain desirable properties. The upper interface, forexample, can be engineered in order to block boron out-diffusion from the poly-Si gate. The lower interface,which is in direct contact with the CMOS channel re-gion, must be engineered to provide low interface trapdensities (e.g., dangling bonds) and minimize carrierscattering (maximize channel carrier mobility) in orderto obtain reliable, high-performance device. Mobilitydegradation, relative to that obtained using SiO2 (orSiON) gate dielectrics, associated with the incorpora-tion of high-k gate dielectrics is an important issue cur-rently under investigation and discussed further below.

Reactions at either of these interfaces during thedevice fabrication process can result in the formationof a significant interfacial layer that will likely re-duce the desired gate stack capacitance. Additionally,any suitable interfacial layer near the channel mustresult in a low density of electrically active defects(/ 1011=cm2 eV is often obtained for SiO2) and avoiddegradation of carrier mobility in the region near thesurface channel.

The reduced capacitance can be seen by noting thatthe dielectric film that has undergone interfacial reac-tions results in a structure that essentially consists ofseveral dielectric layers in series. If we suppose that thedielectric consists of two layers, then from electrostat-ics the total capacitance of two dielectrics in series isgiven by 1=Ctot D 1=C1 C 1=C2, where C1 and C2 arethe capacitances of the two layers. Thus, the lowest-capacitance layer will dominate the overall capacitanceand also set a limit on the minimum achievable teqvalue. If we consider a dielectric stack structure suchthat the bottom layer (layer 1) of the stack is SiO2, andthe top layer (layer 2) is the high-k alternative gate di-electric, (27.8) is expanded (assuming equal areas) to

teq D tSiO2 C kSiO2

khigh-kthigh-k : (27.9)

From (27.9), it is clear that the layer with the lower di-electric constant (SiO2 in this case) limits the ultimatecapacitance of the MIS gate stack.

Of course, the actual capacitance of a CMOSgate stack for ultra-large-scale integration (ULSI) de-vices does not scale simply with 1=t due to parasitics,quantum-mechanical confinement of carriers, and de-pletion effects. Indeed, consideration of these importanteffects can result in much confusion on the definitionof dielectric thickness as extracted from electrical mea-surements.


C|27.2

Parasitic resistances and capacitances associatedwith various portions of the transistor structure can re-sult in an overall degradation of performance as definedby a delay time figure of merit [27.14, 17]. There ex-ist several materials issues associated with the controlof such parasitics including source/drain dopant-profilecontrol, gate/contact sheet resistance minimization, etc.which are beyond the scope of this chapter.

Quantum-mechanical confinement effects on carri-ers in the channel region occur as a result of the largeelectrical fields in the vicinity of the Si substrate sur-face. These fields quantize the available energy levelsresulting in the displacement of the charge centroidfrom the interface into the Si and at energies abovethe Si conduction-band edge. The extent of the pen-etration of the charge centroid is dependent upon thebiasing conditions employed for the metal–insulator–semiconductor (MIS) structure and, for accurate es-timates of transistor drain-current performance, theinversion capacitance measurement provides accuratedetermination of the equivalent oxide thickness [27.32–34].

Earlier MIS gate-stack structures employ heavilydoped polycrystalline Si (poly-Si) as the metal gateelectrode for CMOS transistors. Poly-Si gates were in-troduced as a replacement for Al metal gates in the1970s for CMOS integrated circuits and have the verydesirable property of a tunable work function for bothn-MOS and p-MOS transistors through the implanta-tion of the appropriate dopant into the poly-Si gateelectrode.

However, in deep-submicron scaled devices, thepoly-Si depletion effect impacts the overall gate-stackcapacitance significantly, as the scaling results in anincreased sensitivity to the effective electrical thick-ness resulting from all of the gate-stack componentfilms, including the gate electrode. The depletion effect(which occurs in any doped semiconductor) is a resultof the decrease in the density of majority carriers nearthe poly-Si/dielectric interface upon biasing, resultingin an increased depletion width in the poly-Si [27.27,35]. This results in a voltage drop across the depletionregion, rendering a smaller voltage drop across the re-maining portions of the gate stack (i. e., the dielectricand the substrate). As a result, the (low-frequency) ca-pacitance under strong inversion biasing conditions issignificantly lower than that obtained under accumula-tion (Fig. 27.9). Moreover, the inversion-layer chargein the substrate is reduced from that possible in theideal case where no depletion layer exists in the gate(i. e., an ideal metal conductor for the gate electrode).This reduction in the inversion-layer charge in turn re-duces the ideal transistor drive current. As the dielectricthickness is reduced in the scaling process, this effect

Capacitance (pF)

Voltage (V)

–3.53.0

180

160

140

120

100

80

60

40

20

0

–3.0–2.5 –1.5 –0.5

0.0 1.0 2.0–2.0 –1.00.5 1.5 2.5

tox = 2 nm Vfb = –1 Nsub= 2e17/cm3 Npoly = 6e19/cm3

With PD&QMWith QMWith PDCorrected

Fig. 27.9 Capacitance–voltage curves demonstrating the effects ofpoly-Si depletion and quantum-mechanical behavior for scaledtransistors. Nsub and Npoly denote the dopant density for the sub-strate and poly-Si gate, respectively. (After [27.36])

becomes a serious limitation for transistor drive cur-rent.

To solve this problem, a return to metal gate elec-trode materials has been invoked to eliminate any deple-tion region in the gate, and thus the interaction of anydielectric with various metal gate candidates is of in-terest. Compatibility of dielectric materials with metalgate materials is discussed later in this chapter.

When a capacitance–voltage curve is properly cor-rected for these quantum-mechanical and dopant deple-tion effects, as seen in Fig. 27.9, one can accurately ex-tract the equivalent oxide thickness (EOT), teq [27.36].This thickness definition is in contrast to that deriveddirectly from the raw data in a capacitance–voltage(C–V) measurement, which is termed the capacitanceequivalent thickness (CET> EOT), or the physicalthickness, which can be determined by non-electricalcharacterization methods such as ellipsometry or high-resolution transmission electron microscopy, as seenin Fig. 27.10 [27.36, 37]. Please note that thicknessesderived from quantum-mechanical-corrected accumula-tion capacitance data are also often abbreviated as tqm.

Leakage CurrentOf course, physically thinning the dielectric layer tothe nanometer regime raises the prospect of quantum-mechanical tunneling through the dielectric – oftenreferred to as leakage. To minimize gate leakage (tun-neling) currents, quantum mechanics indicates that thegate dielectric must be sufficiently thick and have a suf-ficient energy barrier (band offset) to minimize the

PartC|27.2


XPS thickness (nm)0 14

14

12

10

8

6

4

2

02 4 6 8 10 12

Thickness by other techniques (nm)

EllipsometryC-VTEM

Fig. 27.10 Metrology results for various measurementtechniques of the thickness of thin SiO2 films. X-rayphotoelectron spectroscopy (XPS) measured thicknessesare compared to thicknesses derived from high-resolutiontransmission electron microscopy (HRTEM), C–V and el-lipsometry. (After [27.37], AIP, with permission © 1997)

resultant tunneling current. Consider the band diagramshown in Fig. 27.11, where the electron affinity (�) andgate electrode work function (˚M) are defined (q is thecharge). For electrons traveling from the Si substrateto the gate, this barrier is the conduction-band offset, EC Š q Œ�� .˚M �˚B/�; for electrons traveling fromthe gate to the Si substrate, this barrier is ˚B. The effectof the height of the energy barrier and the film thick-ness on tunneling current can be seen by consideringthe expression for the direct tunneling current whereelectron transport occurs through a trapezoidal energybarrier [27.16]

Jdt D A

t2dielexp .�Btdiel/

�(�

˚B � Vdiel

2

�exp

"s�˚B � Vdiel

2

�#

��˚B C Vdiel

2

�exp

s�˚B C Vdiel

2

�)

:

(27.10)

Here A is a constant, B D 4�=h.2m�q/1=2, ˚B is thepotential-energy barrier associated with the tunneling

Vacuum level

SemiconductorInsulatorMetal

EF

qΦM qΦB q

qΨB

Ec

EiEv

Eg

Fig. 27.11 Energy-band diagram for an MIS stack structure

process, tdiel is the physical thickness of the dielec-tric, Vdiel is the voltage drop across the dielectric, andm� is the electron effective mass in the dielectric.From (27.10), one observes that the tunneling (leakage)current increases exponentially with decreasing barrierheight and thickness for electron direct-tunneling trans-port. In the context of charge transport through thedielectric, electrically active defects (electron or holetraps) can result in charging of the dielectric, which inturn deleteriously affects the electric field in the channelregion and therefore mobility. Conduction mechanismsthrough such fixed charge traps can also be evaluatedthrough electrical characterization techniques [27.16].In the case of dielectrics layers, tunneling transport hasalso been previously examined [27.38].

The introduction of a dielectric material that ex-hibits a suitable energy barrier and thickness, whileperforming electrically as a thin SiO2 layer, is nowa key research and development goal for the indus-try to continue the scaling trend. It is also clearthat the gate dielectric must exhibit adequate thick-ness uniformity and integrity over the surface of thewafer. The reduction of this leakage current impactsimportant circuit properties such as stand-by powerconsumption, as shown in Fig. 27.12. With the min-imization of leakage current as a key driving force,alternate gate dielectric materials appear to be requiredfor low-power CMOS device technologies in the nearfuture and are therefore the subject of intense re-search.

ReliabilityAny gate dielectric material must possess the abilityto enable a specified, stable operational lifetime forthe transistor. Key areas of concern in this regard in-cludes defect generation/mitigation resulting in dielec-tric breakdown phenomenon, charge formation withinthe dielectric and at the associated interfaces, and resis-tance to energetic (hot) carrier interactions. This is often


C|27.2

Gate currentdensity (A/cm2)

Gate voltage (V)0 8

103

102

101

100

10–1

10–2

10–3

10–4

10–5

10–6

10–7

102

101

100

10–1

10–2

10–3

10–4

10–5

10–6

10–7

10–8

(Assumes 0.1 cm2 area)Standby power

consumption (W)

1 2 3 4 5 6 7

15Åoxide

High- forteq = 15 Å

10 mW

1 mW

K

Fig. 27.12 Reduction of leakage (tunneling current) fromthe incorporation of a higher permittivity gate dielectric.(After [27.14], AIP, with permission © 2001)

Table 27.2 Properties of SiO2

Geometrical parametersSi�Si bond length 3:12ÅSi�O bond length 1:62ÅO�O bond length 2:27ÅMean bond angle 144ı (tetrahedral bonding)Bond angle range Si�O�Si: 110 to 180ı

Density (g=cm3)Thermally grown (fused silica) 2:20Quartz 2:65Index of refraction (optical frequencies)Thermally grown (fused silica) 1:460Quartz 1:544Quasi-static dielectric constant (� 1 kHz)Thermally grown (fused silica) 3:84Quartz 3:85Band gapThermally grown (fused silica) 8:9 eVQuartz � 9:0 eVElectrical breakdown strengthThermally grown (fused silica) 10MV=cmQuartz � 10MV=cm

evaluated in the context of accelerated lifetime testingthrough electrical stressing in combination with ther-mal stressing of devices. Reviews on these topics can befound in this handbook as well as other sources [27.3,27, 39, 40].

Pressure (kbar)

Temperature (C)0

100

90

80

70

60

50

40

30

20

10

0400 800 1200 1600 2000

-Quarz

α-Quarz (Chrystobalite)

(Tridymite)Liquid

Coesite

Stishovite

Θ

O

S i

b)

O

Si

Oa)

O O

i S

Fig. 27.13a,b Phase diagram for SiO2. Inset: bonding configura-tions for the O�Si�O system. (a) Tetrahedral unit for the Si�Obonding arrangement. (b) Bond angle defined for O�Si�Obonds. (After [27.41], IOP Publishing © 1994, with permission)

27.2.3 Silicon Dioxide

As articulated byHummel, silicon has an amazing num-ber of desirable materials (and therefore electronic)properties that no other electronic material can ri-val [27.42]. Silicon constitutes 28% of the Earth’s crust,it is nontoxic, exhibits a useful band gap (EG D 1:12 eV)for applications at room temperature, and can be grownin crystalline form (from abundant sand, i. e., SiO2).However, it can be argued that the ability of Si toform the stable, high-quality insulator, SiO2, may bethe primary reason that Si-based transistor technologyhas dominated the industry since the 1960s [27.5, 43].This compound has a number of material properties thatresult in outstanding electrical performance. Some ofthese properties are summarized in Table 27.2. Overthe last 25 years, abundant compendia of the proper-ties of SiO2 with particular emphasis on materials andelectrical properties have been published, as well as

PartC|27.2


Intensity (arb. units)

Initial-state energy (eV relative to bulk Si2p3/2)–7 3

b)

–6 –5 –4 –3 –2 –1 0 1 2

Intensity (arb. units)

Initial-state energy (eV relative to bulk Si2p3/2)–8

c)

–7 –6 –5 –4 –3 –2 –1 0 1 2

a)

Si(111)

Si(100)

Si 2p3/2

SiO2 Si

Si3+

Si2+

Si1+

Si(111)

Si(100)

Si 2p3/2

SiO2 Si

Si3+

Si2+Si1+

Si

Si

Si

Si Si

Si0

O

Si

Si

Si Si

Si1+

O

Si

Si

Si O

Si2+

O

O

Si

O O

Si3+

O

O

Si

Si4+

O O

Fig. 27.14 (a) Oxidation states and local chemical bonding variations associated with the Si�SiO2 interface. Af-ter [27.41]. High-resolution XPS results demonstrating the existence of such bonding variations at the interface forsubstrate orientation and with (b) 5Å and (c) 14Å SiO2 film thickness. Photon energy h� D 130 eV. (After [27.44], APS,with permission © 1988)

conferences which have focused almost exclusively onSiO2 [27.45–54].

It is noteworthy that the early development of tran-sistor technology utilized the semiconductor Ge, whichhas a rather unstable oxide, GeO2, that is water sol-uble. The utilization of crystalline Si and its stable

oxide presented a superior solution for the practicalmanufacturing of the planar transistor and the associ-ated integrated circuit of the era [27.43]. It was theutilization of the properties of SiO2 that resulted inthe dominance of Si-based device technology over Ge-based technology in the 1960s.


C|27.2

100% Si4 + (SiO2)

65% Si4++ 35% Si3+

29% Si4++ 71% Si3+

64% Si2++ 36% Si1+

Si(100)

0.6 nm

t

t

a) b)

Fig. 27.15 (a) First-principles simulations of the SiO2/Si interface. After [27.55] © 2002 Elsevier. (b) Angle-resolvedXPS results for the SiO2/Si interface showing the detected O�Si�O bonding environments. The single layer thick-ness t D 0:137 nm associated with the bonding distance in Si in this evaluation. (After [27.56], © 2001 by APS, withpermission)

Bonding Arrangements for Thin SiO2As can be seen in Fig. 27.13, the phase diagram forSiO2 has a number of crystalline phases and associatedpolymorphisms [27.41, 53]. In the context of accessi-ble phase space appropriate for typical CMOS pro-cesses (pressure � 1 bar and T 1100 ıC), the quartzand tridymite phases are stable [27.57]. High-pressurephases are also well studied [27.58].

The bulk SiO2 tetrahedral bonding coordination (in-set, Fig. 27.13) results in an average Si�O�Si bondangle of � 145ı [27.59] comparable to that observedfor vitreous silica [27.41, 60]. As noted originally inthe classic work by Zachariasen, the bonding inter-connections among the various SiO4 tetrahedra canresult in an amorphous SiO2 film consisting of locallyordered ring structures commonly observed in silicaglasses [27.51, 53, 61]. The numerous available varia-tions of the ring structure provide substantial flexibilityand minimize bond strain and the density of defects atinterfaces [27.62].

For the purposes of microelectronic applications,we first consider so-called thermally grown SiO2. Asthe name implies, a SiO2 layer is formed on Sifrom a thermally activated oxidation process (oftenreferred to as a thermal oxide) rather than simplya (low-temperature) deposition process. Thermal oxidefilms are stable enough to endure high-temperature (�1000 ıC) post-implantation/dopant activation anneals.These films have useful electrical properties includinga stable (thermal and electrical) interface with min-imal electrically-active-defect densities (� 1010 =cm2)

as well as high breakdown strength (� 10MV=cm)over a large area (� 1 cm2) [27.16]. The breakdownstrength is important for high reliability of devices fab-ricated with a dielectric, as the scaling of devices typ-ically results in somewhat higher electric fields acrossthe oxide.

Recent experimental results on thin thermalSiO2 [27.36, 39, 63] combined with modern compu-tational modeling [27.55, 59] of the defects associ-ated with the SiO2/Si(001) interface, which is thedominant microelectronic materials system, and bulkSiO2 [27.64] has provided a reasonably consistentpicture of the known defects and interface struc-ture.

High resolution x-ray photoelectron spectroscopy(XPS) evidence, coupled with other experimental andtheoretical modeling results, appears to support thepresence of SiOx (x D 4) species (often called sub-oxides) detected as a chemical shift in the associatedSi oxidation states (Fig. 27.14) [27.44, 65–67].

More recent high-resolution angle-resolved XPSanalysis of ultrathin (6Å) SiO2 has resulted in a furtherunderstanding of the average oxidation state observedwith depth along the interfacial transition region [27.56,68]. From these experimental results, models of theinterface have been constructed from first-principlesmethods that reproduce the experimental results, asshown in Fig. 27.15 [27.55, 59]. As seen in Fig. 27.15,the transition region between the Si substrate and theSiO2 consists of interfacial suboxide species of varyingabundance (and therefore density). These results appear

PartC|27.2


Pressure(Torr)

1000/T (K–1)0.6

10–1

10–2

10–3

10–4

10–5

10–6

10–7

10–8

10–9

10–10

Temperature (C)600 700 800 900 1000 1100 1200

1.1 1.0 0.9 0.8 0.71.2

Si + O2 SiO2(s)

SiO2 formation

SiO formation(etching)

2Si + O2 2 SiO(g)

Fig. 27.16 Pressure–temperature phase diagram for thinSiO2/Si. (After [27.76], © 1997 AIP, with permission)

to be in general agreement with recent high-resolutiontransmission electron microscopy as well [27.69].

Oxidation Kinetics of SiThe oxidation kinetics of Si have also been exhaustivelystudied and reviewed [27.27, 39, 70]. Two regimesfor oxidation are generally characterized as passiveand active in nature. The passive oxidation regimerefers to the low-temperature/high-pressure region ofthe pressure–temperature (p–T) phase space shownin Fig. 27.16 [27.39, 71–76]. In this portion of the p–Tphase space, the reaction between Si and O2 proceedsas a surface reaction resulting in a thin ( 2 nm) SiOx

layer, where 0:5 x 2. Decreasing pressure and in-creasing temperature during the reaction results in bothSi etching and oxidation – the so-called active regime –and the formation of thicker SiO2 films.

The clever utilization of isotopic labeling tech-niques coupled with depth profiling from ion scat-tering [27.77] and nuclear reaction analysis [27.70]has generally confirmed that molecular oxygen (O2) isthe mobile species that interstitially diffuses througha growing oxide and only reacts at the Si interface toform the SiO2 on the Si surface, as first empiricallyproposed by Deal and Grove in 1965 for SiO2 thickerthan about 4 nm [27.78, 79]. The details of the oxida-tion process for thin films deviates from theDeal–Grovemodel, and is discussed thoroughly in the review byGreen et al., for example [27.39].

Defects for Thin SiO2In addition to the electrical breakdown strength asso-ciated with SiO2, the physicochemical properties ofthe interface between the substrate Si and SiO2 playsa major role in establishing the observed electrical prop-erties [27.63, 67]. Like all interfaces of solids, the inter-face between bulk Si and bulk SiO2 naturally results inthe presence of point defects (Fig. 27.17). Examples in-clude strained bonds, atoms that are not fully bondedto neighboring atoms (so-called dangling), bonds andhydrogenic species bonded among the Si�O bondingnetwork. These defects can result in energy levels inthe band structure associated with an MIS device, andserve as traps for carriers (electrons and holes).

The dominant orientation for contemporary Si-based integrated circuit technology substrates isSi(100). This is, of course, no accident and the choiceof the substrate orientation has much to do with the re-sultant SiO2/Si interface. Early in the development ofSi-based transistors, it was observed that the density ofinterface states for SiO2 grown on Si(100) was signifi-cantly lower than that observed on Si(111) [27.80–84].This difference in interface state behavior is attributedto the density of unsatisfied (dangling) bonds at theSiO2/Si interface.

Techniques sensitive to the presence of such pointdefects, such as electron (paramagnetic) spin reso-nance (EPR or ESR) [27.85] have provided valuableinsight on the atomic nature of the various defects inthe bulk and interfacial regions of SiO2 [27.86–91].For such defects, although the electrical manifestationof significant densities ( 1010 =cm2 eV) of such trapstates is easily detected by conventional electrical char-acterization methods, the unambiguous identificationof the moiety responsible for the observed electricalbehavior is very difficult using only electrical charac-terization. From techniques like ESR employed over thelast 30 years, point-defect structural models have beenestablished in the bulk regions of SiO2 and Si, as wellas at the interface (including various substrate orienta-tions). A schematic illustration of various known pointdefects for the Si/SiO2 system is shown in Fig. 27.17.The major classes of defects that have been examinedover the last 35 years by ESR have included interfacialdangling bonds (Pb centers) and bulk defects in SiO2

(E0 centers) [27.88, 91].The early discovery and study of Pb centers [27.92–

94] eventually led to the interpretation of their ESRsignals as due to dangling bonds and the realizationof their importance to MOS device physics [27.87, 88,95, 96]. It has also been noted that Pb-center defectsare generated for unannealed, thermally stressed andradiation-damaged MOS structures, and moreover canaccount for roughly 50% of the density of interface de-


C|27.2

a) b)Pb Pb

SiO2

(111) Si

(110) Si

Pb Pb

SiO2

(100) Si

SiO2

Pb0 Pb0 Pb1? Pb1?

Pb

SiO2

(111) Si

Pb

+E1

Eb

Peroxy

H

NBOHC

SiliconOxygen

Pbd

Fig. 27.17a,b Schematic representations of (a) the various point defects for the SiO2/Si interface and (b) bulk SiO2.(After [27.41], IOP, with permission © 1994)

fect states (Dit/ for Si/SiO2 interfaces [27.41, 97, 98]. Ithas been demonstrated that the interface state densitycan be directly proportional to the density of Pb centers(dangling bonds) for the SiO2/Si(111) and SiO2/Si(100)interfaces, as seen in Fig. 27.18. Recently, further ESRwork has been performed to establish the detailed struc-ture of the defect on Si(100) and Si(111) [27.99–106].

Mitigation of Defects for Thin SiO2Synopses of the early MOS transistor work [27.108–110] examining the importance of the dielectric–semiconductor interface are available [27.3, 43, 111].Indeed, the close connection between interfacial chem-ical behavior and electrical device performance wasinvestigated and realized in pioneering surface sci-ence work by Law and coworkers on the reaction ofgaseous species with atomically clean Ge [27.112] andSi surfaces [27.113–115]. In particular, the relative in-terface state (dangling-bond) density, as measured bythe areal density of surface reactions with technologi-cally important species such as H2O, H2, O2, CO, CO2,provided important clues on the control of the Si/SiO2

interface and the resultant electrical properties reported5�10 years later.

The control of the density of interface defectsthrough the chemical reaction of species, introducedmainly through gaseous exposure at elevated temper-atures, has proven to be fruitful. As noted above, earlysurface science work [27.113] indicated the rapid re-action of H2 with the atomically clean Si surface. Bydefinition, the atomically clean Si surface is saturated

Midgap Dit (1011/cm2eV)

Spin density (1011/cm2)0 30

30

25

20

15

10

5

05 10 15 20 25

N2 SP Si(111)O2 FP Si(111)O2 FP n-type Si(111)O2 FP p-type Si(111)O2 FP n-type Si(100)O2 FP p-type Si(100)Linear fit

Fig. 27.18 Correlation of mid-gap interface state densitywith detected spin density from ESR measurements forSiO2/Si(111) and SiO2/Si(100). FP and SP denote fast andslow pullout conditions for the wafers from the furnaceafter thermal treatments. (After [27.96, 107], with permis-sion)

with dangling bonds. The reaction of these bonds withH2 results in the chemical passivation of the surface –that is, the reaction of the surface to eliminate thedangling bonds and produce a H-terminated Si sur-face. In the context of the MOS structure [27.48, 116],it was realized early that annealing the structure in

PartC|27.2


Vacuum level

n-type semiconductorDielectricMetal

EF

qΦMqΦB

q

qΨB

Ec

EI

Ev

EgEF

a)

Vacuum level

p-type semiconductorDielectricMetal

EF

qΦMqΦB

q

qΨB

Ec

EI

Ev

Eg

EF

b)

C

V

+Qf

VFB

Ideal C-V

V

–Qf

VFBIdeal C-V

– 0 +

C

V

+Qf

VFBIdeal C-V

V

–Qf

VFBIdeal C-V

– 0 +

Fig. 27.19a,b The effect of fixed charging of the capacitor dielectric, demonstrating the shift of the associated flat-bandvoltage for MIS structures with (a) n-type and (b) p-type substrates. (After [27.14], © 2001 AIP, with permission)

ambient H2 resulted in beneficial transconductance per-formance [27.117–120]. The use of anneals in forminggas (N2 W H2 of various mixtures, typically 90�95%N2 : 10�5% H2) were originally developed to improveelectrical contacts for the gate and source/drain regionsof the metal/oxide/semiconductor field effect transistorMOSFET. Balk and Kooi established the effect of hy-drogen ambients on the reduction of fixed charge in theAl/SiO2/Si MOS structure [27.119, 121].

Subsequent studies demonstrated that anneals of theMOS structure in hydrogenic environments, typically at400�500 ıC for 30�60min, results in the passivationof dangling bonds at the interface [27.96, 99–104, 122–125].

Hydrogen incorporation into the bulk of SiO2 can,however, also be detrimental to dielectric performancein MOS capacitors and FETs [27.41, 126]. For exam-

ple, silicon bonded to hydroxyl (silanol) species havebeen identified with fixed charge in the oxide, re-sulting in undesirable, irreversible voltage shifts. Thischarge induced shift is shown in Fig. 27.19 for n-typeand p-type MIS diode structures from their associ-ated capacitance–voltage response [27.3, 4, 14]. (Ananalogous threshold-voltage shift would be observedin a transistor turn-on characteristic.) More compli-cated effects such as negative-bias temperature insta-bility (NBTI), where an increase of the density offixed charge (Qf) and interface trap (Qit) density isnoted with time upon thermal stress and/or under neg-ative bias, has been attributed to H2O-induced depas-sivation of Si dangling bonds (i. e., generation of Pbcenters) at the Si/SiO2 interface [27.41, 127]. Defectsgenerated by radiation damage have also been exten-sively investigated [27.41, 128] as well as interactions


C|27.2

with annealing ambients such as vacuum [27.129] orSiO [27.123].

Dielectric Breakdown and Reliability of SiO2As noted in Sect. 27.2.2, the reliability of dielectricsis obviously an important phenomenon to control. Thescaling of microelectronic devices necessarily resultsin increased stress on the dielectric due to the higherelectric fields placed across the dielectric film. As a re-sult, power-supply voltages are also scaled to minimizethe likelihood of catastrophic (hard) breakdown, whichwould generally result in complete failure in the as-sociated integrated circuit. As noted by Hori, sucha catastrophic breakdown phenomenon is dependentupon the presence of defects in the dielectric, and thusrequires a statistical analysis of many devices (andtherefore films) to enable a reliability prediction for thedielectric layer [27.16]. Evaluation of the breakdownis often performed under the conditions of constant-field stress until a time at which breakdown is observed(called time-dependent dielectric breakdown (TDDB)).Breakdown fields for thermally grown SiO2 with thick-nesses larger than � 10 nm often exceed 10MV=cm,providing outstanding insulator prosperities for micro-electronic applications. Various models have also beendeveloped to accelerate such testing to perform reliabil-ity predictions. A concise review of these is offered inthe literature as well [27.16, 27]. Defects such as filmnonuniformity, bond stress, surface asperities, contam-ination, and particulates embedded in the film or theSi substrate are a few examples of potential causes ofcatastrophic breakdown phenomenon.

With the scaling of the SiO2 gate dielectric layerto thicknesses well below 10 nm, extensive evaluationshave been made of the various models that attempt topredict the reliability of SiO2 in regard to breakdown.Often, a soft breakdown can be observed, where thefilm exhibits a sudden increase in conductivity, but notto the same degree as that observed in hard breakdownphenomenon. In spite of the many years of research onSiO2 thin films, the nuances of the dependence of volt-age acceleration extrapolation on dielectric thicknessand the improvement of reliability projection arisingfrom improved oxide thickness uniformity, have onlyrecently become understood, despite decades of re-search on SiO2 [27.130].

27.2.4 Silicon Oxynitride: SiOxNy

The introduction of nitrogen in SiO2, often described assilicon-oxynitride (or more simply SiON) has providedthe opportunity to maintain the scaling expectationsfor integrated circuits while minimizing the processvariations associated with the modification of the gate

T (C)

log (pO2 bar)–25 –5

1800

1600

1400

1200

–20 –15 –10

G

LS

Si3N4

Si2N2O

SiO2 (Crystobalite)

SiO2 (Tridymite)

Fig. 27.20 Calculated phase diagram for the growth ofSi�O�N for various oxygen partial pressures. (Af-ter [27.133], with permission)

dielectric material [27.16, 39, 70, 131]. (It should benoted that engineers and technologists often loosely re-fer to SiON films simply as oxide or nitride – frequentlyleading to confusion on the detailed chemical compo-sition of the film.) Introduction of N into SiO2 hasbeen accomplished by thermal treatments (in N2, N2O,NO and NH3) as well as plasma treatments [27.16,132]. The bulk phase diagram for the SiON systemis presented in Fig. 27.20, which indicates that, underequilibrium conditions, Si2N2O is the only stable SiONspecies and SiO2 and Si3N4 would not coexist [27.133].As noted by Green et al., N would not be expectedto incorporate into SiO2 whenever an even very smallpartial pressure of oxygen PO2 > 10�20 atm is present.However, the nonequilibrium surface reaction kineticsand/or a reduction in interfacial bond strain likely playsa key role in the tendency for interfacial N incorporationfor SiON films [27.39].

The dielectric constant and band gap as a functionof the SiO2 content are presented in Fig. 27.21 [27.134].As noted in Sect. 27.2.2, it is the increase in the di-electric constant that increases the capacitance of anassociated MOS structure. Thus, for a SiON film withk D 7, a 2 nm SiON film would ideally exhibit electri-cal behavior (such as capacitance and leakage-currentbehavior) equivalent to a 1:1 nm SiO2 film, accordingto (27.8). The data in Fig. 27.21 implies that the index ofrefraction (at 635 nm) varies between n.SiO2/ D 1:46and n.Si3N4/ D 2, indicating that optical techniques

PartC|27.2


Band gap (eV)

SiO2 (%)

9

8

7

6

5

4

Dielectric constant

8

7

6

5

4

30 20 40 60 80 100

Fig. 27.21 Dependence of permittivity and insulator bandgap of SiOxNy with SiO2 content. (After [27.134], withpermission)

such as ellipsometry can provide very useful informa-tion for such films.

Like the SiO2/Si system, point defects have alsobeen studied for SiON films on silicon [27.135]. Lena-han and coworkers examined the role of strain at theinterface and the impact on the associated danglingbonds [27.136]. More recently, work on the effects ofhydrogen annealing has also examined the SiON sys-tem [27.137].

It is also noted that the SiON material system alsoexhibits useful diffusion-barrier properties. This prop-erty is utilized to inhibit uncontrolled dopant diffusionfrom the polysilicon gate electrode through the dielec-tric layer and into the channel region of transistors, forexample. The formation of SiON films from the reac-tion of NO or N2O with Si, as well as nitridation ofSi and SiO2 from N2 and NH3 exposure, has been ex-amined in detail and has been summarized in recentreviews [27.39, 70].

For transistor gate dielectric applications, a con-trolled variation in the depth concentration profile for Nis often required throughout the dielectric to maintainthe improved device reliability and mobility associ-ated with SiON thin films [27.27]. An example ofsuch N profiles is shown in Fig. 27.22, where a some-what reduced N content is noted in the vicinity of theSi channel/dielectric interface relative to that near the

N concentration (with respect to O in SiO2)

Distance from Si /SiO2 interface (nm)0

0.09

0.06

0.03

0.00

1 2

Si/SiO2interface

SiO2/poly-siliconinterface

NO/O2/NO800 C/5', 500 C/52', 900 C/5'

Si

4.0 nm

SiO2 Polysilicon

N

N

3 4

Fig. 27.22 N concentration depth profiles for tailoring theoverall dielectric constant and materials properties ofa SiON layer. (After [27.36], © 1999 Elsevier, with per-mission)

dielectric/poly-Si gate interface [27.36]. Such profilesare thought to control effects such as interfacial strainand roughness (which can degrade mobility) and inhibitdopant out-diffusion from the gate electrode. Incorpora-tion of N in thin dielectric films using plasma processeshas been studied extensively [27.132, 138–142].

Given the various leakage-current constraints af-forded by power limitations and reliability, the scalingof SiON appears to be limited to teq � 1 nm, cor-responding to the 65 nm node for high-performancemicroprocessor products [27.7]. As a result, the incor-poration of alternative high-k dielectric materials hasbeen achieved for scaled transistors over the last sev-eral years.


C|27.2

Table 27.3 Desirable properties for high-k gate dielectrics (65 nm node)

Physical property Value/criteria Electrical property Value/criteriaPermittivity 15�25 Equivalent oxide thickness < 1 nmBand gap > 5 eV Gate leakage current

(low power)< 0:03A=cm2

Band offset > 1:5 eV Gate leakage current(high performance)

< 103 A=cm2

Thermodynamicstability to 1000 ıC

When in direct contact with Si channel CV frequency dispersion Minimal (meV)

Compatibility withmetal electrodes

Mimimized extrinsic (pinning) defects CV hysteresis Minimal (meV)

Morphology control Resistance to interdiffusion of constituents,dopants, and capping metals

VT (VFB) shift (fixed charge,defects, trapping, etc.)

Minimal

Deposition process Suitable for high-volume production Channel mobility Near SiO2

universal curveEtching Suitable control for patterning after process-

ing/annealingInterface quality Near SiO2

Dit � 5�1010 =cm2 eV

Table 27.4 Comparison of relevant properties for selected high-k candidates. Key: mono. = monoclinic; tetrag. = tetrag-onal

Material Dielectric constant (k) Band gap EG (eV) �EC (eV) to Si Crystal structure(s) (400�1050 ıC)SiO2 3:9 8:9�9:0 3:2�3:5b AmorphousSi3N4 7 4:8a � 5:3 2:4b AmorphousAl2O3 9 6:7h � 8:7 2:1a � 2:8b Amorphous�

Y2O3 11d � 15 5:6�6:1d 2:3b CubicSc2O3 13d 6:0d CubicZrO2 22d 5:5a � 5:8d 1:2a � 1:4b Mono., tetrag., cubicHfO2 22d 5:5d � 6:0 1:5b � 1:9c Mono., tetrag., cubicLa2O3 30 6:0 2:3b Hexagonal, cubicTa2O5 26 4:6a 0:3a,b OrthorhombicTiO2 80 3:05�3:3 � 0:05b Tetrag. (rutile, anatase)ZrSiO4 12d 6d � 6:5 1:5b Tetrag.HfSiO4 12 6:5 1:5b Tetrag.YAlO3 16� 17d 7:5d ��

HfAlO3 10e � 18g 5:5�6:4f 2�2:3f ��

LaAlO3 25d 5:7d ��

SrZrO3 30d 5:5d ��

HfSiON 12�17i,j 6:9k 2:9k Amorphous

� (� -Al2O3 phase) has been recently reported [27.143], �� Onset of crystallization depends upon Al content,a [27.144], b [27.145–147], c [27.148], d [27.149], e [27.150], f [27.148], g [27.151], h [27.152], i [27.153], j [27.154], k [27.155]

27.2.5 High-k Dielectrics

High-k dielectrics have now been incoprorated to fur-ther enable scaling of transistor (and memory capacitor)technology. In the context of the industry roadmap, theterm high-k dielectric more generally refers to materialswhich exhibit dielectric constants higher than the SiONfilms (k � 7) described above.

Desirable Properties for High-k DielectricsMany materials systems were originally under consid-eration as potential replacements for SiO2 and SiOxNy

as the gate dielectric material for sub-100nm (CMOS)

technology. A systematic consideration of the requiredproperties of gate dielectrics indicates that the keydesirable properties for selecting an alternative gate di-electric include: permittivity and the associated bandgap/alignment to silicon as well as mobility, thermo-dynamic stability, film morphology, interface quality,compatibility with the current or expected materialsto be used in processing for CMOS devices, processcompatibility, and reliability. The desirable proper-ties are summarized in Table 27.3. Reviews of thedeveloping field and recent research on high-k di-electric materials candidates are available [27.14, 156,157].

PartC|27.2


Optical bandgap (eV)

Dielectric constant5 40

10

9

8

7

6

5

4

3

20 10 15 20 25 30 35

SiO2 Al2O3

Y2O3

ZrSiO4

YAlO3MgO

CaO

Si3N4

Gd2O3SrO

ZrO2

GdScO3

SmScO3

Sm2O3SrZrO3

LaLuO3

LaAlO3

Sc2O3

HfO2

Fig. 27.23 Band gap versus dielectric constant for a num-ber of dielectric materials. (After [27.149], MRS Bulletin,with permission)

Many gate dielectric materials appear favorablein some of these areas, but very few materials arepromising with respect to all of these properties. In-deed, many of these desirable properties are interre-lated. Many of these materials have been examinedover the last 20 years for capacitor applications, forexample. With the introduction of Hf-based (and Zr-based) gate dielectrics in research in the mid to late1990s [27.158–163] and then announced by the indus-try for 45 nm node production in 2007 [27.164, 165],it is well known that the industry has widely adoptedHf-based oxides, largely based upon the desirable prop-erties mentioned above. Table 27.4 summarizes some ofthe measured or calculated properties associated withvarious high-k dielectric material constituents. Onenotes the tradeoff between the band gap (and thereforethe conduction/valence-band offsets to those of Si) forthese dielectrics and the associated dielectric constant,as seen in Fig. 27.23 [27.149].

The compatibility of alternative dielectrics withmetal gate electrodes is also an important consid-eration [27.14, 30, 166]. The interfacial reactions be-tween some gate electrode metals and gate dielectricis thought to lead to extrinsic states due to Fermi-level pinning, which shifts the threshold voltages fortransistors to a fixed value. Another clear challenge iscompatibility with other gate-first process steps that en-tail substantial thermal budgets (� 1000 ıC, 10 s) forconventional CMOS. Indeed, it was found that the de-velopment of a replacement gate last process was keyfor high-k dielectric integration in high-volume man-ufacturing [27.1]. A key innovation in the deposition

Insulator thickness (nm)

Dielectric constant2 100

20

10

4

2

14 10 20 40

Worse than SiO2

SiO2

Good!

Too muchtunneling current

30

25

2220

1817

1615.5

Fig. 27.24 Contours of constant scale length, which is pro-portional to the transistor gate length, versus dielectricconstant and insulator thickness, showing the useful de-sign space for high-k gate dielectrics. Data points are roughestimates of the tunneling constraints for various high-k in-sulators. The depletion depth is assumed to be 15 nm. Theuseful design space will shrink with decreasing depletiondepth. (After [27.21], © 2004 IEEE, with permission)

process for the high-k dielectric was also employed:atomic layer deposition (ALD). This deposition processenables atomic layer conformaility over device struc-tures – a key requirement for scaled planar and 3-Dtransistor (and trech capacitor) geometries utilized cur-rently [27.1].

Mobility Degradation for Transistorswith High-k Dielectrics

In the case of many of the alternate gate dielectricmaterials (mainly metal oxides) currently under consid-eration, the polarizability of the metal–oxygen (ionic)bond is responsible for the observed low-frequency per-mittivity enhancement. Such highly polarizable bondsare described to be soft relative to the less polariz-able stiff Si�O bonds associated with SiO2. Unlikethe relatively stiff Si�O bond, the polarization fre-quency dependence of the M�O bond is predicted toresult in an enhanced scattering coupling strength forelectrons with the associated low-energy and surfaceoptical phonons. This scattering mechanism can there-fore degrade the electron mobility in the inversion layerassociated with MOSFET devices. A theoretical ex-amination of this effect is provided by Fischetti et al.where calculations of the magnitude of the effect indi-cate that pure metal–oxide systems, such as ZrO2 andHfO2, suffer the worst degradation, whereas materialswhich incorporate Si�O bonds, such as silicates, farebetter [27.167]. In that work, it is also noted that the

Dielectric Materials for Microelectronics 27.3 Isolation Dielectrics 635Part

C|27.3

presence of a thin SiO2 interfacial layer between theSi substrate and the high-k dielectric can help boostthe resultant mobility by screening this effect, althoughthe maximum attainable effective mobility is still be-low that for the ideal SiO2/Si system. These researchersfurther suggest that the effect is also minimized by theincorporation of Si�O in the dielectric, as in the caseof pseudo-binary systems such as silicates. Indeed, theutilization of a thin, Si-oxide rich interface has demon-strated several advantages, including a higher qualityhigh-k/Si interface [27.1].

At this time, work on higher-k dielectric materi-als are under exploration to enable the roadmap targetspresented in Table 27.1. Combinations of ALD high-k layers are often employed to increase the overallgate stack capacitance, while minimizing the thicknesswithin the constraints for leakage current [27.1].

It is also important to note that most of the high-kmetal oxides listed in Table 27.4 crystallize at relativelylow temperatures (T � 500�600 ıC). An exception isAl2O3 where crystallization in thin films is observed atT � 800 ıC [27.168]. In the case of Hf–silicates, filmmorphology (viz. suppression of crystallization) anddiffusion-barrier properties can be controlled throughthe incorporation of N, as in the case of SiO2 [27.153,160–162, 169, 170].

Suppression of crystallization is also observed foraluminates (depending upon the Al content) [27.171],

but there are fewer studies of interdiffusion with the Sisubstrate available at this time. As noted above how-ever for the case of Al2O3 thin films, Al penetration intothe Si substrate has been reported upon high tempera-ture thermal annealing budgets appropriate for dopantactivation [27.172]. Such penetration could be a con-cern for any high-k dielectric incorporating Al as wellif a high temperature gate stack processs is employed.

The morphology of the dielectric film may also im-pact on the propensity for capping layer constituents(from metal gate material layers) to diffuse through thestack as well. Metal gate materials can include well-known minority-lifetime killers such as Ni (in NiSi) aswell as tunable-work-function alloys and layers [27.30,166, 173, 174]. The potential for the interdiffusion ofmetals into the channel region is clearly undesirable.

The limits of a useful high-k dielectric constantvalue have also been examined. For example, the studyby Frank et al. (Fig. 27.24) suggests that there exista range of useful permittivity values as planar CMOStransistor structures are scaled [27.21]. It is noted thatthe physical thickness of the gate insulator should beless than the Si depletion length under the channel re-gion, and that this results in a limited design space thatenables further device scaling. Again, one notes thatthe dielectric constant cannot be arbitrarily increasedwithout careful consideration of the complete transistordesign.

27.3 Isolation Dielectrics

Dielectrics are also employed to electrically isolatevarious regions of an integrated-circuit technology.The dominant material for these applications is SiO2.A method commonly employed to obtain such isola-tion in larger-scale IC technologies (generally with gatelengths larger than 0:25�m) is the so-called local ox-idation of silicon (LOCOS) technique, where regionsof Si between various components are preferentially(thermally) oxidized [27.16, 27]. Such isolation oxidesare typically several hundred nanometers thick and thetapered shape of the edge of the LOCOS isolation ox-ide near the transistor gate dielectric and source/drainregion (often referred to as the bird’s beak) is an im-portant region to control during the device fabricationat these gate lengths. Thinning of the dielectrics in thisregion results in breakdown reliability concerns, as theelectric fields in this region can be quite high. A re-oxidation process is often performed to improve thethickness and reliability of the SiO2 in this region aswell.

Scaling ICs beyond this gate-length regime howeverhas required the placement of isolated regions utilizingdeposited SiO2 trench structures, as seen in Fig. 27.6.As summarized by Wolf, extensive work has been doneto control the shape of the trench walls and the SiO2

layer initially formed on these walls. Chemical va-por deposition methods are normally utilized for thedielectric deposition as this approach provides supe-rior conformality in the trench structure. Filling thetrench without void formation, controlling film stress,and chemical mechanical polishing properties are alsoimportant aspects that must be addressed in the fabri-cation process [27.7, 27]. Scaling of integrate circuitswill result in a decrease of the area available for theseisolation trenches, and so the increasing aspect ratioof the trench depth to width requires considerable at-tention in regard to trench filling. The control of theshape of the top corner regions of the trench structuresis also an area of concern due to high-field reliabil-ity as well as the formation of essentially a parasitic

PartC|27.4


edge transistor. Initially, thermal oxidation methodswere employed to round off the shape of the corner,but further scaling will require etch processing meth-ods.

The fabrication of transistor source/drain regionsutilizing implantation processes also utilizes a dielec-tric spacer layer that surrounds the transistor gate re-gion (Fig. 27.6). This spacer provides isolation betweenthe gate and source/drain regions, and also permits thecontrol of the depth (and therefore profile) of the im-

planted dopant species – a so-called self-aligned dopantimplantation process. Dielectrics used for spacer tech-nologies include deposited SiO2 and Si3N4, and theextent of the spacer dimensions from the gate is animportant device parameter to control [27.16]. Fur-ther scaling of transistor structures will likely resultin the need for elevated source/drain regions, and soprocess compatibility of the spacer material with thesource/drain formation processes and high-k dielectricswill become an important consideration [27.7].

27.4 Capacitor Dielectrics

Capacitors are employed in a variety of integrated cir-cuits including storage (memory) circuit elements andinput/output coupling circuitry. Clearly, dielectrics arecritically important in this application. In contrast to theMIS structure associated with transistors, capacitors arepassive devices incorporating a metal–insulator–metal(MIM) structure. Early electrodes were composed ofdegenerately doped Si while more recent work focuseson integrating metals for modern devices.

27.4.1 Types of IC Memory

A dominant memory technology for the IC indus-try includes dynamic random-access memory (DRAM)in which capacitors play the essential role of stor-ing charge, and thereby useful information. This typeof memory element requires refreshing in order tomaintain useful information, and the rate of refresh isfundamentally related to the dielectric associated withthe capacitor structure and leakage of charge from thatcapacitor. As a result, this class of memory devicesis called volatile. In contrast, a static random-accessmemory (SRAM) nonvolatile memory element requireda capacitor which stores charge without the refresh re-quirement, and can preserve charge for many years.Again capacitor design must include the considerationof the dielectric [27.25].

In addition to DRAM capacitors, other types ofcapacitors are used in the back end of the transistorflow. These devices are MIM capacitors, and they typi-cally reside between levels of metal interconnects, andserve as decoupling or radio-frequency (RF) capaci-tors for input/output functions. For these applications,the capacitance density is still of critical importance,but other factors must be considered, such as the lin-earity of the capacitance as a function of voltage andtemperature. Memory is also more frequently becom-ing embedded with logic, enabling faster on-chip stor-age.

27.4.2 Capacitor Dielectric Requirementsin View of Scaling

In brief, scaling the capacitor dimensions requiresa tradeoff between the amount of stored charge re-quired for a reliable memory element and the areaoccupied by the capacitor (and the associated transistorsfor the memory cell). From generation to generationof devices, the amount of stored charge has been keptroughly constant (� 30 fF=cell), even though dimen-sional scaling occurs, for bit detection (sense amplifier),retention and reliability reasons [27.27, 175].

As noted in (27.6) for a simple parallel-plate capac-itor, the area associated with the capacitor as well as thedielectric permittivity play an important role. Maintain-ing the required capacitance with scaling was (and willbe) accomplished by increasing the capacitor area, fora suitable dielectric thickness where leakage currentsare severely limited; this can be accomplished by uti-lizing three-dimensional capacitor structures producedin the Si bulk, such as deep-trench capacitors [27.175,176]. Clever and intricate processing methods to in-crease the capacitor area were adopted for severalgenerations for well-established SiO2 and Si–oxynitridedielectric capacitor materials, such as the implementa-tion of hemispherical-grain (HSG) poly-Si and crownstructures (Fig. 27.25). Eventually, practical concernsabout cost and device yield make manufacturing suchstructures problematic. Thus, substantially increasingthe dielectric constant of the insulating material wasconsidered, and less-complicated structures can be fab-ricated. At this point, both stacked and trench capacitorstructures are dominant in the industry. Indeed, the abil-ity to fabricate deep-trench structures will help guidethe need for the incorporation of alternative dielectrics.These structures often require the use of chemical va-por deposition (CVD) methods to ensure conformalityover the stacked structure topography or deep withintrenches that have large aspect ratios. More recently,

Dielectric Materials for Microelectronics 27.4 Capacitor Dielectrics 637Part

C|27.4

0.4 m 0.37 m

0.25 m

Stacked8 fF/cell

Crown15 fF/cell

Disk26 fF/cell

Trench

HSG stacked(X2)16 fF/cell

HSG crown30 fF/cell

Fig. 27.25 Assorted capacitor structures employed in IC technology. (Courtesy of S. Summerfelt)

atomic-layer CVD processes have been examined forthis purpose as well. Although capacitors do not haverequirements regarding lateral transport of carriers, astransistors do, capacitors have much more rigorouscharge-storage-capacity requirements when they serveas memory elements. This additional constraint resultsin projected limitations.

27.4.3 Dielectricsfor Volatile Memory Capacitors

Capacitor dielectric properties for dynamic random-access memory (DRAM) applications have been impor-tant since these devices were introduced commerciallyin the early 1970s for volatile memory [27.177]. Fazanprovides some rules of thumb that provide guidancefor the selection of desirable materials (and electrical)properties for DRAM capacitor dielectrics [27.175].In addition to the desire to maintain the storage ca-pacitance around 30 fF=cell (in spite of shrinking di-mensions), leakage of charge from the storage capac-itor must be kept to a current density of less than0:1�A=cm2 so that less than � 10% of the capacitorcharge is lost during the associated refresh (recharge)cycle. Scaling the DRAM cell size has necessarily re-sulted in the consideration of a variety of dielectricmaterials for some time [27.7, 25, 27].

SiO2 and SiOxNyThe earliest DRAM planar capacitors utilized SiO2

as the dielectric. Subsequent scaling into the Mbitregime required an increased capacitance density, andthus a higher dielectric constant. So-called oxide/nitride(ON) or oxide/nitride/oxide (ONO) dielectric stackswere incorporated [27.16]. As the names imply, the di-electric consisted of a stack of SiO2 and Si3N4 layers.The incorporation of the Si nitride layer, typically by

a deposition method such as chemical vapor deposition,results in an overall increase in the dielectric constantof the stack. Scaling has required the consideration ofhigh-k materials in currrent DRAM technologies.

ZrO2/Al2O3/ZrO2Scaling metal-insulator-metal capacitors required thedevelopment of alternative dielectrics (e.g., Al2O3 andZrO2) and their integration into DRAM processes [27.7,178]. The stack provides useful dielectric constants inthe range of k � 20�50 for adequate charge storage andleakage performance.

PerovskitesConsiderable effort has also been exerted in the searchfor CMOS-compatible ultra high-k dielectrics. Suchmaterials are envisioned to be required for capacitorscaling at and beyond the 10 nm node [27.7]. Perovskitematerials, with a k > 50�100 have been a focus forthis application. The movement of the Ti atom (ion) inthe perovskite lattice structure results in a substantialcontribution to the polarization of this materials sys-tem. Utilization of perovskite has required the use ofnoble-metal electrodes including Pt, Ru (RuO2) and Irto control interfacial reactions. As a result, considerableprocess complexity is introduced into the manufactur-ing process.

27.4.4 Dielectrics for Nonvolatile Memory

As the name implies, nonvolatile memory devices re-tain their state whether power is applied to the deviceor not. A thorough description of such devices is pro-vided by Hori [27.16]. For example, the electricallyerasable programmable read-only memory (EEPROM)device requires an erase operation prior to programming(writing) new data to the device. To accomplish this,

PartC|27.4


Table 27.5 Comparison of non-volatile memory technologies. (After [27.179])

Specifications FRAM SRAM EEPROM FlashNon-volatileRetains data w/o power

Yes No Yes Yes

Write speed (13KB) 10ms < 10ms 2 s 1 sAverage active power (�A=MHz)16 bit word access by the CPU

100 < 60 > 50 000 230

Write endurance 1015 Unlimited 100 000 10 000Soft errors Below measurable limits Yes Yes YesBit-wise programmable Yes Yes No NoUnified memoryFlexible code and data partitioning

Yes No

a stacked-gate MOS structure is utilized where the in-termediate gate is embedded in a dielectric – a so-calledfloating gate. The placement of a higher electric fieldto permit Fowler–Nordheim tunneling through such di-electrics to the floating gate is utilized to program arraysof these elements – called flash memory. Scaling andthe reliability required for such nonvolatile memory de-vices has required the evolution from using SiO2 toSiOxNy.

SiO2 and SiOxNyFor flash memory elements, the formation of nitridedSiO2 enables a suitable dielectric for reliable operation.The nitridation process, as described earlier, entails theexposure of an SiO2 dielectric to anneals with N2, NH3,or N2O (or combinations of these), often under rapidthermal annealing conditions. Details of this processhave been summarized by Hori [27.16]. Subsequent re-oxidation of the dielectric is also employed to improvereliability properties. So-called silicon oxide nitride ox-ide silicon (SONOS) structures are under examinationto improve the scaling limitations of the dielectric thick-ness and tunneling properties [27.181].

Further scaling of transistors presents significantchallenges for flash memory. The thickness of the di-

P

V

+Ps

+Pr–Vc

–Pr +Vc

–Ps

Fig. 27.26 Polarization–voltage curve for a ferroelectricmaterial. (After [27.180], © 2004 IEEE, with permission)

electric is again a key constraint given the need forreliable operation under high-electric-field conditions.Memories based on Si nanocrystals embedded withinSiO2 are currently under development to address thischallenge [27.182].

FerroelectricsFerroelectric materials, such as PbZr1�xTixO3 (PZT) orSrBi2Ta2O9 (SBT) have been utilized for some timeas dielectrics for non-volatile memory elements basedupon the ferroelectric effect [27.24]. In storage capaci-tors incorporating such materials, the polarization stateof the ferroelectric is preserved (once poled) without thepresence of an electric field [27.23]. This state is thensensed by associated circuitry and can therefore be usedas a memory device. The technology has been success-fully incorporated in smart card applications as well asmicrocontroller embeded random access memory – socalled ferroelectric RAM (FeRAM or FRAM) [27.179].A comparison of various memory technologies is pro-vided in Table 27.5.

Principles. Ferroelectricity describes the spontaneousalignment of dipoles in a dielectric as the result of anexternally applied electric field. This alignment behav-ior has thermal constraints in that heating the dielectricabove the Curie temperature results in a phase trans-formation to a paraelectric state. Therefore, capacitorsand circuits which utilize the ferroelectric effect mustcontain materials that have a relatively high Curie tem-perature compared to that experienced during operationand reliability testing (generally > 200 ıC). As shownin Fig. 27.26, the polarization response of these ma-terials to an externally applied electric field exhibitsa hysteresis behavior [27.180]. (This behavior is analo-gous to that observed in ferromagnetic materials, hencethe name. Note however that ferroelectric materialscontain no iron.) Upon increasing the voltage acrossthe ferroelectric above a coercive value (Vc), the po-larization of the material is limited to the spontaneousvalue (Ps), corresponding to maximum domain align-

Dielectric Materials for Microelectronics 27.5 Interconnect Dielectrics 639Part

C|27.5

A

O

B

Fig. 27.27 Perovskite ABO unit cell showing motion of theB ion in the cell among the equilibrium positions, result-ing in ferroelectric polarization behavior. (After [27.180],© 2004 IEEE, with permission)

ment. Removal of the electric field results in a decreaseof the polarization to the remnant value (Pr), which canbe sensed accordingly. The time required for the polar-ization to be switched is on the order of nanosecondsfor these devices. Moreover, this can be accomplishedin low-power circuits, making these materials attractive,in principle, for scaled CMOS.

Materials. In addition to the perovskite PZT andSBT materials mentioned above, other materials in-vestigated for nonvolatile memory applications in-clude BaTiO3, PbTiO3, Pb1�xLaxZr1�yTiyO3 (PLZT),PbMg1�xNbxO3 (PMN), SrBi2Nb2O9 (SBN), andSrBi2.Ta1�xNbx/2O9 (SBTN). These materials gener-ally have the cubic structure ABO3 shown in Fig. 27.27,

with the larger (A) cations in the corner of the cubic unitcell, and the smaller (B) cations (e.g., Ti, Zr, Mg, Nb,Ta) located in the center of the unit cell. The oxygen an-ions are located at the face-centered-cube positions. Thedistortion of the unit cell in response to the externallyapplied electric field results in the observed polariza-tion. In particular, the movement of the B cation (e.g.,Ti) in the associated lattice between the equilibriumpositions results in substantial distortion and thereforepolarization [27.24, 180].

Issues for Ferroelectric Materials. Substantial re-search has been performed to understand the relia-bility issues associated with ferroelectric memory de-vices, as their integration tends to occur at the backend of (fabrication) line (BEOL) stage of the typicalchip fabrication process. The retention of the polar-ization state is one area of investigation. It is ob-served that the polarization state decreases slowly overtime (log-time decay behavior), even in the absenceof an electric field, and the reasons are still not un-derstood. Another area of concern is imprint, wherea polarization state, if repeatedly poled to the samestate, becomes preferred. Subsequent switching to theopposite state can result in relatively poor retentiontimes. Again, the physical mechanism associated withthis phenomenon is poorly understood. The role ofhydrogen exposure is another area of investigation,where exposure of ferroelectric random-access memory(FeRAM) elements to hydrogen, commonly from form-ing gas during CMOS back-end processing, can resultin the suppression of the remnant polarization [27.183–185]. Barriers for hydrogen (and moisture) permeationinto the ferroelectric, such as ALD Al2O3, are impor-tant for reproducible and reliable operation [27.186–188].

27.5 Interconnect Dielectrics

As noted in Fig. 27.1, the performance of the inte-grated circuit, as measured by the time delay for signalpropagation, also depends upon the interconnectionsbetween circuit elements. The scaling of CMOS has re-sulted in a substantial increase in interconnect metallines throughout the IC chip, which make a majorcontribution to the delay time. The industry segmentsthese levels into local (interconnection between neigh-boring devices), intermediate (metal 1 interconnectionbetween neighboring circuits), and global (interconnec-tion across the chip), as shown in Fig. 27.28. A crosssection of a 65 nm-node IC is shown in Fig. 27.29whereeight layers of metallization and the associated dielec-tric isolation are evident.

As discussed in Sect. 27.1.1, the RC time de-lay for the interconnect contribution to performancecan be attributed to the metal lines and their isola-tion dielectrics (see Fig. 27.1). The resistivity of thelines has been reduced in the industry by recentlyadopting copper metallization processes in lieu of alu-minium metallization in 1998. Further reductions inthe delay time then require the consideration of thedielectric between the lines, as these essentially forma parasitic capacitor structure, and therefore low-k di-electrics are required. Examples of such interconnectdielectrics are presented in Table 27.6. Reviews of inter-connect technology for CMOS are available [27.189].It is noted that for the global interconnect level, new

PartC|27.5


Global(up to 5)

Inter-mediate(up to 8)

Metal 1

Passivation

Dielectric

Etch stoplayer

Dielectriccappinglayer

Copperconductorwith barrier/nucleationlayer

Pre metaldielectricTungstencontact plug

Metal 1 pitch

Wire

Via

Fig. 27.28 Schematic of a typical chip cross section showing keyinterconnect metallization and dielectric layers. (From [27.7])

Metal-8

Inter-connectdielectrics

Metal-7

Metal-6

Metal-5

Metal-4

Metal-3Metal-2Metal-1

Fig. 27.29 Cross section of a 65 nm node IC chip from2005 showing eight levels of metal interconnects isolatedby low-k dielectrics. (Courtesy of Intel)

concepts such as RF or optical communication, willlikely be needed to address extreme CMOS scal-ing.

27.5.1 Tetraethoxysilane (TEOS)

For many years, CVD-deposited SiO2 provided ade-quate isolation for interconnection of ICs. This was

Table 27.6 Interconnect dielectric materials. (After [27.7,27])

Dielectric constant Material3:5�3:7 FSG3:0�3:6 Polyimides2:7�3:1 Spin-on glass2:6�2:9 Organo-silicate glasses (OSGs)2:6�2:8 Parylene-based polymers2:5�3:2 Methyl/hydrogen silsesquioxane

(MSQ/HSQ)1:8�2:4 Porous MSQ, parylene-based polymers1:1�2:2 Silica aerogels1:5�2:2 Silica xerogels

frequently accomplished through the deposition oftetraethoxysilane (TEOS) and subsequent densificationthermal treatments to render a dielectric constant ofk � 4. Films produced in this manner were relativelyeasy to process and provided good mechanical strength.The incorporation of fluorine into these films (fluori-nated silicate glass or FSG) succeeded in a reductionof the dielectric constant to k � 3:5�3:7 after consid-erable efforts. As F is among the most electronegativeelements, the incorporation of F into the silica matrixrenders the film less polarizable due to Si�F bond for-mation, and therefore results in a lower permittivity.Scaling CMOS however has driven the industry to con-sider interconnect dielectric materials with k � 4.

27.5.2 Low-k Dielectrics

As seen in Figures 27.28 and 27.29, several levels ofdielectrics must be incorporated with the metallizationschemes associated with ICs. As can be seen, dielectricsutilized in this back end of (fabrication) line (BEOL)portion of the IC fabrication process are also segmentedinto pre-, inter- and intra-metal dielectrics. Addition-ally, dielectric layers are employed to facilitate etchingcontrol for Cu metal patterning of the various intercon-nection lines. This requires materials integration withbarrier layers (that control Cu diffusion), etch stop lay-ers, CMP (chemical mechanical polishing) stop layersas well as overall mechanical stability. Additionally, forthe local and metal 1 layers, the future incorporation ofmetal gate and/or NiSi materials may require extensivelimitations on processing temperatures (< 500 ıC).

Several materials have been explored for the low-kapplication, and some of these are summarized in Ta-ble 27.5 [27.7, 27]. Most consist of polymeric (low-Z)materials with varying porosity to enable a sufficientlylow dielectric constant for interconnect applications. Atthis point, films are deposited by either CVD or spin-on methods. Desirable properties for low-k dielectricsinclude thermal stability (to � 500 ıC), mechanical

Dielectric Materials for Microelectronics References 641Part

C|27

stability (to withstand packaging), electrical isolationstability/reliability (similar to SiO2), chemical stabil-ity (minimal moisture absorption, resistance to pro-cess chemicals, resist compatibility), compatibility withBEOL materials (e.g., diffusion barriers) and processes(etching, cleaning, post-metallization and forming-gasanneals, chemical mechanical polishing, etc.) and of

course low cost. As noted by Wolf, thermal propertiesof low-kmaterials are important for effective power dis-sipation in high-performance applications. Accordingto the 2013 ITRS Roadmap, a lack of progress on low-k dielectric scaling presents a significant challenge tothe industry where innovative solutions would be verywelcome [27.7].

27.6 SummaryIt should be evident that IC technology is critically de-pendent upon suitable dielectrics throughout the entirechip. Materials properties, and their resultant electricalproperties, must be carefully evaluated throughout theresearch and development process associated with inte-grated circuit technology.

Recent years and roadmap predictions clearly placean emphasis on the development of new materials forthe various dielectrics employed to achieve scaling. Re-

searchers and technologists engaged in this endeavormust be able to span several disciplines to enable thesuccessful integration of these new dielectric materials.

Acknowledgments. RMW gratefully acknowledgesthe many discussions and hard work of his colleaguesand students engaged in gate-stack research. This workis supported in part by the Erik Jonsson DistinguishedChair at the University of Texas at Dallas.

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