chi han charge multiplexing

Charge Locking Quantum Multiplexer and Triple Addressing

System

CHI HAN CHONG

21/5/2014

Outline• Quantum MUX

• Double charge locking in two-way MUX

• Attempts of adding a top gate

• Polyimide

• Three-way MUX

• Split gate test

Quantum Multiplexer

• Path selector [1]

• Single input quantum device with

many tunable outputs

Source: Al-Taie et al, APL 102, 243102 (2013)

[1] Debashis D.2010. Basic electronics. India: Dorling Kindersley Pvt Ltd. Pg 557

Quantum multiplexer

• Ward et al - measurement of multiple quantum devices in a single chip using Si/Ge QDs [2]

• Al-Taie et al – 256 split gates on a single GaAs/AlGaAs chip [3]

• Hornibrook et al – Frequency multiplexing → read spin qubits [4]

[2] D. R. Ward, D. E. Savage, M. G. Lagally, S. N. Coppersmith and M. A. Eriksson, Appl. Phys. Lett. 102, 213107 (2013)[3] H. Al-Taie, L. W. Smith, B. Xu, P. See, J. P. Griffiths, H. E. Beere, G. A. C. Jones, D. A. Ritchie, M. J. Kelly, & C. G. Smith, APL 102, 243102 (2013)[4] J. M. Hornibrook, J. I. Colless, A. C. Mahoney, X. G. Croot, S. Blanvillain, H. Lu,A. C. Gossard, and D. J. Reillyy, arXiv1312.5064 (2013)

Advantages

• 1 cooldown , many measurements [3]

• Automated measurements → save time & £ £

• Same environment

Two –way charge locking MUX

- Output proliferation of 2n

- Locking occurs by pinching off quantum wires (QW)

2DEG under Mesa/QW

Gold leadneg. bias

High e- density No e-

Locking processes for a four output 2-wayMUX

Router Mesa

Mesa Skeleton

Device Mesa

Detection

Credits: Dr Reuben Puddy

Locking processes for a four output MUX

Router Mesa

Mesa Skeleton

Device Mesa

Detection

Polyimide insulator (Shield the 2DEG from elec. potential)

Polyimide insulator

mesa

Ohmic contact

Gold leads

Devgate

DS

Surface gate

Addressing gates

Router gate

locking gate

Polyimide insulator

mesa

Ohmic contact

Gold leads

Ramp to - 1V

0V

0V

0V

0V

Source Drain

Devgate

Surface gate

Min pinch ≈ -0.4V

Polyimide insulator

mesa

Ohmic contact

Gold leads

DS

0V

0V

-2V

-0.2V

-2V

-0.5V

Caveat : Leads can’t be positive than 2DEG by 0.4V

Polyimide insulator

mesa

Ohmic contact

Gold leads

DS

0V

-0.5V

-2V

-2V0V

-0.2V

Ramped up in steps together

Polyimide insulator

mesa

Ohmic contact

Gold leads

DS

-1V

-0.5V

-2V

-2V

-1V

-1V

Polyimide insulator

mesa

Ohmic contact

Gold leads

DS

-1V

0V

-2V

-2V

-2V

-2V

• Aim: Check the rate of charge leakage

• Vary Router gate voltage

• Isolated & observe source

Locking Stability Plot for 4-way MUX

Polyimide insulator

mesa

Ohmic contact

Gold leads

DS

-1V

-2V

-2V

-2V

-2V

Less potential, less depletion, more current

Top gate

- Capacitive coupling : 2DEG & gates

- Coat Polyimide on MUX +gold top

- Increase capacitance of circuit→ more stability?

polyimide

Gold top

Credits: Dr Reuben Puddy- - - - - - - - - - - - - - -

+ + + + + + + + + + + + + Gold topPolyimideMUX

Polyimide insulator

mesa

Ohmic contact

Gold leads

Devgate

DS

Surface gate

Addressing gates

Router gate

Cured in oven at high T + dry N2

Polyimide insulator

mesa

Ohmic contact

Gold leads

Devgate

DS

Surface gate

Addressing gates

Router gate

Gold evaporated on Polyimide

Findings• Curing with gates: 275 oC +N2 (For Polyimde)

≥350oC

• Leaks if Tcure is low

Collaboration with Yousun

Findings• Polyimide can be removed :

- Set gas dial to ‘1’

- High Power

- Variable ashing rates,

600nm in 4, 300s ashes

Microwave asher

Credits: Joanna Waldie

Brown stains (only seen after gold deposition) ~50nm

Postulate:Burnt residue

Possible Solution:Low power, Progressively short ashing times

Three-way MUX

Credits: Prof Charles Smith Modified by: Dr Reuben Puddy

Vpinch for leads ≠ Vpinch for split gates

mesa

Ohmic contact

Gold leads

Polyimide insulator

Three-way MUX

Credits: Prof Charles Smith Modified by: Dr Reuben Puddy

0V

-1V

Three-way MUX

Credits: Prof Charles Smith Modified by: Dr Reuben Puddy

0V

-2V

Three-way MUX

Credits: Prof Charles Smith Modified by: Dr Reuben Puddy

-1V

-1V

Output proliferation 30.5(n-1)Vbias

Split-gate designs

- Need specific pinch off voltages

- 3 sizes(WxL): 800x400 nm , 800x800 nm, 800x1600 nm

W

L

Pinch off measurements

L=400nm Vp≈ -(0.973±0.002)V for I<1x10-7 L=800nm Vp ≈ -(0.830±0.002)V for I<1x10-7

L1600nm Vp ≈ -(0.764±0.002)V for I<1x10-7

Prob density

Split gates

Pinch off vs split gate length at fixed VSD

Vb = 10μV, RMS [5]

[5] Iqbal et al , J. Appl. Phys. 113, 024507 (2013)

Higher bias

No hysteresis

Why Vpinch differs with polarity?

• VSD (DC bias) steps up energy levels at source

• Gate bias → Barrier

• Polarity of VSD affects size of Vg – VSD energy gap

VSD

Potential /V

Vg

Ei

Ei+1

EF EF

Ej

Ej+1

Position/μm

Credits: Dr Reuben Puddy

Why Vpinch differs with VSD polarity?

• Larger difference in potential → higher barrier

VSD = -0.5

Potential /V

Vg = -1

EF EF

Ej

Ej+1

Position/μm

VSD = +0.5

EF‘

negative axis

Conclusion

• Pinch off voltage is dependent on L of split gate and VSD

• Adding split gates enable triple addressing

• Gate contacts undergo chemical changes at high T >300 oC

• Polyimide can be (almost) removed using a microwave asher

References• [1] Debashis D.2010. Basic electronics. India: Dorling Kindersley Pvt Ltd. Pg 557

• [2] D. R. Ward, D. E. Savage, M. G. Lagally, S. N. Coppersmith and M. A. Eriksson.2013. Integration of on-chip field-effect transistor switches with dopantless Si/SiGe quantum dots for high-throughput testing. [e-journal] Appl. Phys. Lett. 102, 213107 (2013)

• [3] H. Al-Taie, L. W. Smith, B. Xu, P. See, J. P. Griffiths, H. E. Beere, G. A. C. Jones, D. A. Ritchie, M. J. Kelly, & C. G. Smith.2013. Cryogenic on-chip multiplexer for the study of quantum transport tin 256 split gate devices. [e-journal] APL 102, 243102 (2013)

• [4] J. M. Hornibrook, J. I. Colless, A. C. Mahoney, X. G. Croot, S. Blanvillain, H. Lu,A. C. Gossard, and D. J. Reillyy.2013. Frequency Multiplexing for readout of Spin Qubits.[e-journal] arXiv1312.5064 (2013)

• [5] M. J. Iqbal, J. P. de. Jong, D. Reuter, A. D. Wieck and C. H. van der Wal.2013. Split-gate quantum point contacts with tunable channel length. [e-journal] J. Appl. Phys. 113, 024507 (2013)