combinational logic - basavaraj talawarbinary adder–subtractor 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1,...

Combinational Logic

Ch. 4. Mano & Ciletti.

Outline● Combinational Circuit Analysis● Design Procedure

– BCD to Excess-3 Converter

● Binary Adder – Subtractor– HA, FA, Carry Lookahead Generator

● BCD Adder● Binary Multiplier● Magnitude Comparator● Decoder, Boolean Functions using Decoders● Encoders● Multiplexers, Boolean Function Implementation● Three State Gates

Analysis

Analysis

Truth Table

Truth Table

Design Procedure● Code Conversion

– BCD to Excess-3 code

BCD toExcess-3BCD to

Excess-34

BCD_A E-34

Design Procedure● Code Conversion

– BCD to Excess-3 codeBCD to

Excess-3BCD to

Excess-34

BCD_A E-3

4

BCD to Excess-3 Code

BCD to Excess-3 Code

BCD to Excess-3● K-Maps for w, x, y, and z.

BCD to Excess-3

BCD to Excess-3

Binary Adder–Subtractor● Bit-wise Addtion:

– 0 + 0 = 0– 0 + 1 = 1– 1 + 0 = 1– 1 + 1 = 10

●

Binary Adder–Subtractor● 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and

1 + 1 = 10● Outputs: Sum and Carry bits

Binary Adder–Subtractor● 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and

1 + 1 = 10● Outputs: Sum and Carry bits● Half Adder: Combinational circuit to

add two bits

Binary Adder–Subtractor● 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1

+ 1 = 10● Outputs: Sum and Carry bits● Half Adder: Combinational circuit to

add two bits● Full Adder: Adds three bits (two

significant bits and a previous carry)

Binary Adder–Subtractor● 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10● Outputs: Sum and Carry bits● Half Adder: Combinational circuit to add two

bits● Full Adder: Adds three bits (two significant

bits and a previous carry)● Binary Adder for two n-bit numbers: n full

adders in cascade .

Half Adder

Half Adder

HalfAdderHalf

Adder

a

bsum

carry

Half Adder - TT

Half Adder

Half Adder

Full Adder● Inputs: Addend, Augend, Carry bits● Outputs: sum, carry

Full Adder● 3 Inputs: Addend, Augend, Carry bit● Outputs: sum, carry

HalfAdderHalf

Adder

a

bsum

carry_out

carry_in

Full Adder – TT

Full Adder – TT

Full Adder

Full Adder

Full Adder

S

Full Adder using Half Adders

● Half Adder Outputs

● Full Adder Outputs

Full Adder using Half Adders

C=x ' yz+xy ' z+xyz '+xyzC=x ' yz+xy ' z+xyz '+xyz

C=x ' yz+xy ' z+xyC=x ' yz+xy ' z+xy

C=z (x ' y+xy ' )+xyC=z (x ' y+xy ')+xy

Full Adder using Half Adders

Full Adder using Half Adders

Full Adder using Half Adders

Binary Adder● 1011 + 0011

Binary Adder● 1011 + 0011

4-bit Adder

4-bit Adder

Ripple Carry AdderRipple Carry Adder

4-bit Adder

Ripple Carry AdderRipple Carry Adder

Which is the critical path?Which is the critical path?

Carry Propagation● Rename HA outputs

Carry Propagation● Rename HA outputs

● FA outputs:

Carry Propagation● Rename HA outputs

● FA outputs: (Ci is the third input)

Carry Propagation

Carry Propagation

Carry Generation

Carry Generation

Carry Lookahead Generator

4-bit Carry Lookahead Adder

Binary Subtractor

Binary Subtractor

BCD Adder● Inputs: Two digits (0 – 9), Carry (0 –

1)● Max sum = 19 (9 + 9 + 1)● Use the 4-b Binary Adder● Convert the Binary output to BCD

BCD Adder

BCD Adder

+6 =

BCDAdder

Binary Multiplier● 2 bit Multiply: B1B0 x A1A0

●

Binary Multiplier● 2 bit Multiply: B1B0 x A1A0

●

Binary Multiplier● 2 bit Multiply:

B1B0 x A1A0

Binary Multiplier● 4b x 3b. B3B2B1B0 x A2A1A0

Binary Multiplier

● 4b x 3b. B3B2B1B0x A2A1A0

Magnitude Comparator● Compares two numbers A and B● Outputs: A > B, A = B, or A < B

ComparatorComparator

nA A=B

nBA<BA>B

Magnitude Comparator● Consider A3A2A1A0, B3B2B1B0

● A = B

Magnitude Comparator● Consider A3A2A1A0, B3B2B1B0

● A = B

Magnitude Comparator● Consider A3A2A1A0, B3B2B1B0

● A > B

Magnitude Comparator● Consider A3A2A1A0, B3B2B1B0

● A > B

Magnitude Comparator● Consider A3A2A1A0, B3B2B1B0

● A > B

● A < B

Magnitude Comparator

Decoders● n-to-m-line Decoder:

– n-bit Input; 2n bit Output

2-to-4-lineDecoder

2-to-4-lineDecoder

2A

D3

D2

D1

D0

Decoder – TT

Decoder – TT

Decoder

Decoder with Enable

2-to-4-lineDecoder

2-to-4-lineDecoder

2AD

3

D2

D1

D0En

Decoder with Enable

2-to-4-lineDecoder

2-to-4-lineDecoder

2AD

3

D2

D1

D0En

Decoder with Enable

2-to-4-lineDecoder

2-to-4-lineDecoder

2AD

3

D2

D1

D0En

Decoder with Enable

2-to-4-lineDecoder

2-to-4-lineDecoder

2AD

3

D2

D1

D0En

Decoder with Enable

2-to-4-lineDecoder

2-to-4-lineDecoder

2AD

3

D2

D1

D0En

Decoder with Enable

Boolean using Decoder● Decoder provides 2n minterms of n

input variables● Any Boolean function can be

expressed in sum-of-minterms● Any n-input, m-output combinational

circuit can be implemented with an n-to-2n-line decoder and m OR gates.

Full Adder using Decoder

Full Adder using Decoder

Encoders● Inverse of a decoder.● Encoder has 2n (or fewer) input

lines and n output lines

23-to-3-line Encoder

23-to-3-line Encoder

23-to-3-line Encoder

23-to-3-line Encoder

Priority Encoder● If two or more inputs are equal to 1

at the same time, input having the highest priority will take precedence.

Priority Encoder

Priority Encoder

Priority Encoder

Priority Encoder – Maps

Priority Encoder – Maps

Priority Encoder

Priority Encoder

Multiplexers● Selects binary information from one of

many input lines and directs it to a single output line.

● Selection of the input line is controlled by a set of selection lines– 2n input lines ==> n selection lines

● Also called Data Selector

Multiplexer

MultiplexerS Y

0 I0

1 I1

MultiplexerS Y

0 I0

1 I1

Y= I 0×S+ I1×SY= I 0×S+ I1×S

MultiplexerS Y

0 I0

1 I1

Y= I 0×S+ I1×SY= I 0×S+ I1×S

4-to-1 Multiplexer

4-to-1 Multiplexer

I0

I1

I2

I3

Y

s2

4-to-1 Multiplexer

I0

I1

I2

I3

Y

s2

4-to-1 Multiplexer

I0

I1

I2

I3

Y

s2

Y=S1S0×I 0+S1S0×I 1+S1S0× I 2+S1S0×I 3Y=S1S0×I 0+S1S0×I 1+S1S0× I 2+S1S0×I 3

4-to-1 MultiplexerI0

I1

I2

I3

Y

s2

Y=S1S0×I 0+S1S0×I 1+S1S0× I 2+S1S0×I 3Y=S1S0×I 0+S1S0×I 1+S1S0× I 2+S1S0×I 3

Quadruple two-to-one-line Multiplexer

A

BY

s

4

4

4

E

Boolean Function Implementation

● Boolean function of n variables– F(x,y,z)

● n–1 variables of the function are connected to the selection inputs– x, and y; for the function F(x,y,z)

● Remaining single variable is used for data input– z, z, 0, 1

Boolean Function Implementation

x y z F

Boolean Function Implementation

Boolean Function Implementation

Boolean Function ImplementationA B C D F

Boolean Function Implementation

Boolean Function Implementation

Three State Gates

Three State Gates

2-to-1-line Mux2-to-1-line Mux

Summary● Combinational Circuit Analysis● Design Procedure

– BCD to Excess-3 Converter

● Binary Adder – Subtractor– HA, FA, Carry Lookahead Generator

● BCD Adder● Binary Multiplier● Magnitude Comparator● Decoder, Boolean Functions using Decoders● Encoders● Multiplexer, Boolean Function Implementation● Three State Gates

Extra

Three State Gates

4-to-1-line Mux4-to-1-line Mux